SIGNAL TRANSMISSION DEVICE

WIPO Patent Application WO/2013/153922

A1

This invention is provided with: a modulation signal convertor (1) for generating, in accordance with transmitted data, a modulation signal that uses a Manchester code with a 50% duty cycle; a clock generator (6) for generating a clock, which is an amount of delay with respect to either the leading edge or the trailing edge of the modulation signal; and a data detector (5) for sampling the modulation signal in synchronization with the clock to generate received data. The modulation signal convertor (1), in order to generate a modulation signal in combination with a 50% duty cycle Manchester code, maintains the duty cycle at a constant 50% regardless of the transmitted data to prevent a DC offset in the reception system modulation signal. Therefore, the effect is that good communication quality is achieved with a simple circuit configuration without DC offset occurring in the reception system modulation signal.

TAJIMA KENICHI (JP)
KAWAKAMI KENJI (JP)
HIRAI AKIHITO (JP)
HIRAMINE MASANOBU (JP)

PCT/JP2013/057821

October 17, 2013

March 19, 2013

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MITSUBISHI ELECTRIC CORP (JP)
TAJIMA KENICHI (JP)
KAWAKAMI KENJI (JP)
HIRAI AKIHITO (JP)
HIRAMINE MASANOBU (JP)

H04L25/49; H03M5/12

JPS6413820A	1989-01-18
JPH0265318A	1990-03-06
JPS6413820A	1989-01-18

D. CHEEWASRIRUNGRAUNG: "A Multi-Gigabit DLL-based CMOS PWM Demodulator Using Delay Vernier Sampler", INTERNATIONAL CONFERENCE ON ECTI-CON, 2010

TAZAWA, Hideaki et al. (JP)
Hideaki Tazawa (JP)

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