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Title:
SILICON OXIDE INSULATOR (SOI) SEMICONDUCTOR HAVING SELECTIVELY LINKED BODY
Document Type and Number:
WIPO Patent Application WO1999031731
Kind Code:
A3
Abstract:
A silicon oxide insulator (SOI) device (A) includes an SOI layer (14, 154, 174) supported on a silicon substrate (12, 156, 172). A body region (B) is disposed on the SOI layer (14, 154, 174), and the body region (B) is characterized by a first conductivity type. Source and drain regions (C) are juxtaposed with the body region, with the source and drain regions (C) being characterized by a second conductivity type. A transition region (D) is disposed near the body region above the SOI layer (14, 154, 174), and the conductivity type of the transition region (D) is established to be the first conductivity type for suppressing floating body effects in the body region (B) and the second conductivity type for isolating the body region. An ohmic connector (E) contacts the transition region (D) and is connected to a drain power supply when the source and drain are doped with N-type dopants. On the other hand, the power supply is a source power supply when the source and drain are doped with P-type dopants. SOI bipolar transistors, pinch resistors, and diodes, all incorporating transition regions, are also disclosed.

Inventors:
WOLLESEN DONALD
Application Number:
PCT/US1998/027030
Publication Date:
September 16, 1999
Filing Date:
December 16, 1998
Export Citation:
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Assignee:
ADVANCED MICRO DEVICES INC (US)
International Classes:
H01L23/52; H01L27/092; H01L21/8238; H01L27/12; H01L29/73; H01L29/739; H01L29/786; H01L29/861; (IPC1-7): H01L27/12; H01L29/786
Foreign References:
US5463238A1995-10-31
US5559368A1996-09-24
EP0724295A11996-07-31
Other References:
YO-HWAN KOH ET AL: "BODY-CONTACTED SOI MOSFET STRUCTURE WITH FULLY BULK CMOS COMPATIBLELAYOUT AND PROCESS", IEEE ELECTRON DEVICE LETTERS, vol. 18, no. 3, March 1997 (1997-03-01), pages 102 - 104, XP000678869
CHEN W ET AL: "SUPPRESION OF THE SOI FLOATING-BODY EFFECTS BY LINKED-BODY DEVICE STRUCTURE", 1996 SYMPOSIUM ON VLSI TECHNOLOGY. DIGEST OF TECHNICAL PAPERS, HONOLULU, JUNE 11 - 13, 1996, 11 June 1996 (1996-06-11), INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, pages 92/93, XP000639298
SHAHIDI G G: "SOI: OPPORTUNITIES AND CHALLENGES FOR SUB-0.25 UM VLSI", PROCEEDINGS OF THE BIPOLAR/BICMOS CIRCUITS AND TECHNOLOGY MEETING, MINNEAPOLIS, OCT. 7 - 8, 1992, 5 October 1992 (1992-10-05), INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, pages 255 - 259, XP000340188
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