SILICON WAFER MANUFACTURING METHOD

Title:

SILICON WAFER MANUFACTURING METHOD

Document Type and Number:

WIPO Patent Application WO/2005/122225

Kind Code:

A1

Abstract:

A silicon wafer manufacturing method is provided for further reducing a crack rate of a silicon wafer. In the silicon wafer manufacturing method, a fine unevenness which exists on a side plane of a silicon block or a silicon stack for silicon wafer manufacture is flattened by polishing, and the obtained silicon block or the silicon stack is sliced or separated to provide a silicon wafer. The flattening is performed so as to have the thickness of the removed side plane by polishing to be Xμm × 5 or more, when the surface roughness (Ry) of the side plane to be flattened is Xμm prior to flattening.

Inventors:

KAJIMOTO KIMIHIKO (JP)
WAKUDA JUNZO (JP)

Application Number:

PCT/JP2005/009887

Publication Date:

December 22, 2005

Filing Date:

May 30, 2005

Export Citation:

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Assignee:

SHARP KK (JP)
KAJIMOTO KIMIHIKO (JP)
WAKUDA JUNZO (JP)

International Classes:

B24B37/04; H01L21/304; (IPC1-7): H01L21/304; B24B37/04

Foreign References:

JP2002237476A	2002-08-23
JP2002176014A	2002-06-21
JPH05182939A	1993-07-23

Attorney, Agent or Firm:

Nogawa, Shintaro (Minamimorimachi Park Bldg. 1-3, Nishitenma 5-chome, Kita-k, Osaka-shi Osaka 47, JP)

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