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Title:
SIMULATION METHOD, METHOD FOR PRODUCING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2024/053115
Kind Code:
A1
Abstract:
This simulation method comprises: preparing a simulation model of a semiconductor device including a substrate, an element, a connecting part which electrically connects the substrate and the element, and a reinforcing material which is disposed on a peripheral part of the element; and calculating an amount of strain applied to the connection part in the simulation model.

Inventors:
HAMAGAMI HIROYUKI (JP)
KATO YASUHIKO (JP)
SEKI KOHEI (JP)
Application Number:
PCT/JP2022/033968
Publication Date:
March 14, 2024
Filing Date:
September 09, 2022
Export Citation:
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Assignee:
RESONAC CORP (JP)
International Classes:
H01L21/56; H01L21/60; H01L23/28
Foreign References:
JP2004146534A2004-05-20
JPH10313022A1998-11-24
JP2007109904A2007-04-26
JPS61159752A1986-07-19
JP2013065705A2013-04-11
JP2010118364A2010-05-27
Attorney, Agent or Firm:
TAIYO, NAKAJIMA & KATO (JP)
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