RELATED APPLICATIONS

[0001] The present application claims the benefit under 35 U.S.C. 119(e) of U.S. Provisional Application 63/358,886 filed on July 7, 2022, the disclosure of which is incorporated herein by reference.

FIELD

[0002] Embodiments of the invention relate to a power switch.

BACKGROUND

[0003] Modern optical and electronic devices of almost all types, from computers to powertrains, comprise power switching circuitry for generating timing pulses, data packets, and/or delivering power. For delivering power to electric powertrains, such as powertrains used to deliver power to electric vehicles, power switches are required that can carry large currents and be turned ON and OFF rapidly to couple and decouple a high voltage electric power source to a load. For example, a high power inverter operated to deliver AC power to an automotive traction motor from a DC power source may comprise a half bridge having a high side array of GaN dies connected to a low side array of GaN dies, and a PCB control circuit to control the arrays to invert the DC power to AC power. It is advantageous that the inverter have low inductance, a small footprint, efficient heat dissipation, and be easily mountable and scalable to satisfy electrical and mechanical constraints of different electric vehicle configurations.

SUMMARY

[0004] An aspect of an embodiment of the disclosure relates to providing a power switch, also referred to as a Power-Mite, characterized by low inductance and small footprint that is readily scalable and may easily be coupled to external electrical circuitry and mounted by soldering or sintering to a heatsink. In an embodiment Power- Mite comprises a pair of half bridges and a printed circuit board (PCB) controller operable to turn ON and turn OFF the half bridges to provide pulses of voltage and current to a load connected to Power-Mite. Each half bridge optionally comprises a high side GaN die connected to a low side GaN die. To provide Power- Mite with relatively low inductance, the half bridges are configured so that current flows in substantially same, parallel directions when the half bridges are turned ON to provide voltage and a pulse of current to the load. The total power loop inductance of Power-Mite during transition between ON and OFF states may be lower than about 2.5 nanoHenries (nH).

[0005] In an embodiment the half bridges, PCB controller, and other electrical and mechanical components of Power-Mite are encapsulated in a protective polymer encapsulation, optionally referred to as an envelope. The envelope has a substantially unbroken uniform geometric external shape comprising relatively large parallel planar face surfaces of a same shape and at least one relatively narrow edge surface. The envelope may by way of example substantially be a rectangular parallelepiped, a rectangular parallelepiped having face surfaces that are rounded parallelograms, or a solid having face surfaces that are squircles. In an embodiment terminals that provide electrical contact to a component or components inside the envelope are embedded in the envelope and have electrical contact surfaces for making electrical contact with the terminals that are located on a surface of the envelope. In an embodiment a terminal contact surface is substantially coplanar with a surface on which it lies. Optionally, the contact surface is recessed or raised with respect to the surface on which it is located. In an embodiment the contact surface is located on a face surface of the envelope. Optionally, the contract surfaces of all the terminals are located on a same face surface.

[0006] Power-Mite may comprise terminal pins that extend from an edge surface of the envelope for making electronic contact with a component or components inside the envelope. In an embodiment the terminal pins comprise terminal pins that are located diagonally opposite each other on opposite edge surfaces of the envelope.

[0007] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

BRIEF DESCRIPTION OF THE FIGURES

[0008] Non-limiting examples of embodiments of the invention are described below with reference to figures attached hereto that are listed following this paragraph. Identical structures, elements or parts that appear in more than one figure are generally labeled with a same numeral in all the figures in which they appear. Dimensions of components and features shown in the figures are chosen for convenience and clarity of presentation and are not necessarily shown to scale.

[0009] Figs. 1 A and IB schematically show top and bottom perspective views of a Power-Mite power switch in accordance with an embodiment of the disclosure; [0010] Fig. 1C schematically shows a variation of a Power-Mite in accordance with an embodiment of the disclosure;

[0011] Figs. 2A-2G schematically show features of the construction and assembly of a Power- Mite, in accordance with an embodiment of the disclosure; and

[0012] Figs. 3A-3C schematically compare footprints of an assembly of prior art power switches with assemblies of Power-Mites in accordance with embodiments of the disclosure.

DETAILED DESCRIPTION

[0013] In the discussion, unless otherwise stated, adjectives such as “substantially” and “about” modifying a condition or relationship characteristic of a feature or features of an embodiment of the disclosure, are understood to mean that the condition or characteristic is defined to within tolerances that are acceptable for operation of the embodiment in an application for which it is intended. Wherever a general term in the disclosure is illustrated by reference to an example instance or a list of example instances, the instance or instances referred to, are by way of nonlimiting example instances of the general term, and the general term is not intended to be limited to the specific example instance or instances referred to. The phrase “in an embodiment”, whether or not associated with a permissive, such as “may”, “optionally”, or “by way of example”, is used to introduce for consideration an example, but not necessarily required, configuration of possible embodiments of the disclosure. Each of the verbs, “comprise” “include” and “have”, and conjugates thereof, are used to indicate that the object or objects of the verb are not necessarily a complete listing of components, elements or parts of the subject or subjects of the verb. Unless otherwise indicated, the word “or” in the description and claims is considered to be the inclusive “or” rather than the exclusive or, and indicates at least one of, or any combination of more than one of items it conjoins.

[0014] Figs. 1 A and IB schematically show top and bottom perspective views respectively of a Power-Mite 20 optionally configured to provide power to a phase of an electric vehicle traction motor, in accordance with an embodiment of the disclosure. Power-Mite 20 comprises an optionally rectangular parallelepiped envelope 22 having a top face surface 23 show in Fig. 1A, a bottom face surface 24 shown in Fig. IB, and four relatively narrow edge surfaces 25. Envelope 22 may be formed as a result of dicing a plurality of Power-Mites 20 from a common multiunit encapsulation mold in which the Power- Mites are encapsulated in a suitable polymer.

[0015] Terminals (not shown in Figs. 1A and IB) discussed below that provide contact to components of Power-Mite 20 are encapsulated in envelope 22 and have contact surfaces 30-1, 30-2, 30-3, and 30-4 that are exposed on top surface 23 and may be generically referenced as contact surfaces 30. Contact surfaces 30-1 and 30-2 are surfaces of power terminals 41 and 42 respectively discussed below that may be used to couple power from a high energy power source (not shown) to half bridges encapsulated in envelope 22. Contact surface 30-3 is a surface of a power phase output terminal 43 discussed below that may be used to couple voltage and current to a phase of an electric motor. Contact surfaces 30-4 are surfaces of control terminals 44 discussed below that may be used to couple control circuitry to a PCB controller discussed below encapsulated in envelope 22.

[0016] Optionally, contact surfaces 30, as schematically shown in Fig. 1A are coplanar, substantially flush, with top surface 23. In an embodiment a contact surface 30 may be raised or recessed to electrically isolate the contact surface and or facilitate making electrical contact with the contact surface. The contact surfaces 30 are formed from material that is compatible with electrically and mechanically coupling a conductor to the surfaces that is intended to provide electrical contact between an external circuit and the surfaces and the respective terminals of which the surfaces are a features. In an embodiment a surface 30 is configured so that a conductor may be electrically and mechanically coupled to a contact surface 30 by soldering, laser welding, or ultrasonic welding. Optionally, a surface 30 and its associated underlying terminal are configured so that a conductor may be screwed, or press fit into a hole formed in the terminal. Bottom surface 24 shown in Fig. IB optionally has a conductive thermal interface 26 formed on the surface. The thermal interface may be way of example be formed from any of various suitable high heat conductive materials such as a thermally conductive solder or adhesive, a sintering or curing type silver paste.

[0017] In an embodiment a Power-Mite 20 may comprise a terminal pin in addition to or in place of a contact surface 30. Fig. 1C schematically shows a Power-Mite 21 in accordance with an embodiment of the disclosure that is similar to Power-Mite 20 but comprising a set 46 of terminal pins 47 and a set 48 of terminal pins 49 in place of terminals having contact surfaces 30 on top face surface 23. In an embodiment, set 46 of terminal pins 47 and set 48 of terminal pins 49 are located diagonally opposite each other on opposite edge surfaces 25 of envelope 22. As discussed below with respect to Figs. 3A and 3B the location of terminal pin sets 46 and 48 diagonally opposite each other facilitates dense packing of a plurality of Power-Mites 20 and convenient connecting of the Power-Mites in parallel to provide switching large currents.

[0018] It is noted that envelope 22 in Fig. 1C exhibits a parting line 27 along which terminal pins are arrayed. Whereas it may be advantageous to encapsulate a plurality of Power- Mite 20 terminals, such as terminals 41-44 having contact surfaces 30, in a common multiunit encapsulation mold and then dice the Power-Mite 20 circuits to free the individual Power-Mite 20 circuits, it may be advantageous to encapsulate Power-Mite having terminal pins, such as terminal pins 47 and 49, individually in single unit molds. Whereas the process of multiunit encapsulation followed by dicing results in envelopes 22 absent parting lines, individual, single unit encapsulation generally requires a two piece release mold, which typically results in envelope 22 shown in Fig. 1C having parting lines 27.

[0019] Figs. 2A-2G schematically show stages in the construction and assembly of Power-Mite 20, in accordance with an embodiment of the disclosure.

[0020] Fig. 2A schematically shows a first stage of the construction of a Power-Mite 20 in which a pattern of conductive traces generically referred to as traces 50 to which components of Power-Mite are to be electrically connected, is formed on an upper surface 41 of an optionally DBC (Direct bond copper) substrate 40. In an embodiment traces 50 comprise positive power terminal traces 51, negative power terminal traces 52, a power output phase trace 53, control traces 54, and die contact traces 55, 56, 57, and 58. Connecting pins 60 that may be used to electrically connect circuit components of Power-Mite to a PCB controller 100 (not shown in Fig. 2A) encapsulated in Power-Mite 20 are mounted to traces 50. In an embodiment conductive spacers 62 are electrically connected to power traces 51 to facilitate connection of the power traces to metallization electrodes of Power-Mite components. As schematically shown in Fig. 2C and discussed below, spacers 62 facilitate using planar interconnects to make electrical connections to metallization electrodes of Power-Mite components that are raised above top surfaces of traces 50 by thickness of the components.

[0021] Fig. 2B schematically shows semiconductor dies that are directly connected to respective traces of traces 50 to form two half bridges 70 and 80 of Power-Mite 20. In an embodiment half bridge 70 comprises a high side, optionally normally ON lateral n-channel GaN (Gallium Nitride) die 72, a high side optionally p-channel MOSFET (Metal On Silicon Field Effect Transistor) die 74, a low side, optionally normally ON lateral n-channel GaN die 76 and a low side, optionally p-channel MOSFET die 78. Similarly half bridge 80 may comprise a high side, optionally normally ON lateral n-channel GaN die 82, a high side, optionally p-channel MOSFET die 84, and a low side, optionally normally ON lateral n-channel, GaN die 86, and a low side, optionally p-channel MOSFET die 88.

[0022] Each normally ON GaN die 72, 76, 82, and 86 optionally comprises an array (not shown) of rows of optionally normally ON lateral GaN transistors (not shown) connected to a fishbone configuration 90 of metallization layers comprising a drain fishbone metallization layer 92-D having spines 93 interleaved with spines 94 of a source fishbone metallization layer 95-S. Drains (not shown) of the normally ON GaN transistors are electrically contacted to spines 92-D of drain fishbone 93 and sources of the transistors are electrically contacted to spines 94 of the source fishbone 95-S. Gates of the GaN transistors are electrically connected to control traces 54 designated “54g” optionally by wire bonds. Gates of the MOSFET transistors are electrically connected to control traces 54 designated “54g*” optionally by wire bonds. The substrates (not shown) of GaN dies 72, 76, 82, and 86 are electrically connected to respective die traces 55, 57, 56, and 58 to which the dies are are mounted.

[0023] Each MOSFET die 74, 84, 78 and 88 comprises an array of MOSFET transistors (not shown) having their respective sources electrically connected to source metallization layers 74-S, 84-S, 78-S and 88-S respectively and their respective drains connected to a drain metallization layer (not shown). The drain metallization layers of high side MOSFET dies 74 and 84 are electrically connected to power output phase output trace 53. Each drain metallization layer of low side MOSFET dies 78 and 88 is electrically connected to a negative power trace 52.

[0024] In Fig. 2C the GaN dies and MOSFET dies shown in Fig. 2B are connected by relatively large area planar interconnect conductors. Drain fishbone metallization layer 92-D (Fig 2B) of high side GaN die 72 is electrically connected to conductive spacers 62 (Fig 2B) located on a positive power trace 51 by, an optionally planar, conductive interconnect 73. Source metallization 95-S (Fig 2B) of high side GaN die 72 is electrically connected to source metallization 74-S of high side MOSFET 70 by, an optionally planar, conductive interconnect 75. Similarly, drain metallization 92-D (Fig 2B) of high side GaN die 82 is electrically connected to conductive spacers 62 located and connected to a positive power trace 51 by, an optionally planar, conductive interconnect 83. Source metallization 95-S (Fig 2B) of high side GaN die 82 is electrically connected to source metallization 84-S of high side MOSFET 84 by, an optionally planar, conductive interconnect 85. Source metallization layer 95-S of low side Gan die 76 is electrically connected to source metallization layer 78-S of MOSFET 78 by, an optionally planar, interconnect 77 and source metallization layer 95-S of low side GAN die 86 is electrically connected to source metallization layer 88-S of MOSFET die 88 by, an optionally planar, interconnect 87. Drain metallization layers 92-D of low side GaN dies 76 and 86 are connected together by, an optionally planar, conductive interconnect 76-86. Interconnect 76- 86 makes electrical contact with conductive spacers 62 on power output phase trace 53 and thereby with the power output phase trace.

[0025] Fig. 2D schematically shows direction of current in half bridge 70 and half bridge 80 when Power-Mite 20 is ON and electrifies power trace 53 to deliver voltage and current to, optionally, a traction motor connected to Power-Mite 20 from a power source connected to positive and negative power terminal traces 51 and 52. In the figure, an arrowed band labeled 1-70 schematically represents current flow that passes through half bridge 70. Solid portions of the band represent current flow of 1-70 on interconnects 73, 75, and on conducting trace 53. A dashed region of band 1-70 represents a “hidden” portion of 1-70 that flows “down” from interconnect 75 through MOSFET 74 (Fig. 2B) to flow on a portion of conducting trace 53 beneath interconnects 75 and 85. Similarly an arrowed band labeled 1-80 schematically represents current flow that passes through half bridge 80. Solid portions of the band represent current flow of 1-80 on interconnects 83, 85, and on conducting trace 53. A dashed region of band 1-80 represent a “hidden” portion of 1-80 that flows “down” from interconnect 85 through MOSFET 84 (Fig. 2B) to flow on conducting trace 53 beneath interconnects 75 and 85. It is noted that currents 1-70 and 1-80 flow parallel to each other in trace 53 and contribute to reducing inductance of Power- Mite 20 during turn ON and turn OFF.

[0026] Fig. 2E schematically shows direction of current in half bridge 70 and half bridge 80 when Power-Mite 20 is turned OFF by turning high side GaN transistors 72 and 82 and MOSFETS 74 and 84 are turned OFF and low side Gan transistors 76 and 86 and low side MOSFETS 78 and 88 are turned ON. Current from negative power terminal trace 52 flows in current branches represented by bands 1-77 and 1-87 through MOSFETS 78 and 88 up to conductive interconnect 76-86 and combine in current represented by a current band 1-53 to flow to Power-Mote 20 along output phase trace 53. Dashed portions of bands represent portions of current hidden in the perspective of Fig. 2E.

[0027] In an embodiment total power loop inductance of Power-Mite 20 during transition between ON and OFF states may be less than about 2.50 nH. Optionally the total power loop inductance may be less than about 2.25nH.

[0028] Fig. 2F schematically shows Power-Mite 20 after power terminals 41 and 42 having contact surfaces 30-1 and 30-2 (Fig. 1A) respectively are mounted to positive and negative power terminal traces 51 and 52 (Fig. 2A), power phase output terminal 43 having contact surface 30-3 (Fig. 1 A) is mounted to power output phase trace 53 (Fig. 2A), and an optionally multilayer control PCB 100 has been mounted to Power-Mite 20. PCB 100 makes contact to components in Power-Mite 20 via connecting pins 60 (Figs. 2A-2E) and with circuitry outside of Power-Mite 20 via optionally cylindrical control terminals 44 having contact surfaces 30-4 (Fig. 1 A). In an embodiment Power-Mite 20 as schematically shown in Fig. 2F is encapsulated to provide Power-Mite 20 in finished form as shown in Fig. 1A.

[0029] Fig. 2G schematically shows the Power-Mite variation, Power-Mite 21, in which cylindrical control terminals 44 shown in Fig. 2F are replaced by diagonally opposite sets 46 configuration shown in Fig. 1C.

[0030] Power-Mites in accordance with an embodiment of the disclosure , such as Power-Mites 20 and 21 engineered as schematically shown in Figs. 1A-2G have unusually aesthetic configurations and relatively small footprints. The small footprints and embedded or diagonally opposite electrical terminals enable Power-Mites in accordance with embodiments of the disclosure to be readily mounted, optionally by soldering or sintering to a heatsink, and connected in parallel, in compact dense “power-pack” arrays.

[0031] By way of example, Figs. 3A and 3B schematically show dimensions of footprint of power-pack arrays 201 and 202 of six Power-Mites 20 and 21 respectively. In accordance with embodiments of the disclosure. For comparison, Fig. 3C shows a footprint of a power-pack 220, were terminal pin arrays mounted directly opposite, instead of diagonally opposite each other as in Power-Mite 21, in accordance with an embodiment. Footprints of power-pack arrays 201 and 202 are substantially smaller than that of footprint of power-pack array 220.

[0032] Descriptions of embodiments of the invention in the present application are provided by way of example and are not intended to limit the scope of the invention. The described embodiments comprise different features, not all of which are required in all embodiments of the invention. Some embodiments utilize only some of the features or possible combinations of the features. Variations of embodiments of the invention that are described, and embodiments of the invention comprising different combinations of features noted in the described embodiments, will occur to persons of the art. The scope of the invention is limited only by the claims.