FIELD OF DISCLOSURE

The present disclosure relates in general to circuits for electronic devices, including without limitation personal audio devices such as wireless telephones and media players, camera and image sensors, visual displays, and wireless communications devices, and more specifically, systems and methods for providing a smooth transition between a low-power mode and a high power mode in a power converter.

BACKGROUND

Electronic devices, including wireless telephones, such as mobile/cellular telephones, cordless telephones, mp3 players, cameras, and other electronic devices, are in widespread use. Such electronic devices may include circuitry for driving any suitable collection of electrical or electronic components, including without limitation speakers, headphones, motors, haptic actuators, image sensors, cameras, displays, wireless communications circuitry, etc. Oftentimes, a power converter may be used to provide a regulated supply voltage to a power amplifier in order to amplify a signal driven to speakers, headphones, motors, haptic actuators, or other components. A switching power converter is a type of electronic circuit that converts a source of power from one direct current (DC) voltage level to another DC voltage level. Examples of such switching DC- DC converters include but are not limited to a boost converter, a buck converter, a buckboost converter, an inverting buck-boost converter, and other types of switching DC-DC converters. Thus, using a power converter, a DC voltage such as that provided by a battery may be converted to another DC voltage used to power the power amplifier or a sensor. In addition to a power amplifier or sensor, one or more other critical components of an electronic device may be powered from a stable power rail with a DC voltage regulated by a power converter.

A predominant portion of a DC-DC converter circuit may be implemented within a single power management integrated circuit (PMIC) that provides a regulated supply voltage for a plurality of components, which themselves may be implemented as one or more other integrated circuits. Many portable electronic devices may require a large number of converter circuits in order to generate multiple rail voltages. Portable electronic devices are usually battery operated and may need to be judicious in their use of power in order to ensure a battery maintains charge for as long as possible. Consequently, many of these PMICs and their converter circuits may need only be powered on in accordance with need. Thus, power converters may be off or in a lower power mode for a large portion of time, and turned on or activated only a short time prior to or exactly at the time the component needing the associated voltage supply rail is enabled.

For example, when a load of a DC-DC converter is off, the DC-DC converter may be operated in a lower power mode wherein the DC-DC converter only switches/operates as necessary to replenish charge on an output capacitor that establishes the supply rail. However, the load may become active at any time, generating a sudden current demand, also known as a load transient, from the DC-DC converter. In many instances, the DC-DC converter and its PMIC may have no prior indication of an impending activation of a load, and hence the DC-DC converter may need to respond quickly to any instantaneous reduction of the voltage on the output capacitor due to the applied load and transition to a higher power mode.

An example of a low-power mode may be a discontinuous conduction mode (DCM) or pulse-frequency modulation (PFM) mode of operation. In such a mode, a DC-DC converter may switch infrequently or on an as-needed basis to transfer charge to the converter’s output capacitor. When operating in such a low-power mode, a significant portion of the digital and analog circuits supporting the DC-DC converter may be turned off to conserve power. When a sudden load is applied, the DC-DC converter may need to power on all supporting blocks and transition to a high-power mode to support the increased load demand. An example of a high-power mode may comprise a continuous conduction mode (CCM) or pulse-width modulation (PWM) mode of operation. The finite time taken (e.g., due to the finite time needed to power on supporting blocks of the DC-DC power converter) to transition from a low-power state to a high-power state may cause a perturbation (e.g., voltage undershoot or voltage overshoot) on the supply rail at the output of the DC-DC power-converter. In many cases, it may be critical to limit these perturbations, as voltage undershoots and overshoots may negatively affect operation. Thus, transitions from low- to high- power states and vice versa may need to occur quickly. However, if transitions occur quickly but not smoothly, additional perturbation on the supply rail may occur. Accordingly, systems and methods for providing for smooth transitions between power modes may be desired.

SUMMARY

In accordance with the teachings of the present disclosure, one or more disadvantages and problems associated with existing approaches to regulating an output voltage of a power converter during transitions between power modes may be reduced or eliminated.

In accordance with embodiments of the present disclosure, a system may include a power converter for regulating an output voltage at an output of the power converter, power management circuitry configured to enable operation of the power converter, including one or more first components critical to operation of the power converter in a high-power mode and one or more second components critical to operation of the power converter in both the high-power mode and a low-power mode in which the system consumes significantly less power than that of the high-power mode, and a controller. The controller may be configured to cause the system to operate in one of the low-power mode and the high-power mode based on power demand from a load at the output of the power converter and when in the low-power mode, monitor the output of the power converter to detect an occurrence of a load transient from the load and in response to detecting the occurrence of the load transient, transition from the low-power mode to the high-power mode via a transition mode to minimize undershoot and overshoot of the output voltage.

In accordance with embodiments of the present disclosure, a method may be provided for a system having a power converter for regulating an output voltage at an output of the power converter and power management circuitry configured to enable operation of the power converter, including one or more first components critical to operation of the power converter in a high-power mode and one or more second components critical to operation of the power converter in both the high-power mode and a low-power mode in which the system consumes significantly less power than that of the high-power mode. The method may include causing the system to operate in one of the low-power mode and the high-power mode based on power demand from a load at the output of the power converter and when in the low-power mode, monitoring the output of the power converter to detect an occurrence of a load transient from the load and in response to detecting the occurrence of the load transient, transitioning from the low-power mode to the high-power mode via a transition mode to minimize undershoot and overshoot of the output voltage.

Technical advantages of the present disclosure may be readily apparent to one skilled in the art from the figures, description, and claims included herein. The objects and advantages of the embodiments will be realized and achieved at least by the elements, features, and combinations particularly pointed out in the claims.

It is to be understood that both the foregoing general description and the following detailed description are examples and explanatory and are not restrictive of the claims set forth in this disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete understanding of the present embodiments and advantages thereof may be acquired by referring to the following description taken in conjunction with the accompanying drawings, in which like reference numbers indicate like features, and wherein:

FIGURE 1 illustrates selected components of an example power management system, in accordance with embodiments of the present disclosure;

FIGURE 2A illustrates selected waveforms of various signals that may be present in the power management system of FIGURE 1 and used in detecting a load transient, in accordance with embodiments of the present disclosure;

FIGURE 2B illustrates selected waveforms of various signals that may be present in the power management system of FIGURE 1 and used in detecting a load transient, in accordance with embodiments of the present disclosure; FIGURE 3 also illustrates selected waveforms of various signals that may be present in the power management system of FIGURE 1 and used in detecting a load transient, in accordance with embodiments of the present disclosure;

FIGURE 4 illustrates selected waveforms of various signals that may be present in the power management system of FIGURE 1 and used in detecting and responding to a load transient, in accordance with embodiments of the present disclosure;

FIGURE 5A illustrates selected waveforms of various signals that may be present in the power management system of FIGURE 1 and used in detecting and responding to a load transient, in accordance with embodiments of the present disclosure;

FIGURE 5B illustrates selected waveforms of various signals that may be present in the power management system of FIGURE 1 and used in detecting and responding to a load transient, in accordance with embodiments of the present disclosure; and

FIGURE 5C illustrates selected waveforms of various signals that may be present in the power management system of FIGURE 1 and used in detecting and responding to a load transient, in accordance with embodiments of the present disclosure.

DETAILED DESCRIPTION

FIGURE 1 illustrates selected components of an example power management system 100, in accordance with embodiments of the present disclosure. Example power management system 100 depicted in FIGURE 1 may be used in connection with any suitable electronic and/or electrical system, including without limitation smartphones, game controllers, portable media players, digital cameras, etc.

In particular, FIGURE 1 illustrates a buck converter implemented by power switches 102 and 104 and power inductor 106, and various other components that may enable the buck converter to operate with apeak current control wherein switching of power switches 102 and 104 is based, at least in part, on comparison of inductor current through power inductor 106 and a peak current, wherein such peak current may vary in accordance with the closed loop control shown in FIGURE 1. While FIGURE 1 depicts a buck converter, the methods and systems described herein may also be applicable to other types of power converters, including without limitation boost converters, buck-boost converters, and others. In addition, while FIGURE 1 depicts components associated with peak current control, the methods and systems described herein may also be applicable to other types of control modes for power converters, including duty cycle control mode and hysteretic control mode, provided that such control modes are operable between at least two modes comprising a high-power mode in which most or all components of a power management system are enabled and a low-power mode in which a significant portion of the components of a power management system are disabled.

In the embodiments represented by FIGURE 1, power management system 100 may include an error amplifier 108 (shown as a combiner in FIGURE 1) configured to amplify a difference between an error signal equal to the difference between a desired setpoint voltage Vsetpoim and an output voltage VOUT generated by the buck converter and sensed by voltage sensing circuity 122. A compensator 1 10 may convert the error signal into a peak current value IPK, which may be compared by a peak current comparator 112 against an inductor current IL sensed by current sense circuitry 114 as modified by slope compensation circuitry 116. Based on the comparison of slope-compensated inductor current IL to peak current IPK, as well as other parameters, controller 118 may generate switching control signals for switch driver circuitry 120, which may in turn generate switching control signals for power switches 102 and 104 to regulate output voltage VOUT for use by load 124. Examples of such other parameters upon which controller 118 may control switching of power switches 102 and 104 include, without limitation:

• comparison of inductor current IL to a maximum current limit by a comparator 126;

• comparison of output voltage VOUT to setpoint voltage Vsetpoim by output comparator 128;

• comparison of output voltage VOUT to a sum of setpoint voltage Vsetpoim and an overshoot voltage Vovershoot by overshoot comparator 130;

• any determinations of inductor current IL decreasing to zero as determined by zero crossing detector (ZCD) 132; and/or

• clock signals generated by clock generator 134 and/or PFM to PWM clock generator 136.

It is assumed that one of skill in the art is generally familiar with peak current control of a buck converter in either a high-power mode (e.g., CCM/PWM) or a low-power mode (e.g., DCM, PFM), including techniques involving zero crossing detection, slope compensation, maximum current limit control, etc. It is also assumed that one of skill in the art may be generally familiar with the fact that in a low-power mode, some components of power management system 100 may be disabled to save power. Examples of such disabled components may include error amplifier 108, compensator 110, voltage sensing circuity 122, peak current comparator 112, slope compensation circuity 116, output comparator 128, current sensing circuity 114, clock generator 134, and/or overshoot comparator 130. Accordingly, discussion herein may be limited mainly to systems and methods employed by controller 118 to smoothly transition between these low-power and high-power modes and vice versa.

In the low-power mode, output comparator 128 may sense when output voltage VOUT drops below setpoint voltage V _se t _P oint, and controller 1 18 may respond to the drop by applying a fixed peak current to control power switches 102 and 104 to charge output capacitor 140 to return output voltage VOUT to the regulated voltage V _se t _P oint, and then controller 118 may cease switching of power switches 102 and 104 until output voltage VOUT again drops below setpoint voltage V _se t _P oint.

If a sudden load transient occurs in the low-power mode (e.g., load 124 goes from demanding little or no current to demanding a significant amount of current), sensing circuitry as well as circuitry that determines an amount of charge to transfer to output capacitor 140 may be disabled. Thus, a rapid transition from the low-power mode to the high-power mode may be needed to support the increased load demand. Such a transition may involve enabling components that were disabled in the low-power mode and gracefully transitioning from the low-power mode to the high-power mode while not pushing too much or too little charge to the output of the buck converter. If the transition from the low- power mode to the high-power mode is not graceful, a large voltage overshoot or undershoot may result, which could compromise proper operation of load 124.

In order to gracefully transition from the low-power mode to the high-power mode, it may first be necessary to detect a load transient that triggers the change from low-power mode to high-power mode. As described above, the tripping of output comparator 128 due to output voltage VOUT decreasing below setpoint voltage V _S et _P oint causes controller 118 to control the buck converter to drive a fixed peak current pulse. In the absence of a load transient, such fixed peak current pulse may cause output voltage VOUT to increase above setpoint voltage V _se t _P oint, thus untripping output comparator 128. In the presence of a load transient, depending on the magnitude and the rate of the load transient, one of two possibilities may occur during a fixed peak current pulse of the low-power mode.

The first possibility is shown in FIGURE 2A, wherein output comparator 128 untrips at time 202 in response to a fixed peak current pulse 204, but trips again at time 206 before end of fixed peak current pulse 204 due to load transient 208. The second possibility is shown in FIGURE 2B, wherein output comparator 128 fails to untrip for the entire duration of fixed current pulse 204 due to load transient 208. In either case, a load transient can be assumed to have occurred.

Controller 118 may be able to easily detect the first condition of FIGURE 2A, given that output comparator 128 retrips while fixed peak current pulse 204 is being driven. The second condition of FIGURE 2B may be harder to detect, as nothing may change with output comparator 128 during the entire fixed peak current pulse 204. If controller 118 waits until the end of the demagnetizing (or discharge) phase of fixed peak current pulse 204 (e.g., the portion of fixed peak current pulse 204 in which inductor current IL is decreasing) in order to determine whether a load transient has occurred, a significant voltage droop 210 to output voltage VOUT may occur. Accordingly, as shown in FIGURE 3, controller 118 may wait for a pre-determined time T during the demagnetization phase of fixed peak current pulse 204 by which, if output comparator 128 has not tripped, controller 118 may assume a load transient has occurred and may take corrective action to transfer additional charge to output capacitor 140, as described in greater detail below.

Such pre-determined time T may be determined in any suitable manner. In some embodiments, controller 118 may determine pre-determined time T to be the time until which an amount of charge transferred to output capacitor 140 during fixed peak current pulse 204 is still increasing (which may be dependent upon an input voltage VBAT for the buck converter and output voltage VOUT). After such time T, controller 118 may cause the start of a new pulse 302 to enter into a transition mode between the low-power mode and the high-power mode. Waiting until later than time T may significantly diminish the opportunity to transfer adequate charge leading to violation of droop requirements/specifications.

FIGURE 4 illustrates a general approach to responding to a detected load transient, detected by using any of the approaches disclosed above. As shown in FIGURE 4, once a load transient has been detected during operation in the low-power mode, the buck regulator may switch from the low-power mode to a transition mode, in which the control scheme imposed by controller 118 is distinct from that of both the low-power and high-power modes. For example, unlike the low-power and high-power modes, during the transition mode, peak current IPK may be controlled in a feed- forward manner, on/off times of power switches 102 and 104 may be directly controlled, and/or frequency of operation may be controlled.

The length of the transition mode may be a predetermined number of switching cycles or a number of switching cycles determined based on one or more of: (a) a number of times output comparator 128 trips in a given time; (b) a duration of time between tripping and/or untripping of output comparator 128; (c) duration of time of a trip or untrip of output comparator 128; and/or (d) timing of a comparator trip relative to a switching cycle of the buck converter.

Because the main system clock (e.g., provided by clock generator 134) may be powered down during the low-power mode and may take time to power on, operations during the transition mode may be based on a low-fidelity clock (e.g., provided by PFM to PWM clock generator 136) generated for the transition mode. In some embodiments, a transition between the low-fidelity clock to the main system clock may be performed (e.g., by crossfading between the two clocks) to minimize clock discontinuity.

Also during the transition mode, components of power management system 100 disabled during the low-power mode may be initialized and/or enabled so that they are ready to operate in the high-power mode at the end of the transition mode. Once the transition mode has ended, the closed loop control system of power management system 100 may control the regulation of output voltage VOUT during the high-power mode. FIGURES 5A-5C set forth example approaches to responding to a detected load transient.

In a first approach shown in FIGURE 5A, the on/off times for power switches 102 and 104 of the buck converter during the transition phase may be controlled entirely based on the output of output comparator 128. For example, high-side power switch 102 may be enabled and low-side power switch 104 may be disabled when output comparator 128 is tripped, and high-side power switch 102 may be disabled and low-side power switch 104 may be enabled when output comparator 128 is untripped. Tying the on/off times of power switches 102 and 104 to output comparator 128 may ensure the amount of charge provided to output capacitor 140 is proportional to the demand of load 124. This manner of controlling the on/off times of power switches 102 and 104 may continue either for a predetermined number of cycles (e.g., at least 1) or may be extended if additional instances of output comparator 128 tripping or failing to untrip are detected. If, at any stage, output comparator 128 has not tripped for a pre-determined amount of time or a certain number of switching cycles have elapsed, controller 118 may switch to the closed loop control of the high-power mode. When switching to the high-power mode, controller 118 may initialize state variables of the closed loop to values that are a function of the number, duration, and/or time separation between trips and untrips of output comparator 128.

In the second approach shown in FIGURE 5B, peak current IPK during switching cycles of the transition mode may be controlled based on one or more of a duration between trips of output comparator 128, duration of time output comparator 128 is tripped, duration of time output comparator 128 is untripped, a difference between output voltage VOUT and setpoint voltage Vsetpoint, and a fixed-predetermined value. Such peak current control may continue either for a fixed number of cycles (e.g., at least 1) or may be extended based on one or more of the parameters set forth in the previous sentence. Once the predetermined number of switching cycles has passed, controller 118 may switch to the closed loop control of the high-power mode. When switching to the high-power mode, controller 118 may initialize state variables of the closed loop to values that are a function of the number, duration, and/or time separation between trips and untrips of output comparator 128.

In the third approach shown in FIGURE 5C, peak current IPK during switching cycles of the transition mode may be controlled based on a fixed value for a fixed number of cycles until a maximum current limit is reached. Thereafter, controller 118 allows peak current IPK to fall to a second lower limit, before switching the closed loop control in the high-power mode. In this third approach, voltage undershoot may be minimized by potentially causing a slight overshoot due to the peak current being increased until the maximum current limit is reached. When switching to the high-power mode, controller 118 may initialize state variables of the closed loop to values that are a function of the number, duration, and/or time separation between trips and untrips of output comparator 128.

In all three approaches, additional switching constraints such as minimum on and off times of power switches 102 and 104 may be imposed to control switching frequency or avoid arbitrarily small or large switch on and off times during the transition phase. As used herein, when two or more elements are referred to as “coupled” to one another, such term indicates that such two or more elements are in electronic communication or mechanical communication, as applicable, whether connected indirectly or directly, with or without intervening elements.

This disclosure encompasses all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that a person having ordinary skill in the art would comprehend. Similarly, where appropriate, the appended claims encompass all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that a person having ordinary skill in the art would comprehend. Moreover, reference in the appended claims to an apparatus or system or a component of an apparatus or system being adapted to, arranged to, capable of, configured to, enabled to, operable to, or operative to perform a particular function encompasses that apparatus, system, or component, whether or not it or that particular function is activated, turned on, or unlocked, as long as that apparatus, system, or component is so adapted, arranged, capable, configured, enabled, operable, or operative. Accordingly, modifications, additions, or omissions may be made to the systems, apparatuses, and methods described herein without departing from the scope of the disclosure. For example, the components of the systems and apparatuses may be integrated or separated. Moreover, the operations of the systems and apparatuses disclosed herein may be performed by more, fewer, or other components and the methods described may include more, fewer, or other steps. Additionally, steps may be performed in any suitable order. As used in this document, “each” refers to each member of a set or each member of a subset of a set.

Although exemplary embodiments are illustrated in FIGURE Is and described below, the principles of the present disclosure may be implemented using any number of techniques, whether currently known or not. The present disclosure should in no way be limited to the exemplary implementations and techniques illustrated in the drawings and described above.

Unless otherwise specifically noted, articles depicted in the drawings are not necessarily drawn to scale.

All examples and conditional language recited herein are intended for pedagogical objects to aid the reader in understanding the disclosure and the concepts contributed by the inventor to furthering the art, and are construed as being without limitation to such specifically recited examples and conditions. Although embodiments of the present disclosure have been described in detail, it should be understood that various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the disclosure. Although specific advantages have been enumerated above, various embodiments may include some, none, or all of the enumerated advantages. Additionally, other technical advantages may become readily apparent to one of ordinary skill in the art after review of the foregoing figures and description.

To aid the Patent Office and any readers of any patent issued on this application in interpreting the claims appended hereto, applicants wish to note that they do not intend any of the appended claims or claim elements to invoke 35 U.S.C. § 112(f) unless the words “means for” or “step for” are explicitly used in the particular claim.