VOLTAGE STRESS MITIGATION TECHNIQUES

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Application Serial No. 63/221,285, filed on 13 July 2021, which is incorporated herein by reference in its entirety as if fully set forth below.

GOVERNMENT LICENSE RIGHTS

[0002] This invention was made with government support under Agreement No. DE- AR0000899, awarded by ARPA-E. The government has certain rights in the invention.

FIELD OF THE DISCLOSURE

[0003] The various embodiments of the present disclosure relate generally to soft switching solid state transformers.

BACKGROUND

[0004] It is desirable to replace conventional line-frequency transformers with solid- state transformers (SST) or power electronic transformers (PET) in various applications because of their generally smaller weight, smaller size, and increased controllability. Most of the prior SST research has focused on medium-frequency transformer (MFT) design, control design, lightning protection, converter topology, and various applications including renewable energy, electric vehicle charging, motor drives, etc. Little research, however, has focused on grounding related issues of the SST, which are critical for safe and reliable operation in utility applications. Furthermore, due to the complexity of large amount of parasitics and the interaction mechanism between them, the grounding issues can be challenging. Accordingly, there is a need for improved transformers to address the various grounding issues present in conventional topologies.

BRIEF SUMMARY

[0005] An exemplary embodiment of the present disclosure provides a soft-switching solid-state power transformer comprising a transformer, a first auxiliary resonant circuit, a first current-source inverter (CSI) bridge, a second auxiliary resonant circuit, a second CSI bridge, and a first transformer capacitor. The transformer can comprise first and second winding

2 connections. The first auxiliary resonant circuit can be coupled to the first winding connection of the transformer. The first auxiliary resonant circuit can comprise a resonant capacitor coupled across the first winding connection, and a resonant inductor coupled across the first winding connection in parallel with the resonant capacitor. The first CSI bridge can be coupled to the first auxiliary resonant circuit. The first CSI bridge can comprise reverse blocking switches configured to conduct current in one direction and block voltage in both directions. The second auxiliary resonant circuit can be coupled to the second winding connection of the transformer. The second CSI bridge can be coupled to the second auxiliary resonant circuit. The second CSI bridge can comprise reverse blocking switches configured to conduct current in one direction and block voltage in both directions. The first transformer capacitor can be coupled to a high voltage side of the first winding connection and a ground.

[0006] In any of the embodiments disclosed herein, the first transformer capacitor can be configured to divert current away from one or more semiconductors of the first CSI bridge. [0007] In any of the embodiments disclosed herein, the power transformer can further comprise a second transformer capacitor coupled to a low voltage side of the of the first winding connection and the ground.

[0008] In any of the embodiments disclosed herein, the first transformer capacitor can have a capacitance equal to a capacitance of the second transformer capacitor.

[0009] In any of the embodiments disclosed herein, the first and second transformer capacitors can be configured to first divert current away from one or more semiconductors of the first CSI bridge.

[00010] In any of the embodiments disclosed herein, the power transformer can further comprise a third transformer capacitor coupled to a high voltage side of the second winding connection and the ground.

[00011] In any of the embodiments disclosed herein, the power transformer can further comprise a fourth transformer capacitor coupled to a low voltage side of the second winding connection and the ground.

[00012] In any of the embodiments disclosed herein, the fourth transformer capacitor can have a capacitance equal to a capacitance of the third transformer capacitor.

[00013] In any of the embodiments disclosed herein, the power transformer can further comprise a second soft-switching solid-state power transformer of claim coupled in parallel with the soft-switching solid-state power transformer of claim. [00014] In any of the embodiments disclosed herein, the power transformer can further comprise a rectifier filter coupled to the first CSI bridge. The rectifier filter can comprise a rectifier capacitor, a rectifier inductor in parallel with the rectifier capacitor, and a dampening resistor in parallel with the rectifier inductor.

[00015] In any of the embodiments disclosed herein, the power transformer can further comprise a fourth capacitor coupled to the first CSI bridge and the ground. The fourth capacitor can be connected in parallel with the rectifier filter.

[00016] In any of the embodiments disclosed herein, the dampening resistor can be configured to dampen LC oscillation between the rectifier filter and inductances in a grounding loop of the transformer.

[00017] In any of the embodiments disclosed herein, the fourth capacitor can be configured to increase an equivalent capacitance of the first CSI bridge and the transformer.

[00018] In any of the embodiments disclosed herein, the first CSI bridge can comprise a plurality of phase legs, and the power transformer can further comprise a rectifier filter coupled to each of the plurality of phase legs. Each of the rectifier filters can comprise a rectifier capacitor, a rectifier inductor in parallel with the rectifier capacitor, and a dampening resistor in parallel with the rectifier inductor.

[00019] In any of the embodiments disclosed herein, the power transformer can further comprise a distinct capacitor coupled to each of the plurality of phase legs of the CSI bridge and the ground, and each of the distinct capacitors can be in parallel with a corresponding rectifier filter.

[00020] In any of the embodiments disclosed herein, the fourth capacitor can be configured to increase an equivalent capacitance of the first CSI bridge and the transformer.

[00021] Another embodiment of the present disclosure provides a soft-switching solid- state power transformer, comprising a transformer, first and second auxiliary resonant circuits, first and second CSI bridges, and a rectifier filter. The transformer can comprise first and second winding connections. The first auxiliary resonant circuit can be coupled to the first winding connection of the transformer. The first auxiliary resonant circuit can comprise a resonant capacitor and a resonant inductor. The resonant capacitor can be coupled across the first winding connection. The resonant inductor can be coupled across the first winding connection in parallel with the resonant capacitor. The first CSI bridge can be coupled to the first auxiliary resonant circuit. The first CSI bridge can comprise reverse blocking switches configured to conduct current in one direction and block voltage in both directions. The second auxiliary resonant circuit can be coupled to the second winding connection of the transformer. The second CSI bridge can be coupled to the second auxiliary resonant circuit. The second CSI bridge can comprise reverse blocking switches configured to conduct current in one direction and block voltage in both directions. The rectifier filter can be coupled to the first CSI bridge. The rectifier filter can comprise a rectifier capacitor, a rectifier inductor, and a dampening resistor. The rectifier inductor can be in parallel with the rectifier capacitor. The dampening resistor can be in parallel with the rectifier inductor.

[00022] In any of the embodiments disclosed herein, the power transformer can further comprise a capacitor coupled to the first CSI bridge and the ground. The capacitor can be in parallel with the rectifier filter.

[00023] In any of the embodiments disclosed herein, the dampening resistor can be configured to dampen LC oscillation between the rectifier filter and inductances in a grounding loop of the transformer.

[00024] In any of the embodiments disclosed herein, the capacitor can be configured to increase an equivalent capacitance of the first CSI bridge and the transformer.

[00025] In any of the embodiments disclosed herein, the first CSI bridge can comprise a plurality of phase legs, and the rectifier filter can be coupled to a first phase leg in the plurality of phase legs. The power transformer can further comprise one or more additional rectifier filters coupled to the one or more additional phase legs in the plurality of phase legs.

[00026] In any of the embodiments disclosed herein, the dampening resistors of each of the plurality of rectifier filters can be configured to dampen LC oscillation between the rectifier filter and inductances in a grounding loop of the transformer.

[00027] In any of the embodiments disclosed herein, the capacitor can be coupled to the first phase leg, the power amplifier can further comprise one or more additional capacitors coupled to each of the one or more additional phase legs in the plurality of phase legs of the CSI bridge and the ground. Each of the one or more additional capacitors can be in parallel with a corresponding rectifier filter.

[00028] In any of the embodiments disclosed herein, the one or more additional capacitors can be configured to increase an equivalent capacitance of the first CSI bridge and the transformer.

[00029] These and other aspects of the present disclosure are described in the Detailed Description below and the accompanying drawings. Other aspects and features of embodiments will become apparent to those of ordinary skill in the art upon reviewing the following description of specific, exemplary embodiments in concert with the drawings. While features of the present disclosure may be discussed relative to certain embodiments and figures, all embodiments of the present disclosure can include one or more of the features discussed herein. Further, while one or more embodiments may be discussed as having certain advantageous features, one or more of such features may also be used with the various embodiments discussed herein. In similar fashion, while exemplary embodiments may be discussed below as device, system, or method embodiments, it is to be understood that such exemplary embodiments can be implemented in various devices, systems, and methods of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

[00030] The following detailed description of specific embodiments of the disclosure will be better understood when read in conjunction with the appended drawings. For the purpose of illustrating the disclosure, specific embodiments are shown in the drawings. It should be understood, however, that the disclosure is not limited to the precise arrangements and instrumentalities of the embodiments shown in the drawings.

[00031] FIG. 1 provides a schematic of a conventional modular soft-switching solid- state transformer (M-S4T), wherein the M-S4T is a current-source converter with magnetizing inductance L _m as its de link.

[00032] FIG. 2A provides a photo of a conventional M-S4T prototype. FIG. 2B provides a photograph of an experimental setup with the M-S4T.

[00033] FIG. 3 provides a schematic of the M-S4T of FIGs. 1 and 2A with parasitics from direct measurements or datasheets. One of the modules of the M-S4T is illustrated in FIG.

3. Capacitances of MV and LV devices are nonlinear and obtained from manufacturer. The values corresponding to the rated operating point are shown.

[00034] FIG. 4A provides a plot of impedance measurement results, and FIG. 4B provides a photograph of the LV device baseplate and the heatsink, in accordance with an exemplary embodiment of the present disclosure. The parasitic capacitance was measured to be 0.39 nF between each baseplate and the heatsink.

[00035] FIG. 5 provides single-module S4T waveforms at 1 kV peak without the exemplary voltage stress mitigation techniques disclosed herein, wherein the existence of the voltage stress issue is verified. [00036] FIG. 6 provides stacked-module M-S4T waveforms without the exemplary voltage stress mitigation techniques disclosed herein. Three modules are under test, two of which are shown in the waveforms. The existence of the voltage stress issue is verified.

[00037] FIGs. 7A-E provide an illustration of the Cause 1 of voltage stress, such that a portion of dc-link current (i _m ) flows through device and heatsink capacitances via grounding cables. FIG. 7A provides an equivalent circuit. FIG. 7B provides a further simplified equivalent circuit without the MV ground. FIG. 7C provides a further simplified equivalent circuit with the MV ground to illustrate the cause of the voltage stress when i _m concentrates on the MV side of the transformer, which is a worst-case scenario. FIG. 7D provides a solution of adding capacitors to reduce the voltage variation/stress across devices, in accordance with an exemplary embodiment of the present disclosure. FIG. 7E provides a simplified equivalent circuit when i _m concentrates on the LV side of the transformer. In the analysis of cause 1 in FIGs. 7A-E, the LV side is assumed solidly grounded, while the LV grounding impedance is considered in cause 2.

[00038] FIGs. 8A-D illustrate plots of voltage stress versus C _xfmr capacitance across variations of inter-winding capacitances (FIG. 8A), device capacitances of both C _{P_eq} and C _{N_eq} (FIG. 8B), only C _{P_eq} (FIG. 8C), and only C _{N_eq} (FIG. 8D), in accordance with an exemplary embodiment of the present disclosure.

[00039] FIG. 9 illustrates the Cause 2 of voltage stress, namely device capacitances and other parasitics resonate with grounding-loop inductance, in which an additional capacitor (C _add ) can shift the LC resonant frequency away from the excitation source and reduce the amplitude of voltage variation across the device. ν _CM from rectifier is of much lower frequency and smaller amplitude and hence not as problematic, in accordance with an exemplary embodiment of the present disclosure.

[00040] FIGs. 10A-C provide schematics of soft-switching solid-state power transformers implementing voltage stress mitigation techniques, in accordance with exemplary embodiments of the present disclosure. FIG. 10A provides a schematic for a single module case. FIGs. 10B-C provides schematics for multi-module cases, in which FIG. 10B and FIG. 10C are equivalent concerning the stress mitigation, i.e., filter capacitance is a short-circuit at the high frequency of interest. C _x2 in FIG. 10C can block lower line-frequency voltage. When the transformer turns ratio is large, e.g., 6: 1 in the prototype, a fraction of LV voltage reflected to the MV side causes negligible stress, and the MV-side C _x2 may not be needed. [00041] FIG. 11 provides a schematic of an experimental setup of a soft-switching solid- state power transformer implementing C _xfmr , C _add , and R _damp for voltage stress mitigation, in accordance with an exemplary embodiment of the present disclosure.

[00042] FIGs. 12A-12D provide single-module waveforms at 1.5 kV (FIG. 12A) peak with an exemplary soft-switching solid-state power transformer implementing voltage stress mitigation techniques and zoom-in at MVAC (FIG. 12B) peak, (FIG. 12C) zero crossing, and (FIG. 12D) valley in accordance with an exemplary embodiment of the present disclosure.

[00043] FIGs. 13A-13E provide stacked-module waveforms (FIG. 13A) under step change from 1.5 kV peak to 4 kV peak with an exemplary soft-switching solid-state power transformer implementing voltage stress mitigation techniques and zoom-in at (FIG. 13B) step-change instant, (FIG. 13C) MVAC peak, (FIG. 13D) MVAC zero crossing, and (FIG. 13E) MVAC valley, in accordance with an exemplary embodiment of the present disclosure. There were five modules in this experiment, though two modules’ output voltages are shown.

DETAILED DESCRIPTION

[00044] To facilitate an understanding of the principles and features of the present disclosure, various illustrative embodiments are explained below. The components, steps, and materials described hereinafter as making up various elements of the embodiments disclosed herein are intended to be illustrative and not restrictive. Many suitable components, steps, and materials that would perform the same or similar functions as the components, steps, and materials described herein are intended to be embraced within the scope of the disclosure. Such other components, steps, and materials not described herein can include, but are not limited to, similar components or steps that are developed after development of the embodiments disclosed herein.

[00045] The present disclosure addresses the issue and the mitigation method of the additional device voltage stress from the grounding-loop current in current-source SST. Compared to multi-stage voltage-source SST, current-source SST can feature single-stage power conversion with an inductive de link and benign failure modes, hi current-source SST, flyback-like operation means that MFT magnetizing current flows through the semiconductor devices on only one side of the MFT at a time to engage the input or the output. The voltages across the semiconductor devices, when they are not engaged with the input or the output, can be driven by parasitic grounding current beyond the normal voltage if not appropriately mitigated. [00046] Soft-switching solid-state transformer (S4T) topologies belong to the current- source SST category, i.e., the S4T with reduced conduction loss and the modular S4T (M-S4T). The S4T is disclosed in U.S. Patent No. 11,309,802, entitled “Transformers, Converters, and Improvements to the Same,” the entire contents of which are incorporated herein by reference as if fully set forth below. As explained in more detail below, various embodiments of the present disclosure provide improvements to the S4T disclosed therein to mitigate voltage stress experienced by those devices in certain configurations.

[00047] The S4T and the M-S4T require a special modulation scheme to achieve the zero- voltage switching (ZVS) state and mitigate the potential device voltage stress from differential-mode operation of the converter. However, the common-mode grounding-loop- induced voltage stress has not been discovered or studied in existing literature of any current- source SST or S4T. Rather, in conventional topologies of the S4T, the input source or the LV rectifier was grounded, while the output load or the MV resistor bank was ungrounded. But such topologies are not feasible for utility applications, in which both the LV side and the MV side are grounded. Accordingly, as discussed in more detail below, the present disclosure provides a voltage stress suppression technique that comprises adding grounding capacitors to the transformer terminal and the input terminal. FIGs. 10A-C, which will be discussed below provide S4T topologies that implement voltage stress mitigation techniques, in accordance with exemplary embodiments of the present disclosure.

[00048] M-S4T Model with Parasitics

[00049] As shown in FIG. 1, the conventional S4T is a single-stage current-source SST. Two current-source inverter (CSI) bridges based on reverse-blocking devices are located on both sides of the medium-frequency transformer (MFT) to interface the input and the output. Also, resonant capacitors, resonant inductor, auxiliary leakage diodes, and switches are placed on both sides of the MFT to achieve ZVS and manage the MFT leakage inductance. Multiple modules can be connected input-series output-parallel (ISOP) as a M-S4T to scale for higher voltage. Take module 1 in FIG. 1 as an example, the basic operation principle is to impose ν _MV1 across the dc-link inductor (L _m ) to energize L _m with the input bridge and later release the energy from L _m to the output through the output bridge, where the space vector of each phase can be modulated like a CSI.

[00050] Photographs of an M-S4T experimental prototype and experimental setup are shown in FIGs. 2A-B, where five modules are connected ISOP for higher voltage. The parasitic model of the M-S4T prototype can be characterized comprehensively as shown in FIG. 3. A rectifier-variac set supplies two LV phases of the M-S4T, and the MV side is coupled to a MV resistor load. The remaining LV phase is connected to a buffer capacitor bank to buffer the double-line-frequency power ripple from single-phase MV output. Filter capacitance C _fMV and C _fLV can be much larger than parasitic capacitances and acts effectively as a short circuit in the later analysis. Therefore, the values of such parameters are not marked in Fig. 3. The parasitics of the converter bridges, the MFT, the rectifier’s filter inductors, etc. are measured using an impedance analyzer. The grounding-loop inductances between the variac and the LV-side of the prototype and between the MV resistor load and the LV-side of the prototype were measured to be 51.97 μH and 8.54 μH, respectively, as marked in FIG. 2.

[00051] Note that a customized 3.3 kV SiC module with its baseplate floating was used on the MV side, which provides small capacitance (63.75 pF) for the isolation between the device die and the module baseplate. However, on the LV side, a self-assembled device module based on discrete TO-247 devices was used. The baseplate of the discrete devices is also the cathode of the diode and the collector of the IGBT. As the LV heatsink is solidly grounded, large parasitic capacitance (0.39 nF) exists between each baseplate and the ground. FIG. 4A illustrates the impedance measurement results between the LV device baseplate and the LV heatsink. FIG. 4B shows a photo of the self-assembled LV device module, which corresponds to the LV devices behind the printed circuit board of the LV bridge in FIG. 2A. Six baseplates in FIG. 4B accommodate the devices of the three LV phases in each M-S4T module.

[00052] Equivalent Circuits to Analyze the Voltage Stress: Phenomenon, Causes, and

Solution

[00053] The experimental waveforms of the M-S4T under a single-module test and a stacked-module test are shown in FIGs. 5-6. In FIG. 5, the S4T operates at 1 kV peak MVAC voltage. It can be observed that the voltage stress across device LVBN1 is as high as 360 V, while the LV source voltage is below 200 V. The voltage stress here is about 180%. The voltage waveforms show a LC-type resonance. The stress occurs during the MV active vector, when the dc-link current i _m1 equals i _xMV1 and ν _MV1 is imposed across L _m . This phenomenon is due to the LC resonance in the LV-side grounding loop. In FIG. 6, the M-S4T operates at 1.5 kV peak MVAC voltage with three ISOP modules. The LVBN1 device voltage is discharged during a ZVS transition state beyond (75 V more than) the envelope of ν _xLV1 . The voltage stress here is about 140%. This excessive discharge phenomenon is due to the dc-link current leaking through the LV device capacitance from the MV side to the LV side through grounding cables.

[00054] Cause 1 and Solution

[00055] The detailed analysis and a solution for the excessive discharge phenomenon, referred to herein as “cause 1,” will now be discussed. The S4T has a ZVS transition state to achieve the ZVS, when the dc-link inductor (L _m ) and its current (i _m ) discharge C _rLV and C _rMV in FIG. 3 until C _rLV /C _rMV voltage equals C _fLV / C _fMV voltage for an incoming LV/MV vector. Once ν _CrLV /ν _CrMV equals ν _CfLV /ν _CfMV , the corresponding switches for the space vector can be turned on with zero voltage, i.e., ν _CrLV — ν _CfLV /ν _CrMV — ν _CfMV across them. The ZVS transition state has been verified in FIG. 6 to be a problematic state during which grounding- loop currents result in additional device voltage stress. The equivalent circuit of the full parasitic model in FIG. 3 under the ZVS transition state is shown in FIG. 7 to illustrate cause 1. Because this equivalent circuit is used to analyze i _m current leakage among the capacitive network in the ZVS transition state, filter capacitors C _fMV and C _fLV with very small impedance compared to parasitic capacitors can be considered as short circuits. Moreover, suppose that multiple modules are cascaded in series on the MV side like Fig. 1 and this module is the second module from the ground. This module will have another filter capacitor C _fMV2 on its path to the MV ground as shown in FIG. 7A. Similar to C _fMV1 , C _fMV2 can also be regarded as a short circuit, which means that the second cascaded module is confronted with the similar situation as the first module in the context of the ground-leakage-current-induced voltage stress issue. If the MV side is ungrounded as shown in FIG. 7B, both C _{P_eq} and C _{N_eq} are discharged by i _m . We have Δν _CN < 0, Δν _CP < 0, Δν _{Cr_LV} < 0, and Equation 1 holds.

[00056] Equation 1 :

| Δν _CN | = |Δν _LVBN I = |Δν _CrLV — Δν _CP I = lΔν _CrLV l — I Δν _CP | = |Δν _xLV | — |Δν _CP | < |Δν _xLV | [00057] Therefore, the LVBN voltage variation in the ZVS transition state will be smaller than and hence within the envelope / voltage variation of ν _xLV .

[00058] With the MV grounded, however, as shown in the simplified equivalent circuit in FIG. 7C, the ground current, i.e., a portion of i _m will cause C _{P_eq} to be charged and C _{N_eq} to be discharged. In other words, Δν _CN and Δν _CP will move in opposite directions. Though the sum of Δν _CN and Δν _CP is equal to Δν _CrLV , Δν _CN will be greater than Δν _{Cr_LV} in this case, which means increased voltage stress compared to the ungrounded case. Analytically, it can be expressed as Δν _CN < 0, Δν _CP > 0, Δν _Cr < 0, and Equation 2 holds. [00059] Equation 2:

IΔν _CN I = IΔν _LVBN I = IΔν _CrLV — Δν _CP I = IΔν _CrLV I + |Δν _CP | = |Δν _xLV | + |Δν _CP | > |Δν _xLV | [00060] The EVEN voltage variation in the ZVS transition state will be bigger than and hence out of the envelope/voltage variation of ν _xLV . The magnitude of this stress was analyzed by solving the equivalent circuit in FIG. 7C. Note that the oscillations between the MV ground inductance (8.54 μH) and the nF-level capacitances were negligible, because the oscillation frequency is more than 10 MHz which can be easily damped by parasitic resistances in the grounding path. Moreover, the duration of the ZVS transition state T _ZVS depends on when the resonant capacitor C _rMV will be discharged to the voltage level of C _fMV , i.e., 0 V to -2 kV considering the worst case for the M-S4T prototype. With larger magnetizing current i _m , the discharge speed (dv/dt) is faster, and the duration T _ZVS is shorter. However, the voltage stress Δν _LVBN is irrespective of the specific i _m value because the voltage stress depends on the charge which translates to Δν _CrMV . This can also be verified by solving the impedance divider in FIG. 7C to arrive at the additional voltage stress Δν _LVBN in Equation 3, which does not contain i _m .

[00061] Equation 3: where the worst case of Δν _CrMV is -2 kV as previously mentioned, and C _branch1 is defined in

Equation 4.

[00062] Equation 4:

[00063] According to Equations 3-4, smaller C _{P_eq} and C _{N_eq} result in larger additional voltage stress Δν _LVBN , which means that device modules with smaller capacitances can exacerbate this issue. Through FIG. 7C, it can be better understood why cause 1 is significant during the ZVS transition state but not an issue during the active vectors. During the MV active vector, the filter capacitor C _fMV is in parallel with C _rMV in FIG. 7C to transfer energy between the MV output and the dc-link inductance (L _m ), and shunts i _m from leaking through other paths. Thus, much smaller current flows through the device capacitances, and actually Δν _CrMV would equal Δν _CfMV which is small switching ripple. On the other hand, during the LV active vector, a pair of LV devices is turned on with dc-link current flowing through for energy transfer, and the voltages that the other LV devices block are well defined by the LV filter capacitor voltage ν _CfMV .

[00064] To address the voltage stress issue from cause 1, in some embodiments of the present disclosure, C _xfmr1 (also shown as C _x1 in the figures) and C _xfmr2 (also shown as C _x2 in the figures) as shown in FIG. 10 can be connected between MFT LV terminals and ground to divert the current from flowing through the device capacitances. The capacitor transformers can divert current away from the semiconductor devices in the CSI bridges, such that the current through the devices and the voltage stress across the devices are reduced. The impedance divider in FIG. 7D can be solved to derive the additional voltage stress Δν _LVBN in Equations 5-6.

[00065] Equation 5:

[00066] Equation 6:

[00067] The additional voltage stress | Δν _LVBN I in Equation 5 with the parameters of the M-S4T prototype under the worst-case -2 kV Δν _CrMV and parameters C _xfmr = C _xfmr1 = C _xfmr2 is illustrated in FIG. 8. The sum of the top and bottom inter- winding capacitances of the MFT is directly measured. Though the top and the bottom inter-winding capacitances of the MFT are expected to have very similar values due to symmetrical transformer structure, to ensure a robust design, the top C _{ps_top} and the bottom C _{ps_bot} inter-winding capacitances are swept from equal to 50% differences in FIG. 8A. Furthermore, to ensure robustness, the equivalent capacitances C _{P_eq} and C _{N_eq} are swept from 20% of the values through 100% to 500% in FIG. 8B, though the capacitance variations of the devices are typically less than 200% close to the nominal voltage, hi FIGs. 8C-D, parameter sweepings on only C _{P_eq} variation and only C _{N_eq} variation are depicted, respectively. According to FIG. 8, the additional voltage stress is limited to about 80 V with 30 nF C _xfmr , considering the application of the 650 V devices on the LV side. A standard capacitance value of 27 nF was thus applied.

[00068] In FIGs. 7A-D, the case that the magnetizing current (i _m ) concentrates on the MV side is shown. To further understand why i _m flows on the MV side is the key issue, the equivalent circuit of the case that the magnetizing current (i _m ) concentrates on the LV side is illustrated in FIG. 7E. It can be observed that both C _{P_eq} and C _{N_eq} are discharged by i _m , i.e., Δν _CN < 0, Δν _CP < 0, Δν _CrLV < 0, and Equation 7 holds.

[00069] Equation 7:

|Δν _CN I — |Δν _LVBN I < |Δν _xLV |

[00070] Therefore, the EVEN voltage variation in this case is within the envelope / voltage variation of v _xLV and there is no additional voltage stress. Finally, for this M-S4T prototype with a 6:1 MFT, concerning cause 1, the dual case on the MV side device is less of an issue. The reason is that in Equation 3, a factor of the MV resonant-capacitor voltage variation Δν _CrMV , e.g., -2 kV results in a relatively large stress for 650 V LV devices. However, the dual of this case is trivial, where a factor of the LV resonant-capacitor voltage variation Δν _CrLV , e.g., -2 kV/6 can result in a relatively small stress for 3.3 kV MV devices.

[00071] Cause 2 and Solution

[00072] While FIG. 7 shows the interaction of parasitic capacitances inside the M-S4T through the MV-to-LV ground path, i.e., Cause 1 , FIG. 9 illustrates the interaction between the converter and the LV-side grounding-loop inductance of the source, which corresponds to the LC-type resonance in FIG. 5, referred to herein as “cause 2” of the voltage stress. The converter can be replaced by its Norton equivalence and the rectifier in FIG. 3 can be replaced by its Thevenin equivalence with a 180 Hz common-mode voltage source. The high-frequency- excitation current source of the converter is the current through ground in FIG. 7C-D. C _{eq_conv} in FIG. 9 is the equivalent input capacitance of the M-S4T to the ground. In some embodiments of the present disclosure, to mitigate the LC resonance in FIG. 9, the corresponding LC resonant frequency where the LC parallel resonant tank’s impedance peaks can be shifted away from the excitation current source frequency (f _sw ) by adding C _add and damping resistor R _damp across the rectifier filter inductors in FIG. 3. In particular, the dampening resistor can be configured to damp out the LC oscillation between the rectifier filter and other inductances in the grounding loop and the equivalent capacitance of the CSI bridge and the transformer. The C _add can be configured to increase the equivalent capacitance of the CSI bridge and the transformer, such that the LC oscillation frequency can be decreased below the switching frequency of the transformer to mitigate the LC oscillation. The resonant frequency and the damping ratio of this equivalent circuit can be calculated as given by Equations 8 and 9.

[00073] Equation 8:

[00074] Equation 9:

[00075] Based on Equations 8 and 9, the final values of C _add and R _damp were selected to be 752 nF and 39 Ohm, respectively, for this exemplary embodiment. C _add can be much larger than C _{eq_conv} and hence can dominate the total capacitance seen by the rectifier.

[00076] FIG. 10 provides an exemplary topology addressing both Cause 1 and Cause 2. In the single-module case of FIG. 10A, the dual of the LV-side grounding capacitances including C _x1 and C _ad1 is similarly applied on the MV side. The LV-side grounding capacitances C _ad can be split among phases, because the filter capacitors with much smaller impedance are equivalent to short circuits in FIG. 7A. Note that if the MFT has a high turns ratio for step down, e.g., 6:1 in the M-S4T prototype, the LV-side stress referred to the MV side can be a small value to the MV devices as discussed, which means C _x2 can be optional. However, if the MFT has a unity turns ratio, the voltage stress referred from the other side can be non-negligible, which means C _x2 can be used. When FIG. 7 A is introduced, it has been discussed that the series-stacked module 2 is confronted with the same situation as the module

1, because the filter capacitors are short circuits in the analysis and the frequency concerning cause 1. Thus, the exemplary voltage stress mitigation techniques can be extended to the ISOP modules in FIG. 10B. The line-frequency voltage blocked by C _ad2 can be further reduced by lumping C _ad2 to the module closest to the MV ground, as shown in Fig. 10C. While a two- module case is illustrated in Fig. 10, a larger number of module is also possible as will be verified in the experimental section below.

[00077] Experimental Results with the Exemplary Voltage Stress Mitigation Techniques

[00078] The M-S4T prototype and setup in FIG. 2 were used to verify the existence of the voltage stress issue from the ground current as shown in FIGs. 5-6 in the single-module and the stacked-module tests. To verify the effectiveness of the proposed exemplary voltage stress mitigation techniques, C _xfmr , C _add , and R _damp were installed in FIG. 11, which shows an exemplary embodiment of the present disclosure, as compared to FIG. 3, depicting a conventional topology, where the parameters are selected as 27 nF, 752 nF, and 39 Ohm as discussed, respectively. C _x2 in Fig. 10C was not required in this M-S4T with 6:1 turns ratio MFTs.

[00079] FIG. 12 shows single module testing results at 1.5 kV peak with an exemplary voltage stress mitigation technique. Compared to FIG. 5 where the LC resonance results in voltage stress as high as 180%, the LC resonance is suppressed in FIG. 12. The LV device voltage ν _LVBN1 is within the transformer LV voltage ν _xLV1 envelope in FIG. 12A, which verifies the exemplary voltage stress mitigation techniques. Moreover, the MV device voltage ν _MVAN1 is within the transformer MV voltage v _xMV1 envelope. FIGs. 12B-D show the zoom- in waveforms of the device voltages on both the MV side and the LV side at different positions in a line cycle to further verify the effectiveness of the exemplary voltage stress mitigation techniques under single-module operation.

[00080] FIGs. 13 A- 13E show stacked module testing results under step change from 1.5 kV to 4 kV peak with the exemplary voltage stress mitigation techniques. Both 4 kV peak steady-state operation and step-change transient can be observed. Note that all the five modules in FIG. 11 were in operation in this experiment, where two modules’ output voltages are measured. Compared to FIG. 6 where the LVBN voltage is discharged out of the envelope of v _xLV with a voltage stress as high as 140%, the device voltage v _LVBN5 is within the transformer voltage envelopes v _xLV1 in FIGs. 13A-B under steady-state and transient conditions, which verifies the exemplary voltage stress mitigation techniques. Moreover, the MV device voltage ν _MVAN1 is within the transformer MV voltage v _xMV1 envelope. Finally, the MV output voltages of the stacked modules are balanced and sinusoidal. The zoom-in waveforms in FIG. 13C-E further verify the exemplary voltage stress mitigation techniques at different positions in a line cycle. The inherent parameter variations among the five modules in the prototype verify the robustness of the exemplary voltage stress mitigation techniques in this stacked-module experiment. To summarize, the experimental waveforms verify the effectiveness of the exemplary voltage stress mitigation techniques under both single-module and stacked-module conditions during both steady state and dynamics.

[00081] It is to be understood that the embodiments and claims disclosed herein are not limited in their application to the details of construction and arrangement of the components set forth in the description and illustrated in the drawings. Rather, the description and the drawings provide examples of the embodiments envisioned. The embodiments and claims disclosed herein are further capable of other embodiments and of being practiced and carried out in various ways. Also, it is to be understood that the phraseology and terminology employed herein are for the purposes of description and should not be regarded as limiting the claims.

[00082] Accordingly, those skilled in the art will appreciate that the conception upon which the application and claims are based may be readily utilized as a basis for the design of other structures, methods, and systems for carrying out the several purposes of the embodiments and claims presented in this application. It is important, therefore, that the claims be regarded as including such equivalent constructions.

[00083] Furthermore, the purpose of the foregoing Abstract is to enable the United States

Patent and Trademark Office and the public generally, and especially including the practitioners in the art who are not familiar with patent and legal terms or phraseology, to determine quickly from a cursory inspection the nature and essence of the technical disclosure of the application. The Abstract is neither intended to define the claims of the application, nor is it intended to be limiting to the scope of the claims in any way.