Title:
SOFTWARE DEFINED NETWORK WITH SELECTABLE LOW LATENCY OR HIGH THROUGHPUT MODE
Document Type and Number:
WIPO Patent Application WO/2018/076638
Kind Code:
A1
Abstract:
Encoding and decoding systems are provided for reduced latency at the decoder. In the encode error detection codewords are produced from source bits. The error detection codewords are then encoded with a systematic error correction encoder to produce a set of parity bits. All of the systematic code source bits and at least some of the parity bits are mapped to modulation symbols for transmission. In the decoder, two signal processings are performed in parallel, one based on soft bit decisions and the other based on hard bit decisions. The soft bit decisions are processed using a systematic error correction decoder. The hard bit decisions are processed by re-encoding error detection codewords to produce parity bits. If the produced parity bits match received parity bits, then the hard bit decisions are reliable and are output without waiting for the result of the systematic error correction decoder.
Inventors:
AHARONY AHIKAM (CA)
Application Number:
PCT/CN2017/081883
Publication Date:
May 03, 2018
Filing Date:
April 25, 2017
Export Citation:
Assignee:
HUAWEI TECH CO LTD (CN)
International Classes:
H04L1/00; H03M13/11
Foreign References:
| US20080240273A1 | 2008-10-02 | |||
| US9432053B1 | 2016-08-30 | |||
| CN1881477A | 2006-12-20 |
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