Title:
SOLDERING METHOD AND SEMICONDUCTOR MODULE MANUFACTURING METHOD
Document Type and Number:
WIPO Patent Application WO/2007/077688
Kind Code:
A1
Abstract:
Disclosed is a method for soldering semiconductor elements on bonding sections arranged
at a plurality of areas on a circuit board, respectively. The soldering method
is provided with a step of arranging the bonding sections in nonlinear arrangement
on at least three areas on the circuit board; a step of arranging the semiconductor
elements on the bonding sections through a solder; a step of placing a guard over
the at least three semiconductor elements nonlinearly arranged; and a step of
melting the solder while applying pressure to the semiconductor elements by
the guard, and thus soldering the semiconductor elements on the bonding sections.
As a result, at the time of soldering the semiconductor elements on the circuit
board, fluctuation in solder thickness at the bonding sections is suppressed.
Inventors:
KIMBARA MASAHIKO (JP)
Application Number:
PCT/JP2006/323184
Publication Date:
July 12, 2007
Filing Date:
November 21, 2006
Export Citation:
Assignee:
TOYOTA JIDOSHOKKI KK (JP)
KIMBARA MASAHIKO (JP)
KIMBARA MASAHIKO (JP)
International Classes:
H01L21/52; B23K1/00; B23K3/00; H01L25/07; H01L25/18; H05K3/34
Foreign References:
| JPH08191130A | 1996-07-23 | |||
| JPH0357230A | 1991-03-12 | |||
| JPH11260859A | 1999-09-24 | |||
| JP2001036224A | 2001-02-09 | |||
| JPH06163634A | 1994-06-10 | |||
| JPH10189845A | 1998-07-21 | |||
| JP2001257458A | 2001-09-21 | |||
| JPH11260859A | 1999-09-24 | |||
| JP2000332052A | 2000-11-30 | |||
| JPH06163612A | 1994-06-10 | |||
| JP2001121259A | 2001-05-08 |
Attorney, Agent or Firm:
ONDA, Hironori (Ohmiya-cho 2-chome Gifu-sh, Gifu 31, JP)
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