SPIN LOGIC DEVICE, PROCESSING IN-MEMORY DEVICE, HALF ADDER AND FULL ADDER

WIPO Patent Application WO/2022/241735

A1

Provided in the embodiments of the present disclosure are a spin logic device, a processing in-memory device, a half adder and a full adder. In the spin logic device, a magnetic unit comprises a spin Hall effect layer and a ferromagnetic layer, which are arranged in a stacking direction. The magnetization direction of the ferromagnetic layer is in the stacking direction. The magnetic unit comprises a first port on a first side, a second port on a second side opposite the first side, and a third port which is located between the first port and the second port and is on a third side. A first negative differential resistor is coupled between the first port and the third port. A second negative differential resistor is coupled between the second port and the third port. The spin logic device may generate significantly different output voltages on two ends of the first negative differential resistor and/or the second negative differential resistor, so as to identify different logic outputs. In this way, a voltage type spin logic device can be implemented, thereby reducing the power consumption of the device, and improving the performance of the device.

ZHANG XIAOZHONG (CN)
PU YUCHEN (CN)
LU ZIYAO (CN)
MOU HONGMING (CN)
LI WENJING (CN)
YE LI (CN)

PCT/CN2021/094983

November 24, 2022

May 20, 2021

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HUAWEI TECH CO LTD (CN)
UNIV TSINGHUA (CN)

H01L43/06; G11C11/16

CN105280214A	2016-01-27
CN112514090A	2021-03-16
CN105514260A	2016-04-20
CN112466359A	2021-03-09
CN107134292A	2017-09-05
CN111354850A	2020-06-30
US20150200003A1	2015-07-16
US20180145691A1	2018-05-24

KING & WOOD MALLESONS (CN)

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