BACKGROUND

[0001] Spintronics is the study of intrinsic spin of the electron and its associated magnetic moment in solid-state devices. Spintronic logic are integrated circuit devices that use a physical variable of magnetization or spin as a computation variable. Such variables can be non-volatile (e.g., preserving a computation state when the power to an integrated circuit is switched off). Non-volatile logic can improve the power and computational efficiency by allowing architects to put a processor to un-powered sleep states more often and therefore reduce energy consumption. Existing spintronic logic generally suffer from high energy and relatively long switching times.

[0002] For example, large write current (e.g., greater than 100 mA/bit) and voltage

(e.g., greater than 0.7 V) are needed to switch a magnet (i.e., to write data to the magnet) in Magnetic Tunnel Junctions (MTJs). Existing Magnetic Random Access Memory (MRAM) based on MTJs also suffer from high write error rates (WERs) or low speed switching. For example, to achieve lower WERs, switching time is slowed down which degrades the performance of the MRAM. MTJ based MRAMs also suffer from reliability issues due to tunneling current in the spin filtering tunneling dielectric of the MTJs e.g., magnesium oxide (MgO).

BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

[0004] Fig. 1A illustrates a magnetization response to an applied magnetic field for a ferromagnet.

[0005] Fig. IB illustrates a magnetization response to an applied magnetic field for a paramagnet.

[0006] Fig. 1C illustrates a magnetization response to an applied charge current for a magnet connected to a Neel spin orbit material (NSOT) with topological anti-ferromagnet.

[0007] Fig. 2A illustrates a Neel spin orbit (NESO) logic, according to some embodiments of the disclosure. [0008] Fig. 2B illustrates a spin orbit material stack at the input of a charge interconnect, according to some embodiments of the disclosure.

[0009] Fig. 2C illustrates a NESO material stack at the output of a charge interconnect, where the NESO stack applies a first magnetization to the magnet, according to some embodiments of the disclosure.

[0010] Fig. 2D illustrates a NESO material stack at the output of a charge interconnect, where the NESO stack applies a second magnetization to the magnet, according to some embodiments of the disclosure.

[0011] Figs. 3A-C illustrate the operating principle of NSOT which is used to switch a free magnet, in accordance to some embodiments.

[0012] Fig. 4 illustrates a NESO logic of Fig. 2A which is operable as a repeater, according to some embodiments.

[0013] Fig. 5 illustrates a NESO logic of Fig. 2A which is operable as an inverter, according to some embodiments.

[0014] Fig. 6 illustrates a top view of a layout of the NESO logic of Fig. 2A, according to some embodiments.

[0015] Fig. 7 illustrates a flowchart of a method for forming a NESO logic device of

Fig. 2A, according to some embodiments of the disclosure.

[0016] Fig. 8 illustrates a majority gate using NESO logic devices of Fig. 2A, according to some embodiments.

[0017] Fig. 9 illustrates a smart device or a computer system or a SoC (System-on-

Chip) with the NESO logic, according to some embodiments.

DETAILED DESCRIPTION

[0018] Various embodiments describe a Neel spin orbit (NESO) Logic which is a combination of various physical phenomena for spin-to-charge and charge-to-spin conversion, where the NESO logic comprises an input magnet and spin orbit coupling (SOC) structure having a stack of layers for spin-to-charge conversion. In some embodiments, spin- to-charge conversion is achieved via one or more layers with the inverse Rashba-Edelstein effect (or spin Hall effect) wherein a spin current injected from an input magnet produces a charge current. The sign of the charge current is determined by the direction of the injected spin and thus by the direction of magnetization.

[0019] In some embodiments, charge-to-spin conversion is achieved via Neel spin orbit torque (NSOT). In some embodiments, the charge current carried by the interconnect generates an electron current in the Neel Spin Orbit material (a topological anti-ferromagnet). Neel SOT materials are the antiferromagnetic counterparts of Rashba-Edelstein effect. The electron current through the NSOT material produces a staggered current induced field in the NSOT material. The NSOT material comprises layers of AFM materials as sub-lattices.

Each sub-lattice settles with a magnetization such that the adjacent sub-lattice in the stack has a different magnetization. For example, two magnetic sub-lattices of the topological anti- ferromagnets experience opposite Rashba-Edelstein coupling. In one instance, the first sub lattice experiences a positive equivalent Rashba field while the second sub-lattice experiences a negative equivalent Rashba field. The net effect is a switching of magnetization of the topological anti-ferromagnet, which in turn switches the magnet attached to the NSOT material.

[0020] There are many technical effects of various embodiments. For example, high speed operation of the logic (e.g., 100 picoseconds (ps)) is achieved via the use of magnetoelectric switching operating on semi-insulating nanomagnets. In some examples, switching energy is reduced (e.g., 1-10 attojoules (aJ)) because the current needs to be“on” for a shorter time (e.g., approximately 3 ps) in order to charge the capacitor. In some examples, in contrast to the spin current, here charge current does not attenuate when it flows through an interconnect. One figure of merit (FoM) for a magnetic logic is the ratio of magnetic switching energy (Esw) to corresponding bias energy (Eb). Spin transfer torque (STT) materials exhibit FoM around 10 ⁴ , which is high. This means that a high switching energy is needed to cause the STT materials to switch a magnet attached to the STT material. Conversely, NSOT materials show a FoM in a range of 1 to 10. This means NSOT can switch magnets with much less energy than STT based materials. As such, a highly efficient magnetic logic is achieved by the NESO logic of the various embodiments. Other technical effects will be evident from various embodiments and figures.

[0021] In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. It will be apparent, however, to one skilled in the art, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

[0022] Note that in the corresponding drawings of the embodiments, signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.

[0023] The term“free” or“unfixed” here with reference to a magnet refers to a magnet whose magnetization direction can change along its easy axis upon application of an external field or force (e.g., Oersted field, spin torque, etc.). Conversely, the term“fixed” or “pinned” here with reference to a magnet refers to a magnet whose magnetization direction is pinned or fixed along an axis and which may not change due to application of an external field (e.g., electrical field, Oersted field, spin torque,).

[0024] Here, perpendicularly magnetized magnet (or perpendicular magnet, or magnet with perpendicular magnetic anisotropy (PMA)) refers to a magnet having a magnetization which is substantially perpendicular to a plane of the magnet or a device. For example, a magnet with a magnetization which is in a z-direction in a range of 90 (or 270) degrees +/- 20 degrees relative to an x-y plane of a device.

[0025] Here, an in-plane magnet refers to a magnet that has magnetization in a direction substantially along the plane of the magnet. For example, a magnet with a magnetization which is in an x or y direction and is in a range of 0 (or 180 degrees) +/- 20 degrees relative to an x-y plane of a device.

[0026] The term“device” may generally refer to an apparatus according to the context of the usage of that term. For example, a device may refer to a stack of layers or structures, a single structure or layer, a connection of various structures having active and/or passive elements, etc. Generally a device is a three dimensional structure with a plane along the x-y direction and a height along the z direction of an x-y-z Cartesian coordinate system. The plane of the device may also be the plane of an apparatus which comprises the device.

[0027] Throughout the specification, and in the claims, the term "connected" means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices.

[0028] The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices. [0029] The term“adjacent” here generally refers to a position of a thing being next to

(e.g., immediately next to or close to with one or more things between them) or adjoining another thing (e.g., abutting it).

[0030] The term "circuit" or“module” may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function.

[0031] The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."

[0032] The term“scaling” generally refers to converting a design (schematic and layout) from one process technology to another process technology and subsequently being reduced in layout area. The term“scaling” generally also refers to downsizing layout and devices within the same technology node. The term“scaling” may also refer to adjusting (e.g., slowing down or speeding up - i.e. scaling down, or scaling up respectively) of a signal frequency relative to another parameter, for example, power supply level.

[0033] The terms“substantially,”“close,”“approximately,”“ near,” and“about,” generally refer to being within +/- 10% of a target value. For example, unless otherwise specified in the explicit context of their use, the terms“substantially equal,”“about equal” and“approximately equal” mean that there is no more than incidental variation between among things so described. In the art, such variation is typically no more than +/-l0% of a predetermined target value.

[0034] Unless otherwise specified the use of the ordinal adjectives“first,”“second,” and“third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

[0035] For the purposes of the present disclosure, phrases“A and/or B” and“A or B” mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase“A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0036] The terms“left,”“right,”“front,”“back,”“top,� �“bottom,”“over,”“under,” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. For example, the terms“over,” “under,”“front side,”“back side,”“top,”“bottom,”“over,”“under,” and“on” as used herein refer to a relative position of one component, structure, or material with respect to other referenced components, structures or materials within a device, where such physical relationships are noteworthy. These terms are employed herein for descriptive purposes only and predominantly within the context of a device z-axis and therefore may be relative to an orientation of a device. Hence, a first material“over” a second material in the context of a figure provided herein may also be“under” the second material if the device is oriented upside-down relative to the context of the figure provided. In the context of materials, one material disposed over or under another may be directly in contact or may have one or more intervening materials. Moreover, one material disposed between two materials may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first material“on” a second material is in direct contact with that second material. Similar distinctions are to be made in the context of component assemblies.

[0037] The term“between” may be employed in the context of the z-axis, x-axis or y- axis of a device. A material that is between two other materials may be in contact with one or both of those materials, or it may be separated from both of the other two materials by one or more intervening materials. A material“between” two other materials may therefore be in contact with either of the other two materials, or it may be coupled to the other two materials through an intervening material. A device that is between two other devices may be directly connected to one or both of those devices, or it may be separated from both of the other two devices by one or more intervening devices.

[0038] Here, multiple non-silicon semiconductor material layers may be stacked within a single fin structure. The multiple non-silicon semiconductor material layers may include one or more“P-type” layers that are suitable (e.g., offer higher hole mobility than silicon) for P-type transistors. The multiple non-silicon semiconductor material layers may further include one or more one or more“N-type” layers that are suitable (e.g., offer higher electron mobility than silicon) for N-type transistors. The multiple non-silicon

semiconductor material layers may further include one or more intervening layers separating the N-type from the P-type layers. The intervening layers may be at least partially sacrificial, for example to allow one or more of a gate, source, or drain to wrap completely around a channel region of one or more of the N-type and P-type transistors. The multiple non-silicon semiconductor material layers may be fabricated, at least in part, with self-aligned techniques such that a stacked CMOS device may include both a high-mobility N-type and P-type transistor with a footprint of a single transistor.

[0039] For the purposes of present disclosure, the terms“spin” and“magnetic moment” are used equivalently. More rigorously, the direction of the spin is opposite to that of the magnetic moment, and the charge of the particle is negative (such as in the case of electron). [0040] It is pointed out that those elements of the figures having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0041] For purposes of the embodiments, the transistors in various circuits and logic blocks described here are metal oxide semiconductor (MOS) transistors or their derivatives, where the MOS transistors include drain, source, gate, and bulk terminals. The transistors and/or the MOS transistor derivatives also include Tri-Gate and FinFET transistors, Gate All Around Cylindrical Transistors, Tunneling FET (TFET), Square Wire, or Rectangular Ribbon Transistors, ferroelectric FET (FeFETs), or other devices implementing transistor functionality like carbon nanotubes or spintronic devices. MOSFET symmetrical source and drain terminals i.e., are identical terminals and are interchangeably used here. A TFET device, on the other hand, has asymmetric Source and Drain terminals. Those skilled in the art will appreciate that other transistors, for example, Bi-polar junction transistors— BJT PNP/NPN, BiCMOS, CMOS, eFET, etc., may be used without departing from the scope of the disclosure. The term“MN” indicates an n-type transistor (e.g., NMOS, NPN BJT, etc.) and the term“MP” indicates a p-type transistor (e.g., PMOS, PNP BJT, etc.).

[0042] Fig. 1A illustrates a magnetization hysteresis plot 100 for ferromagnet (FM)

101. The plot shows magnetization response to an applied magnetic field for ferromagnet 101. The x-axis of plot 100 is magnetic field Ή’ while the y-axis is magnetization‘m’. For FM 101, the relationship between Ή’ and‘m’ is not linear and results in a hysteresis loop as shown by curves 102 and 103. The maximum and minimum magnetic field regions of the hysteresis loop correspond to saturated magnetization configurations 104 and 106, respectively. In saturated magnetization configurations 104 and 106, FM 101 has stable magnetizations. In the zero magnetic field region 105 of the hysteresis loop, FM 101 does not have a definite value of magnetization, but rather depends on the history of applied magnetic fields. For example, the magnetization of FM 101 in configuration 105 can be either in the +X direction or the -x direction for an in-plane FM (e.g., FM with magnetization which is along the plane of a device). As such, changing or switching the state of FM 101 from one magnetization direction (e.g., configuration 104) to another magnetization direction (e.g., configuration 106) is time consuming resulting in slower nanomagnets response time.

It is associated with the intrinsic energy of switching proportional to the area in the graph contained between curves 102 and 103.

[0043] In some embodiments, FM 101 is formed of CFGG (i.e., Cobalt (Co), Iron

(Fe), Germanium (Ge), or Gallium (Ga) or a combination of them). In some embodiments, FM 101 comprises one or more of Co, Fe, Ni alloys and multilayer hetro-stmctures, various oxide ferromagnets, garnets, or Heusler alloys. Heusler alloys are ferromagnetic metal alloys based on a Heusler phase. Heusler phases are intermetallic with certain composition and face-centered cubic crystal structure. The ferromagnetic property of the Heusler alloys are a result of a double-exchange mechanism between neighboring magnetic ions. In some embodiments, the Heusler alloy includes one of: Cu ₂ MnAl, Cu ₂ MnIn, Cu ₂ MnSn, Ni ₂ MnAl, NFMnln, NFMnSn, NFMnSb, NFMnGa Co ₂ MnAl, Co ₂ MnSi, Co ₂ MnGa, Co ₂ MnGe, Pd ₂ MnAl, Pd ₂ MnIn, Pd ₂ MnSn, Pd ₂ MnSb, Co ₂ FeSi, Co ₂ FeAl, Fe ₂ VAl, Mn ₂ VGa, Co ₂ FeGe, MnGa, or MnGaRu.

[0044] Fig. IB illustrates magnetization plot 120 for paramagnet 121. Plot 120 shows the magnetization response to an applied magnetic field for paramagnet 121. The x-axis of plot 120 is magnetic field Ή’ while the y-axis is magnetization‘m’. A paramagnet, as opposed to a ferromagnet, exhibits magnetization when a magnetic field is applied to it. Paramagnets generally have magnetic permeability greater or equal to one and hence are attracted to magnetic fields. Compared to plot 100, the magnetic plot 120 of Fig. IB does not exhibit hysteresis which allows for faster switching speeds and smaller switching energies between the two saturated magnetization configurations 124 and 126 of curve 122. In the middle region 125, paramagnet 121 does not have any magnetization because there is no applied magnetic field (e.g., H=0). The intrinsic energy associated with switching is absent in this case.

[0045] In some embodiments, paramagnet 121 comprises a material which includes one or more of: Platinum(Pt), Palladium (Pd), Tungsten (W), Cerium (Ce), Aluminum (Al), Lithium (Li), Magnesium (Mg), Sodium (Na), CnCL (chromium oxide), CoO (cobalt oxide), Dysprosium (Dy), Dy ₂ 0 (dysprosium oxide), Erbium (Er), EnCL (Erbium oxide), Europium (Eu), EU2O3 (Europium oxide), Gadolinium (Gd), Gadolinium oxide (Gd ₂ 0 _{3 )} , FeO and Fe^Os (Iron oxide), Neodymium (Nd), Nd ₂ 0 ₃ (Neodymium oxide), K0 ₂ (potassium superoxide), praseodymium (Pr), Samarium (Sm), Sm ₂ 0 ₃ (samarium oxide), Terbium (Tb), Tb ₂ 0 ₃ (Terbium oxide), Thulium (Tm), Tm ₂ 0 ₃ (Thulium oxide), or V ₂ 0 ₃ (Vanadium oxide). In some embodiments, paramagnet 121 comprises dopants which include one or more of: Ce,

Cr, Mn, Nb, Mo, Tc, Re, Nd, Gd, Tb, Dy, Ho, Er, Tm, or Yb. In various embodiments, the magnet can be either a FM or a paramagnet.

[0046] Fig. 1C illustrates a magnetization response to an applied magnetic field for a ferromagnet connected to a Neel spin orbit material or Neel spin orbit torque (NSOT) material 132 with topological anti-ferromagnet. Plot 130 shows that magnetization functions l33a and l33b have hysteresis. Neel SOT materials are the antiferromagnetic counterparts of Rashba Edelstein effect. The electron current I _c produces a staggered current induced field in the NSOT material 132. The NSOT material comprises layers of AFM materials as sub lattices. Each sub-lattice settles with a magnetization such that the adjacent sub-lattice in the stack has a different magnetization. In this example, negative charge current I _c results in the NSOT material 132 having a magnetization in the -x direction in the topological anti- ferromagnet of the NSOT material. This magnetization provides a Rashba-Edelstein like coupling to FM 131, causing FM 131 to establish a magnetization (e.g., in the +X direction). Continuing with this example, positive charge current I _c results in the NSOT material 132 having a magnetization in the +X direction in the topological antiOferromagnet of the NSOT material. This magnetization provides a Rashba-Edelstein like coupling to the FM 131, causing the FM 131 to establish a magnetization (e.g., in the -x direction). In some embodiments, the magnet 131 can be a paramagnet instead of a ferromagnet. In some embodiments, by combining NSOT material 132 with paramagnet 131, switching speeds of paramagnet as shown in Fig. IB are achieved. In some embodiments, the hysteresis behavior of FM 131, as shown in Fig. 1C, is associated with the exchange coupling of the AFM.

[0047] Fig. 2A illustrates a Neel spin orbit (NESO) logic 200, according to some embodiments of the disclosure. Fig. 2B illustrates a spin orbit material stack at the input of a charge interconnect, according to some embodiments of the disclosure. Fig. 2C illustrates a NESO material stack at the output of a charge interconnect, where the NESO stack applies a first magnetization to the magnet, according to some embodiments of the disclosure. Fig. 2D illustrates a NESO material stack at the output of a charge interconnect, where the NESO stack applies a second magnetization to the magnet, according to some embodiments of the disclosure.

[0048] In some embodiments, NESO logic 200 comprises a first magnet 201, a spin- orbit coupling structure having a stack of layers (e.g., layers 202, 203, and 204, also labeled as 202a/b, 203a/b, and 204a/b), interconnecting conductor 205 (e.g., a non-magnetic charge conductor), NSOT structure 206 (206a/b), second magnet 207, first contact 209a, and second contact 209b.

[0049] In some embodiments, the first and second magnets 201 and 207, respectively, have in-plane magnetic anisotropy. For example, first and second magnets 201 and 207, respectively, are free conducting magnets with in-plane magnetization along the y-axis with reference to an x-y plane of a device having NESO logic 200. [0050] In some embodiments, first magnet 201 comprises first and second portions, wherein the first portion of first magnet 201 is adjacent to the SOC structure having stack of layers (e.g., layers 202a, 203a, and 204a), and wherein the second portion of first magnet 201 is adjacent to NSOT structure 206b. In some embodiments, second magnet 207 comprises first and second portions, wherein the first portion of second magnet 207 is adjacent to the NSOT structure 206a, and wherein the second portion of second magnet 207 is adjacent to another SOC structure having a stack of layers (e.g., layers 202b, 203b, and 204b).

[0051] In some embodiments, conductor 205 (or charge interconnect) is coupled to at least a portion of the SOC structure having a stack of layers (e.g., one of layers 202a, 203a, or 204a). For example, conductor 205 is coupled to layer 204a of the stack.

[0052] In some embodiments, the stack of layers is to provide an inverse Rashba-

Edelstein effect (or inverse spin Hall effect). In some embodiments, the stack of layers provide spin-to-charge conversion where a spin current J _s or 7 _S is injected from first magnet 201 (also referred to as the input magnet) and charge current I _c is generated by the stack of layers. This charge current I _c is provided to conductor 205 (e.g., charge interconnect). In contrast to spin current, charge current does not attenuate in conductor 205. The direction of the charge current I _c depends on the direction of magnetization of first magnet 201. In some embodiments, the charge current I _c determines the magnetization of NSOT layer 206a which exerts Neel spin orbit torque on second magnet layer 207, and the direction of the magnetization of the NSOT layer 206a in direct contact with the second magnet 207 determines the magnetization of second magnet 207. The same dynamics occurs by NSOT structure 206b which exerts Neel spin orbit torque on first magnet 201 according to input charge current on conductor 21 la.

[0053] In this example, the length of first magnet 201 is L _m , the width of conductor

205 is W _c , the length of conductor 205 from the interface of layer 204a to ME para-electric structure 206a is L _c , t _c is the thickness of the magnets 201 and 207, and t _N so _T is the thickness of NSOT structure 206a. In some embodiments, conductor 205 comprises a material including one of: Cu, Ag, Al, Au, Co, or Graphene.

[0054] In some embodiments, the input and output charge conductors (21 la and

21 lb, respectively) and associated spin-to-charge and charge-to-spin converters are provided. In some embodiments, input charge current I _C har _g e(iN) (or IIN) is provided on interconnect 21 la (e.g., charge interconnect made of same material as interconnect 205). In some

embodiments, interconnect 21 la is coupled to first magnet 201 via NSOT structure 206b. In some embodiments, interconnect 21 la is orthogonal to first magnet 201. For example, interconnect 21 la extends in the +x direction while first magnet 201 extends in the -y direction. In some embodiments, I _C har _ge (iN) is converted to a corresponding magnetic polarization of 201 by NSOT structure 206b. The materials for NSOT structure 206a/b are the same as the materials of NSOT structure 206.

[0055] In some embodiments, an output interconnect 21 lb is provided to transfer output charge current I _C har _g e(ouT) to another logic or stage. In some embodiments, the output interconnect 21 lb is coupled to second magnet 207 via a stack of layers that exhibit spin Hall effect and/or Rashba-Edelstein effect. For example, layers 202b, 203b, and 204b are provided as a stack to couple output interconnect 21 lb with second magnet 207. Material wise, layers 202b, 203b, and 204b are formed of the same material as layers 202a, 203a, and 204a, respectively.

[0056] In some embodiments, the charge current carried by the interconnect (e.g.,

21 la or 205) generates an electron current in the NSOT structure 206a/b (a topological anti- ferromagnet). Neel SOT materials are the anti-ferromagnetic counterparts of Rashba Edelstein effect. The electron current produces a staggered current induced field in the NSOT material of NSOT structure 206a/b. The NSOT material comprises layers of AFM materials as sub-lattices. Each sub-lattice settles with a magnetization such that the adjacent sub-lattice in the stack has a different magnetization. For example, two magnetic sub-lattices of the topological anti-ferromagnets experience opposite Rashba Edelstein coupling. In one instance, the first sub-lattice experiences a positive equivalent Rashba field where the second sub-lattice experiences a negative equivalent Rashba field. The net effect is a switching of magnetization of the topological anti-ferromagnet, which in turn switches the magnet (e.g., 201 or 207) attached to the NSOT material.

[0057] In some embodiments, first magnet 201 injects a spin polarized current into the high spin-orbit coupling (SOC) material stack (e.g., layers 202a, 203a, and 204a). The spin polarization is determined by the magnetization of first magnet.

[0058] In some embodiments, the stack comprises i) an interface 203a/b with a high density 2D (two dimensional) electron gas and with high SOC formed between 202a/b and 204a/b materials such as Ag or Bi, or ii) a bulk material 204 with high Spin Hall Effect (SHE) coefficient such as Ta, W, or Pt.

[0059] In some embodiments, the stack of layers providing spin orbit coupling comprises: a first layer 202a/b comprising Ag, wherein the first layer is adjacent to first magnet 209a/b; and a second layer 204a/b comprising Bi or W, wherein second layer 204a/b is adjacent to first layer 202a/b and to a conductor (e.g., 205, 21 lb). In some embodiments, a third layer 203a/b (having material which is one or more of Ta, W, or Pt) is sandwiched between first layer 202a/b and second layer 204a/b as shown. In some embodiments, the stack of layers comprises a material which includes one of: b-Ta, b-W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table groups.

[0060] In some embodiments, magnets 201 and 207 are perpendicular magnets. In one such example, 2D materials for the SOC structure are used to convert spin to charge. In some embodiments, the 2D materials include one or more of: Mo, S, W, Se, Graphene, M0S2, WSe2, WS2, or MoSe2. In some embodiments, the 2D materials include an absorbent which includes one or more of: Cu, Ag, Pt, Bi, Fr, or H absorbents. In some embodiments, the SOC structures comprise a spin orbit material which includes materials that exhibit Rashba- Bychkov effect. In some embodiments, material which includes materials that exhibit Rashba-Bychkov effect comprises materials ROCI12, where‘R’ includes one or more of: La, Ce, Pr, Nd, Sr, Sc, Ga, Al, or In, and where“Ch” is a chalcogenide which includes one or more of: S, Se, or Te.

[0061] In some embodiments, a spacer (or template layer) is formed between the first magnet 201 and the injection stack. In some embodiments, this spacer is a templating metal layer which provides a template for forming first magnet 201. In some embodiments, the metal of the spacer, which is directly coupled to first magnet 201, is a noble metal (e.g., Ag, Cu, or Au) doped with other elements from Group 4d and/or 5d of the Periodic Table. In some embodiments, first magnet 201 (and by extension first semi-insulating magnet 209a) are sufficiently lattice matched to Ag (e.g., a material which is engineered to have a lattice constant close (e.g., within 3%) to that of Ag).

[0062] Here, sufficiently matched atomistic crystalline layers refer to matching of the lattice constant‘a’ within a threshold level above which atoms exhibit dislocation which is harmful to the device (for instance, the number and character of dislocations lead to a significant (e.g., greater than 10%) probability of spin flip while an electron traverses the interface layer). For example, the threshold level is within 5% (e.g., threshold levels in the range of 0% to 5% of the relative difference of the lattice constants). As the matching improves (e.g., matching gets closer to perfect matching), spin injection efficiency from spin transfer from first magnet 201 to first ISOC (inverse spin orbit coupling) stacked layer increases. Poor matching (e.g., matching worse than 5%) implies dislocation of atoms that is harmful for the device. [0063] In some embodiments, a transistor (e.g., p-type transistor MP1) is coupled to first conducting magnet 201 via contact 209a (e.g., Cu, Al, Ag, or Au, etc.). In this example, the source terminal of MP1 is coupled to a supply V _dd , the gate terminal of MP1 is coupled to a control voltage V _ci (e.g., a switching clock signal, which switches between V _dd and ground), and the drain terminal of MP1 is coupled to first magnet 201 via contact 209a. In some embodiments, contact 209a is made of any suitable conducting material is used to connect the transistor to the first magnet 201. In some embodiments, the current I _drive from transistor MP1 generates spin current into the stack of layers (e.g., layers 202a, 203a, and 204a).

[0064] In some embodiments, along with the p-type transistor MP1 connected to V _dd

(or an n-type transistor connected to V _dd but with gate overdrive above V _dd ), an n-type transistor MN1 is provided which couples to first magnet 201 via contact 209a, where the n- type transistor is operable to couple ground (or 0 V) to first magnet 201. In some

embodiments, an n-type transistor MN2 is provided which is operable to couple ground (or 0V) to second magnet 207 via contact 209b.

[0065] In some embodiments, a p-type transistor MP2 is provided which is operable to couple power supply (V _dd or -V _dd ) to second conducting magnet 207 via contact 209b. For example, when clock is low (e.g., V _ci =0 V), then transistor MP1 is on and V _dd is coupled to first conducting magnet 201 (e.g., power supply is V _dd ) and 0 V is coupled to second conducting magnet 207. This provides a potential difference for charge current to flow. Continuing with this example, when clock is high (e.g., V _ci =V _dd and power supply is V _dd ), then transistor MP1 is off, transistor MN1 is on, and transistor MN2 is off. As such, 0 V is coupled to first conducting magnet 201.

[0066] In some embodiments, the power supply is a negative power supply (e.g., -

V _dd ). In that case, then transistor MPl’s source is connected to 0 V, and transistor MNl’s source is connected to -V _dd , and transistor MN2 is on. When V _ci = 0 V and power supply is - V _dd , then transistor MN1 is on, and transistor MP1 is off, and transistor MN2 (whose source is at -V _dd ) is off and MP2 whose source is 0 V is on. In this case, -V _dd is coupled to input magnet 201 and 0 V is coupled to output magnet 207 via respective contacts 209a/b. This also provides a path for charge current to flow. Continuing with this example, when the clock is high (e.g., V _ci =-V _dd and power supply is -V _dd ), then transistor MP1 is off, transistor MN1 is on, and transistor MN2 is off. As such, 0 V is coupled to input magnet 201.

[0067] Table 1 summarizes transduction mechanisms for converting charge current to magnetization for bulk materials and interfaces. Table 1: Transduction mechanisms for Charge to Spin Conversion

[0068] The charge current I _c , carried by interconnect 205, produces a staggered current induced field in the NSOT material of NSOT structure 206a. The NSOT material comprises layers of AFM materials as sub-lattices. Each sub-lattice settles with a

magnetization such that the adjacent sub-lattice in the stack has a different magnetization.

For example, two magnetic sub-lattices of the topological anti-ferromagnets experience opposite Rashba-Edelstein coupling. The net effect is a switching of magnetization of the topological anti-ferromagnet, which in turn switches the second magnet 207 attached to the NSOT material of structure 206a.

[0069] In some embodiments, materials for the first and second magnets 201 and 207 have saturated magnetization M _s and effective anisotropy field ER. Saturated magnetization M _s is generally the state reached when an increase in applied external magnetic field H cannot increase the magnetization of the material. Anisotropy Hk generally refers material properties that are highly directionally dependent.

[0070] In some embodiments, materials for first and second magnets 201 and 207, respectively, are non- ferromagnetic elements with strong paramagnetism which have a high number of unpaired spins but are not room temperature ferromagnets. A paramagnet, as opposed to a ferromagnet, exhibits magnetization when a magnetic field is applied to it. Paramagnets generally have magnetic permeability greater or equal to one and hence are attracted to magnetic fields. In some embodiments, magnets 201 and 207 comprise paramagnets with hexagonal lattice structure.

[0071] In some embodiments, NSOT structure 206a/b is formed of a material which includes one of: MroXY, where‘X’ includes one of Au, Ag, or Cu; and where Ύ’ includes one of: As, P, Sb, Bi, or N.

[0072] Figs. 3A-C illustrate the operating principle of NSOT which is used to switch a free magnet, in accordance to some embodiments. Fig. 3A illustrates a lattice structure 140 of a NSOT material comprising Mn, As, and Cu (e.g., M CuAs). The anti-ferromagnet (AFM) of NSOT is organized in distinct layers such as layers 132i_ _h , where‘n’ is an integer greater than one. The separate layers of AFM within the NSOT lattice results in a topological AFM. Upon flow of charge current along the x-direction through the NSOT lattice structure 140, each AFM of the NSOT establishes a magnetization in the y-direction such that magnetization of one AFM layer is different from the magnetization of the adjacent AFM layer. For example, a charge current flow in the x-direction generates spin current in the -y direction, which in turn generates a corresponding magnetization direction in the AFM layer. In this example, the AFM layer adjacent to the one described above generates spin current (and hence magnetization) in the +y direction.

[0073] Fig. 3B illustrates an anticlockwise texture of spins in AFM layer 132i of the

NSOT lattice structure 140 when observed from the top of the structure 140 towards the y- direction. Here, an example magnetization of AFM 132i is illustrated as l33a.

[0074] Fig. 3C illustrates a clockwise texture of spins in an adjacent AFM layer l32 ₂ of the NSOT lattice structure 140 when observed from the top of the structure 140 towards the y-direction. Here, an example magnetization of AFM l32 ₂ is illustrated as 133b. Each AFM layer in the lattice structure 140 may exhibit a Rashba-Edelstein effect opposite to the Rashba-Edelstein effect of the adjacent AFM layer. This is because Rashba-Edelstein effect is caused by a two dimensional (2D) electron gas. Compared to just Rashba-Edelstein as observed in traditional spin coupling materials, NSOT material exhibits higher stability than traditional spin coupling material because of the AFM aspect of the NSOT material in addition to the Rashba-Edelstein effect.

[0075] Fig. 4 illustrates a NESO logic 400 of Fig. 2A which is operable as a repeater, according to some embodiments. In some embodiments, to configure the NESO logic as a repeater, a portion of the stack of the layers (e.g., layer 204) is coupled to ground, first magnet 201 (input magnet) is coupled to a negative supply (e.g., -V _dd ), and second magnet 207 (output magnet) is coupled to ground (e.g., 0V). For -V _dd supply voltage applied to the input magnet, a spin current polarized in the same direction as the nanomagnets is injected into the high SOC region (e.g., stack having layers 202, 203, and 204). The inverse Rashba- Edelstein effects (or inverse SOC effects of stack having layers 202, 203, and 204) produce a charge current proportional to the injected spin current. The injected charge current I _c produces a magnetization on the topological AFM of the NSOT 206a/b, producing Neel spin orbit torque on output magnet 207. When NESO device 400 operates as a repeater, magnetization of input magnet 201 is same as the magnetization of output magnet 207.

[0076] Fig. 5 illustrates a NESO logic 500 of Fig. 2A which is operable as an inverter, according to some embodiments. In some embodiments, a portion of the stack of the layers (e.g., layer 204) is coupled to ground, first magnet 201 (input magnet) is coupled to a positive supply (e.g., +V _dd ), and second magnet 207 (output magnet) is coupled to ground (e.g., OV). The logic inverter operation of SOL device 520 works by injection of a spin current from input magnet 201 with a +V _dd supply voltage. The inverse Rashba-Edelstein effects (or SOC effects of stack having layers 202, 203, and 204) produces charge current I _c which is injected into conductor 205. The injected charge current I _c produces a

magnetization on the topological AFM of the NSOT 206a/b, producing Neel spin orbit torque on output magnet 207. The magnetization direction of the topological AFM in this case is parallel but opposite of that in Fig 4, producing Neel spin orbit torque on the detector free layer 207. When NESO logic 500 operates as an inverter, magnetization of input magnet 201 is opposite to the magnetization of output magnet 207.

[0077] NESO devices of some embodiments provide logic cascadability and unidirectional signal propagation (e.g., input-output isolation). For example, one NESO logic can be coupled to another logic NESO and so on. In some examples, the unidirectional nature of logic is ensured due to large difference in impedance for injection path versus detection path. The injector is essentially a metallic spin valve with spin to charge transduction with RA (resistance area) products of approximately 10 mOhm.micron ² . The detection path is a low leakage capacitance with RA products much larger than 1

MOhm.micron ² in series with the resistance of the FM capacitor plate with estimated resistance greater than 500 Ohms.

[0078] Fig. 6 illustrates a top view 600 of a layout of the NESO logic of Fig. 2A, according to some embodiments. An integration scheme for SOL devices with CMOS drivers for power supply and clocking is shown in the top view. Here, transistor MP1 is formed in the active region 601, and power supply is provided via metal layer 3 (M3) indicated as 606. The gate terminal 604 of transistor MP1 is coupled to a supply interconnect 605 through via or contact 603. In some embodiments, M3 layer 607 is coupled to ground which provides ground supply to layer 204. In some embodiments, another transistor can be formed in active region 602 with gate terminal 610. Here, 608 and 609 are contact vias to the power supply line. The density of integration of the devices exceeds that of CMOS since an inverter operation can be achieved within 2.5P x 2M0. In some embodiments, since the power transistor MP1 can be shared among all the devices at the same clock phases, vertical integration can also be used to increase the logic density.

[0079] Fig. 7 illustrates a flowchart 700 of a method for forming a NESO logic device of Fig. 2A, according to some embodiments of the disclosure. While the blocks and/or operations are illustrated in a certain order, the order can be altered. For example, some blocks can be performed before or after others, and some can be performed

simultaneously with others.

[0080] At block 701, a magnet (e.g., magnet 201/207) is formed having a first portion and a second portion. In some embodiments, the magnet has in-plane magnetic anisotropy with magnetization pointing along a direction parallel to a plane of a device in the apparatus. In some embodiments, the magnet includes one or more of: Co, Fe, Ge, or Ga or a Heusler alloy, and wherein the Heusler alloy includes one or more of Co, Cu, Fe, Ga, Ge, In, Mn, Al, In, Sb, Si, Sn, Ni, Pd, Ru, or V. In some embodiments, the magnet is a paramagnet which includes one or more of: Pt, Pd, W, Ce, Al, Li, Mg, Na, Cr, Co, Dy, O, Er, Eu, Eu, Gd, Fe,

Nd, K, Pr, Sm, Tb, Tm, or V, or wherein the magnet is a paramagnet which comprises dopants which include one or more of: Ce, Cr, Mn, Nb, Mo, Tc, Re, Nd, Gd, Tb, Dy, Ho, Er, Tm, or Yb.

[0081] At block 702, a first structure (e.g., 202a, 203a, 204a) is formed, a portion of which is adjacent to the first portion of the magnet, wherein the first structure is to provide an inverse spin orbit coupling effect. In some embodiments, forming the first structure comprises forming a material which includes one or more of: b-Ta, b-W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table group, Ti, S, W, Mo, Se, B, Sb, Re, La, C, P, La, As, Sc, O, Bi, Ga, Al, Y, In, Ce, Pr, Nd, F, Ir, Mn, Pd, or Fe.

[0082] At block 703, a second structure (e.g., 206b) is formed adjacent to the second portion of the magnet, wherein the second structure comprises a Neel STO material (e.g., topological AFM). In some embodiments, NSOT material includes one of: MroXY, where ‘X’ includes one of Au, Ag, or Cu; and where Ύ’ includes one of: As, P, Sb, Bi, or N. In some embodiments, the antiferromagnetic material is a topological antiferromagnetic material with sub-lattices including a first sub-lattice and a second sub-lattice, wherein the first sub lattice has a first magnetization, and wherein the second sub-lattice has a second

magnetization, wherein the first and second magnetizations are parallel, but in opposite directions.

[0083] In some embodiments, the method comprises forming a first conductor (e.g.,

21 la) adjacent to the second structure; and forming a second conductor (205) adjacent to a portion of the first structure.

[0084] Fig. 8 illustrates a majority gate 800 using NESO logic devices of Fig. 2A, according to some embodiments. A charge mediated majority gate is proposed using the spin orbit coupling and magnetoelectric switching. A charge mediated majority gate is shown in Fig. 8. Majority gate 800 comprises at least three input stages 801, 802, and 803 with their respective conductors 205 , , and 205 coupled to summing interconnect 904. In some embodiments, summing interconnect 804 (e.g., made of the same materials as interconnect 205). In some embodiments, summing interconnect 804 is coupled to the output stage 805 which includes the second magnet 207. The three input stages 801, 802, and 803 share a common power/clock region therefore the power/clock gating transistor can be shared among the three inputs of the majority gate, in accordance with some embodiments. The input stages 801, 802, and 803 can also be stacked vertically to improve the logic density, in accordance with some embodiments. The charge current at the output (Idiarge(ouT)) is the sum of currents I _Chi , Ich2, and I _Ch 3·

[0085] Fig. 9 illustrates a smart device or a computer system or a SoC (System-on-

Chip) with the NESO logic, according to some embodiments. Fig. 9 illustrates a block diagram of an embodiment of a mobile device in which flat surface interface connectors could be used. In some embodiments, computing device 1600 represents a mobile computing device, such as a computing tablet, a mobile phone or smart-phone, a wireless-enabled e- reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device 1600.

[0086] In some embodiments, computing device 1600 includes first processor 1610 with NESO logic, according to some embodiments discussed. Other blocks of the computing device 1600 may also include a NESO logic, according to some embodiments. The various embodiments of the present disclosure may also comprise a network interface within 1670 such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.

[0087] In some embodiments, processor 1610 can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor 1610 include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device 1600 to another device. The processing operations may also include operations related to audio I/O and/or display I/O. [0088] In some embodiments, computing device 1600 includes audio subsystem

1620, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 1600, or connected to the computing device 1600. In one embodiment, a user interacts with the computing device 1600 by providing audio commands that are received and processed by processor 1610.

[0089] In some embodiments, computing device 1600 comprises display subsystem

1630. Display subsystem 1630 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device 1600. Display subsystem 1630 includes display interface 1632, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface 1632 includes logic separate from processor 1610 to perform at least some processing related to the display. In one embodiment, display subsystem 1630 includes a touch screen (or touch pad) device that provides both output and input to a user.

[0090] In some embodiments, computing device 1600 comprises I/O controller 1640.

I/O controller 1640 represents hardware devices and software components related to interaction with a user. I/O controller 1640 is operable to manage hardware that is part of audio subsystem 1620 and/or display subsystem 1630. Additionally, I/O controller 1640 illustrates a connection point for additional devices that connect to computing device 1600 through which a user might interact with the system. For example, devices that can be attached to the computing device 1600 might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

[0091] As mentioned above, I/O controller 1640 can interact with audio subsystem

1620 and/or display subsystem 1630. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 1600. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem 1630 includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller 1640. There can also be additional buttons or switches on the computing device 1600 to provide I/O functions managed by I/O controller 1640. [0092] In some embodiments, I/O controller 1640 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device 1600. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).

[0093] In some embodiments, computing device 1600 includes power management

1650 that manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem 1660 includes memory devices for storing information in computing device 1600. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem 1660 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 1600.

[0094] Elements of embodiments are also provided as a machine-readable medium

(e.g., memory 1660) for storing the computer-executable instructions (e.g., instructions to implement any other processes discussed herein). The machine-readable medium (e.g., memory 1660) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer- executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).

[0095] In some embodiments, computing device 1600 comprises connectivity 1670.

Connectivity 1670 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device 1600 to communicate with external devices. The computing device 1600 could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.

[0096] Connectivity 1670 can include multiple different types of connectivity. To generalize, the computing device 1600 is illustrated with cellular connectivity 1672 and wireless connectivity 1674. Cellular connectivity 1672 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface) 1674 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.

[0097] In some embodiments, computing device 1600 comprises peripheral connections 1680. Peripheral connections 1680 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device 1600 could both be a peripheral device ("to" 1682) to other computing devices, as well as have peripheral devices ("from" 1684) connected to it. The computing device 1600 commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device 1600. Additionally, a docking connector can allow computing device 1600 to connect to certain peripherals that allow the computing device 1600 to control content output, for example, to audiovisual or other systems.

[0098] In addition to a proprietary docking connector or other proprietary connection hardware, the computing device 1600 can make peripheral connections 1680 via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.

[0099] Reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic "may," "might," or "could" be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to "a" or "an" element, that does not mean there is only one of the elements. If the specification or claims refer to "an additional" element, that does not preclude there being more than one of the additional element.

[00100] Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[00101] While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.

[00102] In addition, well known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown within the presented figures, for simplicity of illustration and discussion, and so as not to obscure the disclosure. Further, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

[00103] An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.