BACKGROUND OF THE DISCLOSURE

1. Field of the Disclosure

[0001] The present disclosure relates to apparatuses and methods for cooling of integrated circuits using thermoelectric devices.

2. Description of the Related Art

[0002] Integrated circuits, often in the form of computer chips, have been around for decades and service as the basis for computer processors, memory, sensors, power management circuits, and controllers. Inside the computer environment, operation of computer chips generates heat and increases the temperature of said computer chips. The heat is typically removed by radiation and convection cooling using fans or pumps to circulate a cooling fluid past the computer chip. The thermal management and cooling are also important in other chips such as power amplifiers used in wireless communications, and in optoelectronic chips used in network communications.

[0003] Temperature of a computer chip impacts performance, as higher temperatures above room temperature tend to reduce performance in certain types of computer chips. As computer chips have grown larger and more complex, certain portions of computer chips may generate more heat than surrounding structures on the same computer chip. In other words, computer chips may have hot spots depending on the operations being performed by the computer chip.

[0004] A shortcoming in prior art computer chip cooling systems is that the entire computer chip or even array of computer chips must be cooled. This means that all computer chips in an array or all portions of a computer chip may not be operated at optimal temperatures because not all of the computer chip is being utilized to the same degree. Uniform cooling may result in unnecessary impacts on performance and cost of cooling systems. Another shortcoming in prior art computer chip cooling is that the cooling is fixed, usually dependent on the proximity to the flow of cooling fluid to the surface of the cooling computer chip. As the computer chip changes operations and different portions generate heat in different patterns, the cooling remains uniform, and is not selective. Similar thermal variations and cross talk considerations happen in wireless chips that have low-noise receiver circuits in close proximity to high-power transmitters, and in optoelectronics chips that have high-power laser sources in close proximity to sensitive photodetectors.

[0005] What is needed is a computer chip or wireless chip or optoelectronic chip cooling system that cools a specific chip in an array or a hot spot on a single chip. What is also needed is a chip cooling system that cools a hot chip in an array or a hot spot on a single chip even when the hot chip/spot change location as the chip operates.

BRIEF SUMMARY OF THE DISCLOSURE

[0006] In aspects, the present disclosure is related to an apparatus and method for cooling of at least a portion of an integrated circuit using a thermoelectric device, and, in particular, spot cooling processors and memories.

[0007] One embodiment according to the present disclosure includes a thermoelectric cooling system that includes: a heat exchanger; a computer processor; and a thermoelectric converter disposed between and in thermal communication with the computer processor and the heat exchanger. The computer processor may have an etched portion defining a hot spot, and the thermoelectric converter may be disposed within a perimeter enclosing the hot spot on the computer processor. The etched portion may be formed by deep reactive ion etching. The system may also include: a signal wire layer in direct contact with the computer processor and opposite the thermoelectric converter; and a support pad layer between the signal wire layer and a fabric interconnect.

[0008] Another embodiment according to the present disclosure includes a thermoelectric cooling system that includes: a heat exchanger; a computer memory; and a thermoelectric converter disposed between and in thermal communication with the computer memory and the heat exchanger. The computer memory may have an etched portion defining a cold spot and the thermoelectric converter is disposed within a perimeter enclosing the cold spot on the computer memory. The etched portion may be formed by deep reactive ion etching. The system may also include: a signal wire layer in direct contact with the computer memory and opposite the thermoelectric converter; and a support pad layer between the signal wire layer and a fabric interconnect. The thermoelectric converter may be a multistage thermoelectric device. The system may also include: a processor in electrical communication with the computer memory and in thermal communication with the heat exchanger; and another thermoelectric converter disposed between and in thermal communication with the processor and the heat exchanger.

[0009] Another embodiment according to the present disclosure includes a method of cooling a microchip that includes the steps of: identifying a portion of a microchip to be cooled; and activating one or more thermoelectric converters in thermal communication with the portion. The microchip may be at least one of: a processor and a computer memory. The thermoelectric converter may be a multistage thermoelectric device. The method may further include the steps of: identifying when cooling is no longer necessary for the portion; and deactivating the one or more thermoelectric converters in thermal communication with the portion.

[0010] Examples of the more important features of the disclosure have been summarized rather broadly in order that the detailed description thereof that follows may be better understood and in order that the contributions they represent to the art may be appreciated. There are, of course, additional features of the disclosure that will be described hereinafter and which will form the subject of the claims appended hereto.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] For a detailed understanding of the present disclosure, reference should be made to the following detailed description of the embodiments, taken in conjunction with the accompanying drawings, in which like elements have been given like numerals, wherein:

FIG. 1A is a side view diagram of a thermoelectric cooling system for computer processors according to one embodiment of the present disclosure;

FIG. IB is a top view diagram of the thermoelectric cooling system of FIG. 1A;

FIG. 1C is a graph of processor performance versus temperature for the thermoelectric cooling system of FIG. 1A with varying performance values of the thermoelectric device;

FIG. 2A is a side view diagram of a thermoelectric cooling system for computer memory storage chips according to one embodiment of the present disclosure;

FIG. 2B is a top view diagram of the thermoelectric cooling system of FIG. 2A;

FIG. 2C is a graph of computer memory retention times versus temperature for the thermoelectric cooling system of FIG. 2A;

FIG. 3A is a top view diagram of computer processor chip suitable for the system of FIG. 1A;

FIG. 3B is a top view diagram of a set of spot cooling thermoelectric converters on the computer processor chip of FIG. 3A;

FIG. 3C is a top view diagram of another set of spot cooling thermoelectric converters on the computer processor chip of FIG. 3A; FIG. 3D is a top view diagram an array of spot cooling thermoelectric converters on the computer processor chip of FIG. 3A;

FIG. 4A is a top view diagram of computer memory chip suitable for the system of FIG. 2A; FIG. 4B is a top view diagram of a set of spot cooling thermoelectric converters on the computer processor chip of FIG. 4A;

FIG. 4C is a top view diagram of another set of spot cooling thermoelectric converters on the computer processor chip of FIG. 4A;

FIG. 4D is a top view diagram an array of spot cooling thermoelectric converters on the computer processor chip of FIG. 4A; and

FIG. 5 is a flow chart for a method of using a spot cooling system of FIGs. 1-4 according to the present disclosure.

DETAILED DESCRIPTION OF THE DISCLOSURE

[0012] Generally, the present disclosure relates to apparatuses and methods for spot cooling of integrated circuits using thin film thermoelectric coolers. The present disclosure is susceptible to embodiments of different forms. They are shown in the drawings, and herein will be described in detail, specific embodiments of the present disclosure with the understanding that the present disclosure is to be considered an exemplification of the principles of the present disclosure and is not intended to limit the present disclosure to that illustrated and described herein.

[0013] This disclosure presents systems for removing heat from all or part of individual microchips for computers, wireless devices, and optoelectronics and other suitable devices by disposing a thermoelectric converter on the microchip and in thermal communication with a heat exchanger. [0014] FIG. 1A shows a thermoelectric cooling system 100 according to one embodiment of the present disclosure. The thermoelectric cooling system 100 includes one or more processors 110, 120, 130 disposed between a fabric interconnect 103 forming a signal and power plane and a heat exchanger 106. Each of the one or more processors 110, 120, 130 is shown disposed on a signal wire layer 112, 122, 132, respectively, and a support pad layer 114, 124, 134, respectively, which may be in electrical communication with the fabric interconnect 103. The signal wire layers 112, 122, 132 provides power and signal communication for the processor 110, 120, 130. The signal wire layers 112, 122, 132 may be any conventional signal layer suitable for printed circuit boards and other electronics, as would be understood by a person of ordinary skill in the art, including those made of copper, aluminum, tungsten, and silicides. The support pad layer 114, 124, 134 may be made up of an array of thermally and electrically conductive pads to support the signal wire layers 112, 122, 132 on the fabric interconnect 103. The one or more processors 110, 120, 130 are shown with different configurations of thermoelectric devices disposed between the processor 110, 120, 130 and the heat exchanger 106.

[0015] The processor 110 is shown with a thermoelectric converter 116 disposed between the heat exchanger 106 and the processor 110. Arrow 114 indicates a flow of heat into the heat exchanger 106 from a hot side 115 of the thermoelectric converter 116. As shown in the top view in FIG. IB, the thermoelectric converter 116 covers all or substantially all of the surface of the processor 110.

[0016] The processor 120 is shown with a thermoelectric converter 126 disposed between the heat exchanger 106 and a portion of the processor 120. A spacer 125 covers the remainder of the processor 120 to provide thermal communication between the processor 120 and the heat exchanger 106. The spacer 125 may be made up of any suitable thermally conducting material as would be understood by a person of ordinary skill in the art, such as copper or silicon carbide SiC. The thermoelectric converter 126 is positioned on a “hot spot” portion 127 of the processor 120 that may require a higher amount of heat removal that other parts of the surface of the processor 120. Hot spots may occur on the processor 120 when a high number of computations are being performed in the portion 127 of the processor 120, such as where the portion includes an arithmetic logic unit (ALU) or a digital signal processor (DSP). The thermoelectric converter 126 may be bounded by a perimeter 128 of deep reactive ion etching that partially penetrates the processor 120. Above the processor 120, the perimeter 128 may coincide with a gap 129 between the thermoelectric converter 126 and the spacer 125. The gap 129 provides thermal insulation between the thermoelectric converter 126 and the spacer 125. Arrow 145 indicates the flow of heat into the heat exchanger 106 through the spacer 125. Arrow 146 indicates the flow of heat into the heat exchanger 106 from the hot spot 127.

[0017] The processor 130 is shown without a thermoelectric converter, but thermal communication is between the processor 130 and the heat exchanger 106 is provided by a spacer 135. The space 135 may be made of the same material suitable for the spacer 125. Arrow 155 indicates the flow of heat into the heat exchanger 106 through the spacer 135. The heat exchanger 106 may include a circulating fluid, such as, but not limited to, air or water. In some embodiments, the heat exchanger 106 may include circulating tubes and/or radiating fins.

[0018] FIG. IB shows a diagram of a top view of the system 100 without the heat exchanger 106. The thermoelectric converter 116 is shown covering all of the processor 110. The hot spot 127 of the processor 120 is covered by the thermoelectric converter 126, while the rest of the processor 120 is covered by the spacer 125. The processor 130 is covered by the spacer 135. The spacers 125, 135 may be made of any suitable thermally conducting material, such as, but not limited to, copper and silicon carbide. All of the processors 110, 120, 130 are shown supported indirectly by the fabric interconnect 103. The fabric interconnect 103 may be any suitable connectivity network. In some embodiments, a printed circuit board or other suitable substitute may be used in place of the fabric interconnect 103.

[0019] The thermoelectric cooling converters 116, 126 may be made of any suitable thin film thermoelectric device as would be understood by a person of ordinary skill in the art. These thermoelectric devices may include single or multiple stage thermoelectric devices. While FIGs 1A-1B show three different configurations for the three processors 110, 120, 130, it is contemplated that any number of these configurations may be applied to any number of processors so long as at least one thermoelectric converter 116, 126 is used with at least of the processors 110, 120

[0020] FIG. 1C is a graph of enhancement in maximum processor power as a function of the hot-side temperature of the thermoelectric converter 116, 126. When the thermoelectric converter 116, 126 is not powered on, the hot-side temperature of the thermoelectric converter 116,126 is close to the processor temperature, and there is no enhancement in the maximum processor power. When the thermoelectric converter is powered, the coefficient of performance (COP) of the thermoelectric converter 116,126 determines the hot side temperature of the thermoelectric converter 116,126. As the operating current increasing beyond an optimal value, the COP reduces due to Joule heating, and the enhancement in maximum processor power declines beyond an optimum hot-side temperature of the thermoelectric converter 116,126. Curve 160 shows the performance of the processor when the thermoelectric cooling device 116, 126 dissipating heat from the processor has a figure of merit (ZT) of 1.0. Curve 161 shows the temperature of the same processor performing at higher temperatures and performance power when the ZT value of the thermoelectric cooling device 116, 126 is 2.0. Improved thermoelectric performance allows the processor to perform at higher power levels. For Curve 160, the enhancement in maximum processor power is shown as about 25% while for Curve 161, the enhancement is shown as about 50%. Higher limits for processor power allow faster computing rates for the processor and the computer.

[0021] FIG. 2A shows a thermoelectric cooling system 200 according to another embodiment of the present disclosure. The thermoelectric cooling system 200 includes one or more processors 210, 220 and one or more computer memories 230 disposed between a fabric interconnect 203 forming a signal and power plane and a heat exchanger 206. The processors 210, 220 may be the same type as the processors 110, 120. The fabric interconnect 203 and the heat exchanger 206 may be the same type as the fabric interconnect 103 and the heat exchanger 106. The fabric interconnect 203 may be the same as the fabric interconnect 103 or even a different portion of the fabric interconnect 103. The heat exchanger 206 may be similar in configuration or even part of the heat exchanger 106. Each of the processors 210, 220 may be disposed on a signal wire layer 212, 222, similar to the signal wire layer 112, 122. Each of the signal wire layers 212, 222 may be disposed on a support pad layer 214, 224, similar to the support pad layer 112, 124, which may be in electrical communication with the fabric interconnect 203. Each of the one or more computer memories 230 may be disposed on a signal wire layer 232, and a support pad layer 234, which may be in electrical communication with the fabric interconnect 203. The one or more thermoelectric cooling converters 236 may be disposed between the memory 230 and the heat exchanger 106.

[0022] The processor 210 is shown with a thermoelectric converter 216 disposed between the heat exchanger 106 and the processor 210. Arrow 214 indicates a flow of heat into the heat exchanger 106 from a hot side 215 of the thermoelectric converter 216. As shown in the top view in FIG. 2B, the thermoelectric converter 216 covers all or substantially all of the surface of the memory 210.

[0023] The processor 220 is shown with a thermoelectric converter 226 disposed between the heat exchanger 106 and a portion of the processor 220. A spacer 225 covers the remainder of the processor 220 to provide thermal communication between the processor 220 and the heat exchanger 106. The thermoelectric converter 226 is positioned on a “hot spot” portion 227 of the processor 220 that may require a higher amount of heat removal that other parts of the surface of the processor 220. In some embodiments, the portion 227 may be a “cold spot” where the performance of the portion 227 benefits from operating at a lower temperature than the rest of the processor 220. The thermoelectric converter 226 may be bounded by a perimeter 228 of deep reactive ion etching that partially penetrates the processor 220. Above the processor 220, the perimeter 228 may coincide with a gap 229 between the thermoelectric converter 226 and the spacer 225. Arrow 245 indicates the flow of heat into the heat exchanger 106 through the spacer 225. Arrow 246 indicates the flow of heat into the heat exchanger 106 from the hot spot 227.

[0024] The memory 230 is shown with a multi-stage thermoelectric converter 236 between the memory 230 and the heat exchanger 106. The thermoelectric converter 230 is configured to lower the temperature of the memory 230 from a typical operating temperature of around 70 degrees Celsius to around -50 degrees Celsius. The significantly lower temperatures enhance the time of retention of the memory 230. Arrow 255 indicates the flow of heat into the heat exchanger 106 from the thermoelectric converter 236.

[0025] FIG. 2B shows a diagram of a top view of the system 200 without the heat exchanger

106. The thermoelectric converter 216 is shown covering all of the processor 210. The hot spot/cold spot 227 of the processor 220 is covered by the thermoelectric converter 226, while the rest of the processor 220 is covered by the spacer 225. The memory 230 is covered by the thermoelectric converter 236. The spacer 225 may be made of any suitable thermally conducting material, such as, but not limited to copper and silicon carbide SiC. All of the processors 210 and 220, and memories 230 are shown supported indirectly by the fabric interconnect 206.

[0026] The thermoelectric cooling converters 216, 226, 236 may be made of any suitable thin film thermoelectric device as would be understood by a person of ordinary skill in the art. These thermoelectric devices may include single or multiple stage thermoelectric devices. While FIGs 2A-2B show three different configurations for the processors 210, 220 and memories 230, it is contemplated that any number of these configurations may be applied to any number of computer systems so long as at least one thermoelectric converter 216, 226, 236 is used with at least of the processors 210, 220, and memories 230. In some embodiments, one or more of the computer processors and memories may not have a thermoelectric converter 216, 226, 236 but have a form of the spacer 235 dimensioned to cover all or substantially all of the processors 210, 220, and memories 230 to ensure thermal communication between the thermoelectric converter 210, 220, 230 and the heat exchanger 106.

[0027] FIG. 2C is a graph of memory retention time and failures at different operating temperatures. Curve 260 shows the retention and failure characteristics of a computer memory chip operating at 360K (87 degrees Celsius). Curve 261 shows the retention and failure characteristics of a computer memory when the operating temperature has been reduced to 340K (67 degrees Celsius). This is a typical operating temperature for a computer memory chip. Curve 262 shows the retention and failure characteristics of a computer memory when the operating temperature has been reduced to room temperature, or around 297K (24 degrees Celsius). Curve 263 shows the retention and failure characteristics of a computer memory when its operating temperature has been reduced to 77K (-196 degrees Celsius). From the above curves, it is clear that operating the computer memory chips at lower temperatures results in a lower failure rate and a longer retention time. The longer retention times lower the power dissipation of the computer system because the data does not need to be read and re-written into the memories to keep data valid.

[0028] FIG. 3A shows a diagram of an exemplary computer processor chip 300. While the embodiment is described in terms of a computer chip, this is illustrative and exemplary only, as the invention may be used on any suitable microchip, including those for wireless devices and optoelectronics. During operation, the computer chip 300 exhibits higher temperatures in particular hot spots 327 where the computer chip 300 processing power is limited in order to not exceed the cooling capacity of its heat exchanger or damage to the computer chip 300.

[0029] FIG. 3B shows a diagram of an apparatus 301, which includes the computer processor chip 300 and one or more thermoelectric cooling converters 326 disposed over the hot spots 327. The portions of the computer processor chip 300 that are not hot spots 327 are covered by a spacer 325, which may be made up of one or more segments. The computer processor chip 300 has an etched perimeter 328 around the thermoelectric cooling converters 326 that penetrate partially into the chip 300, just like the perimeter 128 and below a gap 329 (similar to the gap 129) between the thermoelectric cooling converter 326 and the spacer 325. The perimeters 328 may be positioned to each enclose at least one hot spot 327 and the thermoelectric cooling converter 326 corresponding to it.

[0030] FIG. 3C shows a diagram of an apparatus 302, which includes the elements of FIG. 3B and adds a multi-stage thermoelectric cooling converter 336 to provide cooling to a greater degree than the thermoelectric cooling converter 326. The multi-stage thermoelectric cooling converter 336 may be used in event of an additional hot spot that requires more cooling than the thermoelectric cooling converter 326 at maximum cooling.

[0031] FIG 3D shows another embodiment of the apparatus 303 that includes the computer processor chip 300 covered by an array 350 of thermoelectric cooling converters 326 separated by gaps 329 and accompanied by perimeters 328. Instead of a single thermoelectric converter over the entire computer processor chip 300, the array 350 enables individual thermoelectric cooling converters 326 to be turned on or off to provide additional cooling for hot spots that may manifest in different areas of the computer processor chip 300 during various operations. In some embodiments, the individual thermoelectric cooling converters 326 of the array 350 may be activated/deactivated by a controller in response to sensors (not shown) that detect temperature changes in portions of the computer processor chip 300. In some embodiments, the existing temperature sensors and controllers on the computer processor chip 300 may provide activation/deactivation signals to the thermoelectric cooling converters 326. In some embodiments, the individual thermoelectric cooling converters 326 of the array 350 may be activated/deactivated in response to or based on the computer processor chip 300 operations, since operations will drive which components of the chip 300 will be drawing defined amounts of power. In some embodiments, the individual thermoelectric cooling converters 326 may be activated/deactivated in response to the individual voltage across individual thermoelectric converter 326.

[0032] FIG. 4A shows a diagram of an exemplary computer memory chip 400. During operation, the computer memory chip 400 includes portions 427 where data is stored and retained for a length of time that is dependent on the temperature of the portion 427. [0033] FIG. 4B shows a diagram of an apparatus 401, which includes the computer memory chip 400 and one or more thermoelectric cooling converters 426 disposed over the portions 427. The portions of the computer memory chip 400 that are portions 427 are covered by a spacer 425, which may be made up of one or more segments. The computer memory chip 400 has an etched perimeter 428 around the thermoelectric cooling converters 426 that penetrate partially into the chip 400, just like the perimeter 228 and below a gap 429 (similar to the gap 229) between the thermoelectric cooling converter 426 and the spacer 425. The perimeters 428 may be positioned to each enclose at least one portion 427 and the thermoelectric cooling converter 426 corresponding to it.

[0034] FIG. 4C shows a diagram of an apparatus 402, which includes the elements of FIG. 4B and adds a multi-stage thermoelectric cooling converter 436 to provide cooling to a greater degree than the thermoelectric cooling converter 426. The multi-stage thermoelectric cooling converter 436 may be used in event of an additional hot spot that requires more cooling than the thermoelectric cooling converter 426 at maximum cooling.

[0035] FIG 4D shows another embodiment of the apparatus 403 that includes the computer memory chip 400 covered by an array 450 of thermoelectric cooling converters 426 separated by gaps 429 and accompanied by perimeters 428. Instead of a single thermoelectric converter over the entire computer memory chip 400, the array 450 enables individual thermoelectric cooling converters 426 to be turned on or off to provide additional cooling for selected data storage portions 427 that may manifest in different areas of the computer memory chip 400 during various operations. In some embodiments, the individual thermoelectric cooling converters 426 of the array 450 may be activated/deactivated by a controller in response to sensors (not shown) that detect temperature changes in portions of the computer memory chip 400. In some embodiments, the existing temperature sensors and controllers on the computer processor chip 400 may provide activation/deactivation signals to the thermoelectric cooling converters 426. In some embodiments, the individual thermoelectric cooling converters 426 of the array 450 may be activated/deactivated in response to or based on the computer memory chip 400 operations, since operations will drive which components of the chip 400 will be drawing defined amounts of power. In some embodiments, the individual thermoelectric cooling converters 426 may be activated/deactivated in response to the individual voltage across individual thermoelectric converter 426.

[0036] FIG. 5 shows a flow chart of a method 500 that may be applied for the thermoelectric cooling system 100 or the thermoelectric cooling system 200. In step 510, the one or more hot spots 327 (on processor 300) or one or more portions 427 (on memory 400) may be identified that have a thermoelectric converter 326, 426 disposed on them (as in FIGs 3B, 3C, 3D, 4B, 4C, and 4D) In some embodiments, the hot spots 327 may be identified by detecting temperature changes in the processor 300. In some embodiments, the hot spots 327 or the portions 427 may be identified based on information entering or from the respective chip 300, 400 that indicates sections of the chip 300, 400 that are receiving more power or storing data. In step 520, one or more of the thermoelectric cooling converters 326, 426 may be activated to cool the respective hot spot 327 or portion 427. In step 530, identifying one or more of the active thermoelectric cooling converters 326, 426 on a hot spot 327 or portion 427 that no longer requires cooling, such as when that particular area of the chip 300, 400 is no longer operating or operations have been reduced. In step 540, deactivating one or more of the active thermoelectric cooling converters 326, 426 that have been identified as associate with an area of the chip 300, 400 that no longer requires cooling. [0037] While the disclosure has been described with reference to exemplary embodiments, it will be understood that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the disclosure. In addition, many modifications will be appreciated to adapt a particular instrument, situation or material to the teachings of the disclosure without departing from the essential scope thereof. Therefore, it is intended that the disclosure not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this disclosure, but that the disclosure will include all embodiments falling within the scope of the appended claims.