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Title:
SR FLIP FLOP
Document Type and Number:
WIPO Patent Application WO/1999/003204
Kind Code:
A1
Abstract:
An SR flip flop which utilizes the reversible breakdown state of a semiconductor junction and controls the bistable states of two output electrodes by directly impressing trigger pulses upon the electrodes. The flip flop can simplify circuits and increase the operating speed of the circuits.

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Inventors:
MASUDA TATSUJI (JP)
Application Number:
PCT/JP1998/002959
Publication Date:
January 21, 1999
Filing Date:
July 01, 1998
Export Citation:
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Assignee:
MASUDA TATSUJI (JP)
International Classes:
H03K3/313; H01L21/82; H01L27/04; H01L29/86; H03K3/037; (IPC1-7): H03K3/313; H01L21/82; H01L27/04; H01L29/86
Foreign References:
JPS61142777A1986-06-30
JPS59211284A1984-11-30
JPS6049678A1985-03-18
JPS59211283A1984-11-30
JPH0879022A1996-03-22
Other References:
See also references of EP 0935343A4
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