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Title:
STACKED GATE-ALL-AROUND NANO-SHEET CMOS DEVICE STRUCTURE AND MANUFACTURING METHOD THEREFOR
Document Type and Number:
WIPO Patent Application WO/2020/248474
Kind Code:
A1
Abstract:
The present invention provides a manufacturing method for a stacked gate-all-around nano-sheet CMOS device structure, comprising: providing a substrate having a supporting layer at one side thereof, and alternately stacking sacrificial layers and channel layers on the supporting portion along the extension direction of the supporting portion, wherein the supporting portion, the sacrificial layers, and the channel layers constitute fin structures, an NMOS uses the channel layer of a first material, a PMOS uses the channel layer of a second material, the respective channel layer is the sacrificial layer of the other, and the hole mobility of the second material is greater than that of the first material; forming a dummy gate stack layer across the fin structure, and forming a source/drain region in the fin structures located at the two sides of the dummy gate stack layer; by means of a selective etching process, sequentially removing the dummy gate stack layer of the NMOS/the PMOS and the sacrificial layer covered by the dummy gate stack layer, so that the surfaces of the channel layers located between the source region and the drain region are partially exposed, and the channel layers having the exposed surfaces constitute a nano-sheet array; and forming a gate stack layer structure around the periphery of each nano-sheet in the nano-sheet array.

Inventors:
YIN HUAXIANG (CN)
YE TIANCHUN (CN)
ZHANG QINGZHU (CN)
YAO JIAXIN (CN)
Application Number:
PCT/CN2019/114174
Publication Date:
December 17, 2020
Filing Date:
October 30, 2019
Export Citation:
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Assignee:
INST OF MICROELECTRONICS CAS (CN)
International Classes:
H01L21/8238; H01L27/092
Foreign References:
CN110246806A2019-09-17
CN108172546A2018-06-15
CN108364910A2018-08-03
CN109411352A2019-03-01
CN108878277A2018-11-23
Attorney, Agent or Firm:
UNITALEN ATTORNEYS AT LAW (CN)
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