Title:
STORAGE DEVICE AND PROGRAMMING METHOD
Document Type and Number:
WIPO Patent Application WO/2020/158531
Kind Code:
A1
Abstract:
In order to provide a storage device with which, even if an operating voltage of a cell transistor is lowered, no malfunction occurs in a peripheral circuit, the storage device is equipped with: a resistance change element, the resistance state of which changes according to a voltage applied between electrodes thereof; a cell transistor constituted by a first transistor and including a diffusion layer that is connected to one electrode of the resistance change element; and a select transistor constituted by a second transistor and including a diffusion layer that is connected to the other electrode of the resistance change element, wherein the diffusion layers of the first transistor and the second transistor are separated from each other and different substrate voltages are applied to the first transistor and the second transistor.
Inventors:
TADA MUNEHIRO (JP)
NEBASHI RYUSUKE (JP)
SAKAMOTO TOSHITSUGU (JP)
NEBASHI RYUSUKE (JP)
SAKAMOTO TOSHITSUGU (JP)
Application Number:
PCT/JP2020/002069
Publication Date:
August 06, 2020
Filing Date:
January 22, 2020
Export Citation:
Assignee:
NEC CORP (JP)
International Classes:
G11C13/00; G11C5/14; H01L21/8234; H01L21/8239; H01L27/088; H01L27/105
Domestic Patent References:
| WO2010047068A1 | 2010-04-29 | |||
| WO2016009472A1 | 2016-01-21 | |||
| WO2014002656A1 | 2014-01-03 |
Foreign References:
| JP2016167329A | 2016-09-15 | |||
| JP2010251491A | 2010-11-04 |
Attorney, Agent or Firm:
SHIMOSAKA Naoki (JP)
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