Title:
STORAGE DEVICE
Document Type and Number:
WIPO Patent Application WO/2024/057519
Kind Code:
A1
Abstract:
In the present invention, a first string includes a first memory cell transistor, one end of the first string being connected to a first wire, the other end being connected to a second wire. A second string includes a second memory cell transistor, one end of the second string being connected to the first wire, the other end being connected to the second wire. A first power supply line is connected to the gate of the first memory cell transistor via a first transistor and is connected to the gate of the second memory cell transistor via a second transistor. A third string includes a third memory cell transistor, one end of the third string being connected to the first wire, the other end being connected to the second wire. A second power supply line is connected to the gate of the third memory cell transistor and applies a voltage different from that of the first power supply line during data erase.
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Inventors:
UCHIYAMA YASUHIRO (JP)
Application Number:
PCT/JP2022/034724
Publication Date:
March 21, 2024
Filing Date:
September 16, 2022
Export Citation:
Assignee:
KIOXIA CORP (JP)
International Classes:
G11C16/04; G11C16/08
Foreign References:
| JP2021093230A | 2021-06-17 | |||
| JP2020144962A | 2020-09-10 | |||
| JP2022113967A | 2022-08-05 | |||
| JP2022042297A | 2022-03-14 |
Attorney, Agent or Firm:
SUZUYE & SUZUYE (JP)
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