CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit under 35 U.S.C. § 119(e) of U.S. Application Serial No. 63/303,013, filed January 25, 2022, under Attorney Docket No. G0766.70349US00 and entitled “HETEROGENEOUS INTEGRATION OF MEMS SENSORS AND MULTIPLE CIRCUIT CHIPS,” which is hereby incorporated herein by reference in its entirety.

FIELD OF THE DISCLOSURE

[0002] The present application relates to stress isolation for heterogenous integrated circuit (IC) package integration, including wafer level chip scale packaging (WLCSP).

BACKGROUND

[0003] Wafer level chip scale packaging is used to package integrated circuits (ICs), microelectromechanical systems (MEMS), or both.

SUMMARY OF THE DISCLOSURE

[0004] Heterogeneous integrated circuit (IC) packaging structures and techniques are provided exhibiting stress isolation. In some embodiments, wafer level chip scale packages with stress isolation are provided, in addition to signal routing features such as through- silicon vias (TSV), redistribution layers (RDL) and solder bump features. The packaging structure includes an interposer having stress isolation features. The stress isolation features are stress isolation platforms in some instances. The stress isolation platforms are configured to isolate stress from a substrate with which the interposer is coupled, preventing the stress from propagating from the substrate to a packaged die. The packaged die may be an integrated circuit (IC) die, a microelectromechanical systems (MEMS) die, a sensor die (e.g., an optical die, a magnetic sensor die, a biosensor die, a microfluidics die) or a combination, among other possible device types. In some embodiments, multiple dies are packaged.

[0005] Packaging structures other than wafer WLCSP are also disclosed, such as general 2D and 3D heterogeneous IC package integrations such as multi-die flip-chip, fan-in and fan-out

SUBSTITUTE SHEET ( RULE 26 ) package, wafer level package, silicon, silicon carbide, silicon germanium, gallium arsenide, gallium nitride, glass, ceramic, laminate, or other type of IC dies and IC packages.

[0006] Packaging of microfabricated devices is described, such as IC, MEMS and sensor devices. The packaging is wafer level chip scale packaging in at least some embodiments. The wafer level chip scale packaging includes an interposer. The interposer includes stress relief features. Thus, stresses originating in the packaging do not propagate to the packaged device. [0007] Some embodiments relate to a 3D heterogeneous packaged device, comprising: a device die; and an interposer coupled with the device die at a plurality of bond points, the interposer comprising a plurality of stress isolation platforms at different locations from the plurality of bond points.

[0008] In some embodiments, a first stress isolation platform of the plurality of stress isolation platforms is coupled to a remainder of the interposer by a plurality of stress isolation suspensions.

[0009] In some embodiments, the plurality of bond points are a first plurality of bond points, and wherein the 3D heterogeneous packaged device further comprises a substrate coupled with the interposer at a second plurality of bond points aligned with the plurality of stress isolation platforms, wherein the interposer is disposed between the device die and the substrate.

[0010] In some embodiments, the device die is an integrated circuit die and the substrate is a printed circuit board, silicon substrate, silicon carbide substrate, silicon germanium substrate, gallium arsenide substrate, gallium nitride substrate, glass substrate, ceramic substrate, or laminate substrate.

[0011] In some embodiments, the device die is an integrated circuit (IC) die, a microelectromechanical systems (MEMS) die, a sensor die, an optical die, a magnetic sensor die, a biosensor die, a microfluidics die), or a combination thereof.

[0012] In some embodiments, the device die is a first device die, and wherein the 3D heterogeneous packaged device further comprises a second device die coupled with the first device die in a vertical stack, with the interposer representing a bottom layer of the vertical stack, the first device die positioned above the interposer as a second layer of the vertical stack, and the second device die positioned above the first device die as a third layer of the vertical stack.

[0013] In some embodiments, the interposer comprises an outer portion and an inner portion, and wherein the stress isolation platforms are formed only at the outer portion of the interposer. [0014] Some embodiments relate to a 3D heterogeneous packaged device, comprising: a substrate; an interposer, bonded to the substrate, comprising: a plurality of stress isolation platforms, at least one of the plurality of stress isolation platforms defining a portion of the interposer that is flexibly coupled to a remainder of the interposer by a plurality of stress isolation suspensions; and a bond pad formed in the at least one of the plurality of stress isolation platforms; a bond, in contact with the bond pad, coupling the interposer to the substrate; and a device die coupled to the interposer, wherein the interposer is disposed between the device die and the substrate.

[0015] In some embodiments, at least eight stress isolation suspensions flexibly couple the at least one of the plurality of stress isolation platforms to the remainder of the interposer.

[0016] In some embodiments, at least one of the plurality of stress isolation suspensions is formed between a pair of trenches that extend across an entire thickness of the interposer. [0017] In some embodiments, the interposer comprises an outer portion and an inner portion, and wherein the stress isolation platforms are formed only at the outer portion of the interposer. [0018] In some embodiments, the device die comprises a MEMS device and the interposer defines a cavity aligned with the MEMS device.

[0019] In some embodiments, the interposer further comprises a thru silicon via (TSV) electrically coupling the bond pad to the device die.

[0020] In some embodiments, the device die is a first device die, and wherein the 3D heterogeneous packaged device further comprises a second device die bonded to the first device die so that the first device die is between the interposer and the second device die.

[0021] In some embodiments, the substrate comprises a laminate substrate bonded to a printed circuit board.

[0022] Some embodiments relate to a method for fabricating a 3D heterogeneous packaged device, comprising: bonding an interposer to a device die; patterning the interposer with a plurality of bond pads; forming a plurality of stress isolation platforms by etching a plurality of trenches through the interposer so that at least one of the plurality of stress isolation platforms includes a bond pad of the plurality of bond pads; and with the interposer bonded to the device die, bonding the interposer to a substrate so that the interposer is between the device die and the substrate.

[0023] In some embodiments, the method further comprises filling the plurality of trenches with gel. [0024] In some embodiments, the method further comprises forming a plurality of thru silicon vias (TSVs) through the interposer, wherein bonding the interposer to the device die comprises electrically coupling the device die to the TSVs.

[0025] In some embodiments, the device die comprises a MEMS device, wherein the method further comprises etching a cavity through the interposer, wherein bonding the interposer to the device die comprises aligning the MEMS device to the cavity.

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are not intended to be drawn to scale. In the drawings, each identical or nearly identical component that is illustrated in various figures may be represented by a reference numeral or character. For purposes of clarity, not every component may be labeled in every drawing. In the drawings:

[0027] FIG. 1A illustrates a cross-sectional view of a 3D heterogenous packaged integrated circuit (IC) having an interposer with stress isolation and signal routing, according to a nonlimiting embodiment of the present application.

[0028] FIG. IB illustrates a top view of one of the stress isolation platforms formed in the interposer of the 3D heterogeneous packaged IC of FIG. 1 A, according to a non-limiting embodiment of the present application.

[0029] FIG. IC illustrates a top view of an interposer having an outer portion and an inner portion, where the outer portion includes a plurality of stress isolation platforms, in accordance to a non-limiting embodiment of the present application.

[0030] FIG. ID illustrates another top view of the interposer of FIG. IC showing additional details, in accordance to a non-limiting embodiment of the present application.

[0031] FIG. 2 illustrates a cross-sectional view of a 3D heterogenous packaged device comprising two integrated circuits (ICs) and an interposer with stress isolation and signal routing, according to a non-limiting embodiment of the present application.

[0032] FIG. 3 illustrates a cross-sectional view of a 3D heterogenous packaged IC having an interposer with stress isolation and signal routing, and bonded with a printed circuit board (PCB), according to a non-limiting embodiment of the present application. [0033] FIG. 4 illustrates a cross-sectional view of an overmolded 3D heterogeneous packaged IC having an interposer with stress relief and signal routing, according to a non-limiting embodiment of the present application.

[0034] FIG. 5 illustrates a cross-sectional view of an overmolded version of the apparatus of FIG. 3 also exhibiting 2D integration of multiple packaged devices, according to a non-limiting embodiment of the present application.

[0035] FIG. 6 illustrates a cross-sectional view of an overmolded 3D heterogenous packaged device comprising two ICs and an interposer with stress isolation and signal routing, according to a non-limiting embodiment of the present application.

[0036] FIG. 7A illustrates a cross-sectional view of a 3D heterogeneous packaged integrated circuit (IC) and MEMS device having an interposer with stress isolation and signal routing, according to a non-limiting embodiment of the present application.

[0037] FIG. 7B illustrates a top view of the interposer of the 3D heterogeneous packaged IC and MEMS device of FIG. 7A, according to a non-limiting embodiment of the present application.

[0038] FIG. 8 illustrates a flowchart representing a method for fabricating a 3D heterogenous packaged, according to a non-limiting embodiment of the present application.

DETAILED DESCRIPTION

I. Overview

[0039] Stress-isolation structures are described for 2D and 3D heterogeneous packaged device integration. Examples of such heterogeneous packaging include wafer level chip scale packaging (WLCSP), multi-die flip-chip, fan-in and fan-out packaging, wafer level package packaging, silicon, silicon carbide, silicon germanium, gallium arsenide, gallium nitride, glass, ceramic, laminate, or other type of IC dies and IC packages. Such packaging is sometimes used to package integrated circuits (ICs), microelectromechanical systems (MEMS) devices, or other devices. Some such devices include stress isolation structures at the die level, for instance built into the IC die or MEMS die. Such dies may be relatively large, and electrical connections to the die may be made via wire bonding. Smaller dies may be utilized in 3D heterogeneous packaged devices that employ bump bonding, solder balls, or other similar bonding structures. Electrical connection may be made to the packaged IC or MEMS device via such bonding connections, without the need for wire bonding. However, because bump bonds, solder bumps, and other similar bonding structures may be substantially rigid, stresses originating from the packaging may propagate into the packaged IC or MEMS device. The inventors have appreciated that including stress isolation features in an interposer of the 2D or 3D heterogenous packaged device may reduce or eliminate the propagation of stresses from the packaging to the IC or MEMS device. Thus, the packaged IC or MEMS device may effectively be isolated from external stresses. As a result, sensitive electronics and/or mechanical components of the packaged IC and/or MEMS device may be protected, and the negative effects of undesired stresses on the device operation may be mitigated.

[0040] Although ICs and MEMS devices are described above, it should be appreciated that aspects of the present application apply as well to other types of microfabricated devices, such as optical dies, sensor dies, and other microfabricated devices.

II. Examples of Interposers with Stress Isolation Platforms

[0041] According to an aspect of the present application, a 3D heterogeneous packaged device includes a packaged IC and an interposer with stress isolation, as well as signal routing features. FIG. 1A illustrates a non-limiting example, and shows a cross-sectional view of a 3D heterogeneous packaged integrated circuit (IC) having an interposer with stress isolation. The illustrated 3D heterogeneous packaged device includes an IC (die) 100, an interposer 110, and a substrate 120. It should be appreciated that the illustrated interposer may be a portion of a larger interposer, focused on a few stress isolation platforms. In practice, the interposer may, and in some embodiments is, larger and will include multiple such stress-isolated platforms.

[0042] Substrate 120 may be any suitable type of substrate, including silicon, silicon carbide, silicon germanium, gallium arsenide, gallium nitride, glass, ceramic, a laminate substrate, a PCB, or a flexible substate, among others.

[0043] IC 100 may be any suitable type of IC. In at least some embodiments, IC 100 may include sensitive electronics, such as circuitry 102, the operation of which may be negatively impacted by stress. In this respect, the IC may be a stress- sensitive IC. Non-limiting examples of circuitry 102 include digital circuits, analog circuits, sensors, MEMS devices, optical devices, among others.

[0044] IC 100 is bonded to interposer 110 via bonds 104. Bonds 104 may be micro bump bonds, metal-metal bonding (e.g., eutectic bonding) or any other suitable type of bonding. Multiple bond points may be provided between IC 100 and the interposer 110. [0045] Interposer 110 includes stress isolation platforms 112. Stress isolation platforms 112 isolate the packaged IC from substrate 120, such that stresses experienced by substrate 120 (whether originated in the substrate itself or in other parts of the package) do not propagate to IC 100 and negatively impact its operation. Stress isolation platforms 112 serve as coupling points for coupling interposer 110 to substrate 120. Bonding is achieved via bonds 115, which may include solder balls, solder pads, or by flip chip bonds. Pads 114 are formed on the surface of interposer 110 and provide electrical connection to bonds 115. Any suitable number of stress isolation platforms 112 may be provided in the interposer 110. The number of stress isolation platforms may be approximately the same as, or may match, the number of bond points between the interposer and the substrate. However, not all embodiments are limited in this respect.

[0046] In some embodiments, interposer 110 may further support signal routing between IC 100 and substrate 120. In the example of FIG. 1A, thru silicon vias (TSVs) 118 are formed through interposer 110 and support signal routing from circuitry 102 to substrate 120, and vice versa. A redistribution layer (RDL) 116 couples TSVs 118 to bonds 115. In some embodiments, interposer 110 may be a passive substrate in that it lacks active (e.g., energy consuming) electronic devices or circuits. For example, interposer 110 may lack transistors.

[0047] In some embodiments, the package illustrated in FIG. 1A (and any one of the packages illustrated on the following figures) may be fabricated in accordance with wafer level chip scale packaging (WLCSP) techniques. Accordingly, IC 100 may be bonded to interposer 110 before the wafer on which ASIC 100 is formed is diced. In other words, IC 100 may be bonded to interposer 110 when it is still part of the wafer. Dicing can occur after IC 100 and interposer 110 are bonded to one another. With WLCSP, the resulting package is practically of the same lateral extension as ASIC 100, thereby avoiding unnecessary waste of space.

[0048] FIG. IB illustrates a top view of a stress isolation platform 112 of the 3D heterogeneous packaged device of FIG. 1 A. Stress isolation platform 112 may be a dual-purpose platform providing both mechanical stress isolation and electrical connectivity between substrate 120 and IC 100. As shown, stress isolation platform 112 may include a plurality of stress isolation suspensions 119 defined at least in part by a plurality of stress isolation trenches 113 that are etched through the interposer. The stress isolation suspensions 119 flexibly couple the stress isolation platforms 112 to the remaining part of the interposer 110. Thus, the stress isolation platforms 112 and the remaining part of the interposer 110 are free to move relative to each other, being mechanically independent of each other. Trenches 113 may be formed in any suitable number and shape. The stress isolation platform of FIG. IB includes eight trenches, four of which are L-shaped. A first segment of an L-shaped trench runs parallel to a first side of pad 114 and a second segment of the L-shaped trench runs parallel to a second side of pad 114 that is perpendicular to the first side. Each of the remaining four trenches runs parallel to a respective side of pad 114. Each suspension 119 is formed between a pair of trenches 113, as shown in FIG. IB.

[0049] To permit free movement of a stress isolation platform 112 relative to the remainder of the interposer, trenches 113 may extend across the entire thickness of interposer 110 (along the z-axis), from the top surface to the bottom surface, as shown in FIG. 1A. A trench may be formed from a single vertical segment extending across the entire thickness of the interposer, or alternatively, may be formed of multiple offset vertical segments coupled together by horizontal or angled segments, in a zig-zag configuration. In some embodiments, trenches 113 may be filled with a gel or other low stress materials to improve mechanical strength while still permitting free movement of the stress isolation platforms.

[0050] The stress isolation platforms 112 also provide electrical interconnectivity between substrate 120 and IC 110. As shown in FIG. IB, a metal pad 114 may be provided on a stress isolation platform 112, and one or more metal traces 117 may be routed from the stress isolation platform 112 over to electrical connection points on the device, whether an IC, MEMS device, sensor die, or other type of device. For example, the metal traces 117 are deposited on top of the suspensions 19 over to the electrical connection points in some embodiments, as shown. Thus, interposer 110 provides both stress isolation and signal routing functionality. In some embodiments, a stress isolation platform 112 may include more than one pad 114, thereby providing multiple points of contact with substrate 120 within the stress isolation platform. [0051] It should be appreciated that the example stress suspensions illustrated in FIG. IB are non-limiting. In that example, eight stress isolation suspensions 119 are provided, positioned symmetrically about the stress isolated platform 112. That is, two stress isolation suspensions 119 are positioned on each side of the stress isolation platform 112. However, other configurations are possible. For example, a stress isolation platform may include more than eight stress isolation suspensions.

[0052] In some cases, the stress isolation platforms can be formed only at an outer part of the die (without stress isolation platforms at the inner part of the die). Such a configuration, illustrated in FIG. IC, may be particularly beneficial with larger dies. In the example of FIG. IC, the inner part 152 of interposer 110 may include rigid (and optionally fine pitch) connections to substrate 120. Multiple stress isolation platforms 112 are formed on the outer part 150 of the interposer. This approach relieves the stress of the outer connection points and provides improved solder joint reliability at those points. In such a configuration, stress may not be relieved for the entire interposer. The stress isolation platforms 112 may completely surround the stress isolation platform-free part of the interposer, as shown in FIG. 1C, although not all embodiments are limited to this configuration.

[0053] FIG. ID illustrates another top view of the interposer of FIG. 1C showing additional details, in accordance to a non-limiting embodiment of the present application. As in the example of FIG. 1C, stress isolation platforms 112 are shown as being formed only at an outer part of the die (without stress isolation platforms at the inner part of the die). FIG. ID further illustrates that each stress isolation platform 112 encompasses a pad 114 (although some stress isolation platforms may encompass more than one pad). The inner part of interposer 110 includes additional pads 114, also configured for connection with the underlying substrate. Those inner pads are not associated with stress isolation platforms. In some embodiments, the pitch of the outer pads (Pl) is greater than the pitch of the inner pads (P2). FIG. ID further illustrates traces formed as part of RDL 116, and TSVs 118 that connect to various points of RDL 116.

[0054] In some embodiments, multiple ICs may be packaged as part of the 3D heterogeneous package. FIG. 2 illustrates a non-limiting example, showing a cross-sectional view of a 3D heterogeneous packaged device comprising two integrated circuits (ICs) and an interposer 110 with stress isolation. The 3D heterogeneous device differs from that of FIG. 1A in that a second IC 200 is added above the first IC 100. ASIC 200 includes circuitry 202. The first IC 100 is disposed between the interposer 110 and the second IC 200. Thru-silicon vias 203 provide electrical connection between the two ICs. Bonds 204 provide mechanical connection between the two ICs.

[0055] According to an aspect of the present application, multiple packaged devices may be bonded to a common laminate substrate, and the laminate substrate may be bonded to a printed circuit board. FIG. 3 illustrates a non-limiting example, showing a cross-sectional view of a 3D heterogeneous packaged IC having an interposer with stress isolation, and bonded with a printed circuit board (PCB) 310. As shown, interposer 110 is bonded to laminate 300, which in turn is bonded to PCB 310 with solder ball bonding, although alternatives are possible. In addition, as shown, additional (e.g., a second) packaged devices (e.g., an IC 320) may be arranged in a 2D manner with the explicitly illustrated device on laminate substrate 300. The packaged devices may be disposed laterally to the side of the first IC 100, thus providing a laterally packaged, stress-isolated multi-chip package. In some embodiments, the additional microfabricated devices (e.g., a second IC 320) may not be packaged, and stress isolation may not be provided for it.

[0056] FIG. 4 illustrates a cross-sectional view of an overmolded 3D heterogeneous packaged IC having an interposer with stress isolation, according to a non-limiting embodiment of the present application. The overmolding 400 encapsulates the IC 100 and interposer 110. A bond ring 410 is provided on the interposer 110 to prevent the molding compound from contaminating the sensitive parts of the device.

[0057] FIG. 5 illustrates a cross-sectional view of an overmolded version of the apparatus of FIG. 3, according to a non-limiting embodiment of the present application, with the addition of additional laterally positioned packaged devices 320. That is, as shown, other IC chips or microfabricated devices may be positioned laterally with respect to the explicitly-illustrated IC, with all such devices being overmolded.

[0058] FIG. 6 illustrates a cross-sectional view of an overmolded 3D heterogeneous packaged device comprising two ICs and an interposer with stress isolation, together with additional packaged microfabricated devices (e.g., ICs 320) laterally positioned on the same laminate substrate 300, according to a non-limiting embodiment of the present application. Thus, it should be appreciated from this non-limiting example that both 2D and 3D stress-isolated packaging may be provided for multiple devices with a laminate or other suitable substrate.

III. Stress Isolation in MEMS Devices

[0059] According to an aspect of the present application, the stress isolation techniques described herein may be used in connection with microelectromechanical systems (MEMS) devices. For example, stress isolation may be built into an interposer with a cavity, where the interposer acts as a cap for a MEMS device. FIG. 7A illustrates an example, showing a cross- sectional view of a 3D heterogeneous packaged device having an ASIC 700, a MEMS die 705, an interposer 710 with stress isolation and signal routing, and a substrate 720. The device of FIG. 7A may further include an optional additional ASIC 730. MEMS die 705 includes a MEMS device 706. MEMS device 706 may include a MEMS accelerometer, a MEMS gyroscope, a MEMS resonator, a MEMS switch, a MEMS optical device, or any other device having a movable mass. A cavity 707 is formed through interposer 710 in correspondence with MEMS device 706. Cavity 707 provides sufficient space to allow for motion of MEMS device 706 towards interposer 710. In this respect, interposer 710 may be viewed as a cap substrate for the MEMS device. ASIC 702 includes circuitry 702, configured to electrically interface with MEMS device 706. Circuitry 702 may include, for example, circuitry for driving motion of MEMS device 706 (in the case of active MEMS devices, such as resonators and gyroscopes) and/or circuitry for sensing motion of the MEMS device, among other types of circuitry.

[0060] In the device of FIG. 7A, interposer 710 and MEMS die 705 are disposed between ASIC 700 and ASIC 730. Accordingly, ASIC 700, MEMS die 705, interposer 710 and ASIC 730 form a vertical stack. Interposer 710 further includes TSVs placing ASIC 700 in communication with ASIC 730. In some embodiments, ASIC 730 may include circuitry (not shown in FIG. 7A) for digital processing information obtained using circuitry 702. In FIG. 7A, the inner TSVs and the metal bond serve as hermetic seal for the MEMS device positioned inside cavity 707.

[0061] Interposer 710 further includes stress isolation platforms 712, which, similar to the stress isolation platforms described in connection with FIGs. 1A-1B, mechanically isolate MEMS die 705 from stress propagating from substrate 720. FIG. 7B illustrates a top view of a stress isolation platform 712 of the 3D heterogeneous packaged device of FIG. 7A. Stress isolation platform 712 may be a dual-purpose platform providing both mechanical stress isolation and electrical connectivity between substrate 720 and ASIC 700. Similar to the stress isolation platform 112, stress isolation platform 712 may include a plurality of stress isolation suspensions 719 defined at least in part by a plurality of stress isolation trenches 713 (also shown in FIG. 7A) that are etched through the interposer. The remaining stress isolation suspensions 719 flexibly couple the stress isolation platforms 712 to the remaining part of the interposer 710. Thus, the stress isolation platforms 712 and the remaining part of the interposer 710 are free to move relative to each other, being mechanically independent of each other. The stress isolation platforms 712 also provide electrical interconnectivity between substrate 720 and ASIC 700. A metal pad 714 may be provided on a stress isolation platform 712, and one or more metal traces 717 may be routed from the stress isolation platform 712 over to electrical connection points on the device.

[0062] It should be noted that stress isolation may be applied to MEMS devices in arrangements different from what is shown in FIG. 7A. In some embodiments, for example, either ASIC 700 or ASIC 730 (or both) may be omitted. In some embodiments, the package may include one or more ASICs in communication with MEMS die 705, but the ASIC(s) may be arranged in a 2D manner (as opposed to a 3D manner), similar to the arrangement shown in FIG. 3 (see IC 320). [0063] Aspects of the present application provide stress isolated 3D heterogeneous packaged devices. The 3D heterogeneous packaged devices may be small, with electrical connections that are made by solder bumps, a ball grid array, or other techniques, excluding wire bonding.

IV. Fabrication

[0064] Aspects of the present application provide methods for fabricating stress isolated 3D heterogeneous packaged devices. An example of such a method is illustrated in FIG. 8, according to a non-limiting embodiment of the present application. The steps of method 800 may be performed in accordance with the order illustrated in FIG. 8, or in any other suitable order. Any of the apparatuses described herein may be fabricated using method 800, including packages having MEMS devices.

[0065] At step 802, thru silicon vias (TSVs) are formed through an interposer. The interposer may be a passive interposer in some embodiments (e.g., lacking transistors). Optional step 804 may be performed in the context of MEMS devices to form a cap substrate. At this step, a cavity is etched through the interposer in correspondence with the area where a MEMS device, once bonded, will interface with the interposer. An example of such a cavity is cavity 707 of FIG. 7A. At step 806, the interposer is bonded to an IC. The IC may be a digital IC, an analog IC, a MEMS die, a sensor die (e.g., an optical die, a magnetic sensor die, a biosensor die, a microfluidics die) or a combination, among other possible device types. Bonding may be performed in some embodiments using flip-chip techniques. In embodiments in which the IC comprises a MEMS device, step 806 results in the MEMS device aligning to the cavity formed at step 804. At step 808, the interposer’s TSVs are exposed to air, which may involve grinding and/or polishing the top surface of the interposer. At step 810, a redistribution layer (RDL) is formed on the interposer. The RDL may support signal routing across the interposer. At step 812, bond metal pads (e.g., pads 114 of FIG. 1A) are patterned on the interposer. At step 814, trenches (e.g., trenches 113 of FIG. 1A or 713 of FIG. 7A) are formed through the interposer in a way so that stress isolation suspensions (119 or 719) are also formed. This step results in the formation of stress isolation platforms. Optional step 816 involves filling the trenches with gel or other low stress material to improve the mechanical strength of the stress isolation platforms during some of the subsequent fabrication steps. Optional step 818 may be performed in the context of MEMS devices, and involves bonding an ASIC to the MEMS die. At step 820, bumps are dropped onto the bond pads. At step 822, the interposer wafer is diced. Optional step 824 involves removing the gel or other low stress material from the trenches. Lastly, at step 826, the interposer and the IC are bonded to an underlying substrate (e.g., a laminate or a PCB).

[0066] Having thus described several aspects and embodiments of the technology of this application, it is to be appreciated that various alterations, modifications, and improvements will readily occur to those of ordinary skill in the art. Such alterations, modifications, and improvements are intended to be within the spirit and scope of the technology described in the application. It is, therefore, to be understood that the foregoing embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereto, inventive embodiments may be practiced otherwise than as specifically described. In addition, any combination of two or more features, systems, articles, materials, and/or methods described herein, if such features, systems, articles, materials, and/or methods are not mutually inconsistent, is included within the scope of the present disclosure.

[0067] As used herein, reference to a numerical value being between two endpoints should be understood to encompass the situation in which the numerical value can assume either of the endpoints. For example, stating that a characteristic has a value between A and B, or between approximately A and B, should be understood to mean that the indicated range is inclusive of the endpoints A and B unless otherwise noted.