BACKGROUND ART Generally, in an AC plasma display, a voltage of above a predetermined level is alternately applied to two discharge electrodes, to thereby display a picture using a luminescence caused due to the discharge generated between the two electrodes. Then, the discharge is sustained to continuously display the picture. This operation will be explained below in detail.

First, when a pulse having a voltage (write voltage) of above a firing voltage which generates the discharge is applied between the two electrodes so as to produce the discharge, and charges generated during the discharge are accumulated on insulating layers placed on the two electrodes. Here, positive charges caused due to the discharge are accumulated on the insulating layer of one electrode having a relatively low potential, and negative charges are accumulated on the insulating layer of the other electrode having a relatively high potential, to thereby form wall charges. Then, when a pulse having a voltage (sustaining voltage) which is lower than the write voltage and has a polarity opposite to that of the write voltage is applied between two electrodes, if the sum of the sustaining voltage and wall voltage caused due to the wall charges becomes a voltage of above the firing voltage, the discharge occurs again.

Accordingly, if the sustaining voltage is alternately applied to the two electrodes, the discharge is continued because the wall charges are accumulated in a cell in which

the discharge occurs due to the write voltage. This phenomenon is called memory effect, and the AC PDP is driven using this effect.

Fig 1 shows a conventional surface discharge AC PDP.

Referring to Fig. 1, the conventional surface discharge AC PDP includes a display panel P, m scan electrode 2, n addressing electrode 3, k sustaining electrode 4, a cell 5 placed on the intersection of scan electrode 2, sustaining electrode 4 and addressing electrode 3, and a barrier wall 6 for partitioning cell 5 and reducing the interference between cells 5. Here, since sustaining electrodes 4 are connected in common, an identical voltage is applied to every cell.

Fig. 2 shows a cell structure of the conventional surface discharge AC PDP. Referring to Fig. 2, the cell includes a back glass substrate 7, which is shown to users, for protecting cell 5, an addressing electrode 3 for addressing a cell in which data will be written, a fluorescent layer 8 for displaying colors, an insulating layer 10 on which wall charges are accumulated when the discharge occurs, a magnesia layer 9 for preventing the insulating layer from being destructed by collision of the insulating layer, electrons and ions generated during the discharge, a scan electrode 2 for addressing a cell to be discharged together with addressing electrode 3, a sustaining electrode 4 for sustaining the discharge in the cell discharged, and a front glass substrate 11 for protecting cell 5.

The operation of the aforementioned AC PDP will be explained below. Since cell 5 is placed on the intersection of scan electrode 2, sustaining electrode 4 and addressing electrode 3, the total number of the cell is mXn. Here, when a cell is selected by addressing electrode 3 and scan electrode 2, the discharge occurs and data is written in this cell. The discharge is continued between sustaining electrode 4 and scan electrode 2 so as to sustain the discharge.

A method of driving the conventional PDP includes the

total writing step, total erasing step, addressing step for the purpose of discharging a predetermined cell in a predetermined sub-field, and sustaining discharging step for repeatedly carrying out the discharge. However, the conventional PDP driven by the above-described method has the following problems. That is, if the panel becomes large- sized, the distance between electrodes becomes wider. This increases the firing voltage required for discharge.

Furthermore, the luminance is decreased.

DISCLOSURE OF THE INVENTION An object of the present invention is to provide a structure and driving method of a PDP having four electrodes, in which a plurality of sustaining electrodes are formed in one display cell, thereby causing a simultaneous discharging between these electrodes and preventing the luminance from being deteriorated.

To accomplish the object of the present invention, there is provided a plasma display panel structure including: front and back substrates having a predetermined distance therebetween by a barrier wall, the front and back substrates being sealed at their edges; a plurality of scan electrodes; a plurality of addressing electrodes; a plurality of first and second sustaining electrodes, the first and second sustaining electrodes being connected in common; and a plurality of display cells each of which is partitioned by the barrier wall, the display cell being formed on the intersection of the scan electrode, sustaining electrode and addressing electrode.

For the object of the present invention, there is further provided a method of driving a plasma display panel, including the steps of: applying a positive writing pulse to a scan electrode and applying a negative writing pulse to first and second sustaining electrodes during a total writing period of each sub-field, to thereby discharge every display cell; applying a negative sustaining pulse to the first and second sustaining electrodes, applying the ground voltage to the scan electrode, and summing a wall voltage

generated due to wall charges formed by the discharge and the applied voltage, to thereby produce the discharge, the sum of the wall voltage and the applied voltage being higher than a discharge firing voltage; addressing a cell which will not be displayed in the sub-field, and erase- discharging the cell; and applying a negative sustaining pulse to the first and second sustaining electrodes and applying a positive sustaining pulse to every scan electrode, to thereby produce the sustaining discharge in a cell in which the erase discharge does not occur.

BRIEF DESCRIPTION OF DRAWINGS Fig. 1 shows a conventional surface discharge AC PDP; Fig. 2 shows a cell structure of the conventional surface discharge AC PDP; Fig. 3 shows a surface discharge AC PDP having four electrodes according to the present invention; Fig. 4 shows a cell structure of the surface discharge AC PDP having four electrode according to the present invention; Figs. 5A to 5D are timing diagrams showing the operation procedure of the surface discharge AC PDP having four electrodes according to the present invention; Figs. 6A to 6M show profiles of wall charges in a cell according to a driving method of an AC PDP of the present invention; and Fig. 7 shows a field structure for explaining a gray scale displaying method according to the driving method of an AC PDP of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION Reference will now be made in detail to the preferred embodiment of the present invention, examples of which are illustrated in the accompanying drawings.

Fig. 3 shows an AC PDP according to the present invention. Referring to Fig. 1, the AC PDP includes a display panel P, m scan electrode 2, n addressing electrode 3, k first sustaining electrode 4, a second sustaining

electrode 20, a cell 5 placed on the intersection of scan electrode 2, first sustenance electrode 4 and addressing electrode 3, and a barrier wall 6 for partitioning cell 5 and reducing the interference between cells 5. Here, first and second sustaining electrodes 4 and 20 are connected in common.

Fig. 4 shows a cell structure of surface discharge AC PDP having four electrodes according to the present invention. Referring to Fig. 4, the cell includes a back glass substrate 7, which is shown to users, for protecting cell 5, an addressing electrode 3 for addressing a cell in which erase discharge will occur, a fluorescent layer 8 for displaying colors, an insulating layer 10 on which wall charges are accumulated when the discharge occurs, a magnesia layer 9 for preventing the insulating layer from being destructed by collision of the insulating layer, electrons and ions generated during the discharge, a scan electrode 2 for addressing a cell to be discharged together with addressing electrode 3, sustaining electrodes 4 and 20 for sustaining the discharge in the cell discharged, and a front glass substrate 11 for protecting cell 5.

The operation of the AC PDP according to the present invention will be explained below. When a voltage is applied to the scan electrode 2 and the first and second sustaining electrodes 4 and 20, write discharge occurs in the whole cell. Here, this writing voltage produces the discharge between first sustaining electrode 4 and scan electrode 2, and scan electrode 2 and second sustaining electrode 20, to thereby write identical data in the whole cells. Successively, the discharge occurs between addressing electrode 3 and scan electrode 2 during an addressing period, to thereby selectively erase the data. By doing so, the data is written in the cell. Then, a sustaining discharge is produced between first sustaining electrode 4 and scan electrode 2, and scan electrode 2 and second sustaining electrode 20.

Figs. 5A to 5D are timing diagrams showing the operation procedure of the AC PDP according to the present

invention. A voltage of +Vw2 is applied to every scan electrode Y1 to Ym and a voltage of -Vw2 is applied to two sustaining electrodes S1 and S2 during a total writing period of each sub-field, to thereby produce the discharge on both sides in the whole cells (period tl of Figs. 5A and 5B). When the discharge occurs as above, wall charges are accumulated in the cell (period t2 of Figs. 5A and 5B).

Successively, if the voltage of -Vwl is applied to two sustaining electrodes S1 and S2 and the voltage of 0V is applied to every scan electrode Y1 to Ym, a voltage externally applied is added to a wall voltage caused due to the wall charges generated by the prior discharge, to thereby increase the voltage above the discharge firing voltage. This produces the discharge (period t3 of Figs. 5A and 5B). If the discharge occurs described as above, the wall charges are accumulated in the cell (period t4 of Figs.

5A and 5B).

Then, if a voltage of +Vk is applied to every scan electrode Y1 to Ym and the voltage of -Vwl is sustained in two sustaining electrodes S1 and S2, the discharge does not occur in the whole cells, sustaining the wall charges generated during the prior discharge (period t5 of Figs. 5A and 5B). At this state, in case that a picture is displayed on the panel, only data required for displaying the picture should be written. Thus, the data written in the cell during the addressing period is selectively erased, and then sustaining discharge is produced, to thereby display the gray scale of each cell.

Accordingly, display data to be erased is sequentially erased from the first display line of the panel. That is, the voltage of 0V is applied to the first scan electrode Y1, the voltage of -Vwl is sustained in two sustaining electrodes S1 and S2, and a voltage of +Va (addressing voltage) is applied to addressing electrode A of the display line to be erased, to thereby produce erase discharge between first scan electrode Y1 and addressing electrode A (period t6 of Fig. 5A and 5B). Meanwhile, in a cell which does not need erase, if the voltage of 0V is applied to

addressing electrode A, the discharge does not occur between first scan electrode Y1 and addressing electrode A (period t6 of Figs. 5A, 5B and 5C).

As described above, when the discharge occurs, the wall charges in the cell are erased (period t7 of Figs. 5A, 5B and 5C). Thereafter, the voltage of +Vk is applied to first scan electrode Y1 before the selection of next display line, finishing the operation of writing data about the first display line in the cell. Here, the discharge does not occur by the applied voltage, sustaining the wall charges (period t8 of Figs. 5A, 5B and 5C). That is, the display line is selected by applying the voltage of 0V to each scan electrode when the voltage of +Vk is applied to every scan electrode Y1 to Ym.

As described above, after the display line is sequentially selected and the data in the cell to be erased is erased, the sustaining discharge starts. Then, if the voltage of -Vw2 is applied to two sustaining electrodes S1 and S2 and the voltage of +Vk is applied to every scan electrode Y1 to Ym, the sustaining discharge is continued in the cell in which the erase discharge does not occur (period t9 of Figs. 5A, 5B and 5C).

By doing so, the sustaining discharge is continued, to thereby display the gray scale. Furthermore, the sustaining discharge occurs between first sustaining electrode S1 and scan electrode Y1, and second sustaining electrode S2 and scan electrode Y2, thereby increasing the luminance.

In Fig. 5C, the voltage applied to addressing electrode A shows the voltages of Va and OV produced if the cell is erased or not. Fig. 5D shows the discharge current which flows through scan electrode Y1 during the discharge.

Periods tl and t2 are the total writing period, periods t3 and t4 are the sustaining discharge period, periods t5 to t8 are the addressing period, and the next period is the sustaining discharge period.

Figs. 6A to 6M show profiles of the wall charges in the cell, which are generated during periods tl to t9. Period tl of Fig. 6A shows the discharge state generated in case that

the voltage of +Vw2 is applied to every scan electrode Y1 to Ym, and the voltage of -Vw2 is applied to two sustaining electrodes S1 and S2. Period t2 of Fig. 6B shows that positive charges are accumulated on the insulating layer placed on sustaining electrodes S1 and S2 having a relatively low potential, and negative charges are accumulated on the insulating placed on scan electrode Y1 having a relatively high potential after the discharge occurs.

Period t3 of Fig. 6C shows the discharge state when the voltage of 0V is applied to every scan electrode Y1 to Ym, and the voltage of -Vwl is applied to sustaining electrodes S1 and S2. Period t4 of Fig. 6D shows the wall charges profile after the discharge. Period t5 of Fig. 6E shows that the discharge does not occur and the wall charge profile of Fig. 6D is maintained in case that the voltage of +Vk is applied to every scan electrode Y1 to Ym, and the voltage of -Vwl is applied to sustaining electrodes S1 and S2.

Period t6 of Fig. 6F is the charge profile right after the addressing period, showing the discharge occurrence between the addressing electrode and scan electrode when the voltage of 0V is applied to first scan electrode Y1, the voltage of -Vwl is applied to sustaining electrodes S1 and S2, and the voltage of +Va is applied to the addressing electrode to carry out the erase discharge. Period t7 of Fig. 6G shows the wall charge profile after the discharge of Fig. 6F. Here, two periods t6 and t7 correspond to the erase discharge period, during which the cell which does not need to be displayed is erased.

Meantime, periods t6 and t7 of Figs. 6J and 6K show that the voltage of 0V is applied to addressing electrode A and first scan electrode Y1, and the voltage of -Vwl is applied to sustaining electrodes S1 and S2 so as not to discharge the cell to be displayed, thereby sustaining the wall charges.

Period t8 of Figs. 6H and 6L shows the state after the addressing of the first display line, and before the selection of the next display line. Here, the voltage of

-Vwl is applied to sustaining electrodes S1 and S2, and the voltage of +Vk is applied to scan electrode Y1, to thereby decrease the sum of the applied voltage and wall voltage below the discharge firing voltage. By doing so, the discharge does not occur.

Period t9 of Figs. 61 and 6M is the final period following the aforementioned periods. In this period, the sustaining discharge occurs when the voltage of +Vk is applied to every scan electrode Y1 to Ym, and the voltage of -Vw2 is applied to sustaining electrodes S1 and S2. Here, the discharge does not occur in the cell which is erase- discharged.

Fig. 7 shows the field structure for displaying 256 gray scales designed for PDP having four electrodes according to the present invention. Referring to Fig. 7, one field (or frame) is divided into eight sub-fields, and the number of times of sustaining discharge is controlled at each sub-field, to thereby display the gray scale. That is, the number of times of sustaining discharge is 128 times at sub-field 1, the number of times of sustaining discharge is sixty-four times at sub-field 2, thirty-two times at sub- field 3, sixteen times at sub-field 4, eight times at sub- field 5, four times at sub-field 6, twice at sub-field 7 and one time at sub-field 8.

In the driving of the PDP of the present invention, identical data is simultaneously written in the whole cells of the panel, and then the sustaining discharge is produced during the total writing period and sustaining discharge period. During the second addressing period, the cell which will not be displayed is addressed, and then the discharge (erase discharge) occurs between the sustaining electrode and addressing electrode, to thereby erase the cell. Then, the third sustaining discharge period is followed. This procedure is repeated eight times, thereby finishing one field.

The addressing period corresponds to data writing (address) time, and it is identical in each field. The display period (discharge period) for the written data

corresponds to the sustaining discharge period. In this period, the gray scale of the picture is displayed by making the width of each- sub-field different from one another.

INDUSTRIAL APPLICABILITY According to the present invention, a plurality of sustaining electrodes are formed in one cell. By doing so, the luminance is prevented from being deteriorated due to the enlargement of the panel, and thus pictures can be clearly displayed.

Therefore, it should be understood that the present invention is not limited to the particular embodiment disclosed herein as the best mode contemplated for carrying out the present invention, but rather that the present invention is not limited to the specific embodiment described in this specification except as defined in the appended claims.