SUB-UNIT, MAC ARRAY, BIT-WIDTH RECONFIGURABLE HYBRID ANALOG-DIGITAL IN-MEMORY COMPUTING MODULE

WIPO Patent Application WO/2021/232949

A1

A sub-unit for hybrid analog-digital in-memory computing, used for one-bit multiplication computing, which only needs 9 transistors. On this basis, multiple sub-units share computing capacitors and transistors to form a computing unit, so that there are nearly eight transistors for the sub-units in average, and thus provided is a MAC array, which is used for multiplication and accumulation computing and comprises multiple computing units, sub-units in each unit being activated in a time-division multiplexing manner. Further, provided is a differential system of the MAC array for improving the fault tolerance of computing. In addition, provided is a hybrid analog-digital in-memory operation module, which digitizes parallel analog output of the MAC array and performs other digital domain operations. An analog-to-digital conversion module in the operation module makes full use of the capacitors of the MAC array, thus reducing both the area of the operation module and the computing error. Furthermore, provided is a method for making full use of data sparsity to save energy consumption by the analog-to-digital conversion module.

JPH07273652	A/D CONVERTER CIRCUIT
JP2024505877	Lookup table-based analog-to-digital converter
JP2002198817	LADDER RESISTOR

YANG MINHAO (CN)
LIU HONGJIE (CN)
MORGADO ALONSO (CN)
WEBB NEIL (CN)
ENZ CHRISTIAN (CN)

PCT/CN2021/084022

November 25, 2021

March 30, 2021

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REEXEN TECH CO LTD (CN)

H03M1/46; H03M1/38

CN111431536A	2020-07-17
CN110941185A	2020-03-31
CN111144558A	2020-05-12
US20130194120A1	2013-08-01
CN101807923A	2010-08-18
CN202010418649A	2020-05-18

See also references of EP 3989445A4

BEIJING GAOWO LAW FIRM (CN)

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