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Title:
SUB-UNIT, MAC ARRAY, BIT-WIDTH RECONFIGURABLE HYBRID ANALOG-DIGITAL IN-MEMORY COMPUTING MODULE
Document Type and Number:
WIPO Patent Application WO/2021/232949
Kind Code:
A1
Abstract:
A sub-unit for hybrid analog-digital in-memory computing, used for one-bit multiplication computing, which only needs 9 transistors. On this basis, multiple sub-units share computing capacitors and transistors to form a computing unit, so that there are nearly eight transistors for the sub-units in average, and thus provided is a MAC array, which is used for multiplication and accumulation computing and comprises multiple computing units, sub-units in each unit being activated in a time-division multiplexing manner. Further, provided is a differential system of the MAC array for improving the fault tolerance of computing. In addition, provided is a hybrid analog-digital in-memory operation module, which digitizes parallel analog output of the MAC array and performs other digital domain operations. An analog-to-digital conversion module in the operation module makes full use of the capacitors of the MAC array, thus reducing both the area of the operation module and the computing error. Furthermore, provided is a method for making full use of data sparsity to save energy consumption by the analog-to-digital conversion module.

Inventors:
YANG, Minhao (CN)
LIU, Hongjie (CN)
MORGADO, Alonso (CN)
WEBB, Neil (CN)
ENZ, Christian (CN)
Application Number:
PCT/CN2021/084022
Publication Date:
November 25, 2021
Filing Date:
March 30, 2021
Export Citation:
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Assignee:
REEXEN TECHNOLOGY CO., LTD. (CN)
International Classes:
H03M1/46; H03M1/38
Attorney, Agent or Firm:
BEIJING GAOWO LAW FIRM (CN)
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