Technical Field This invention relates to printed wiring board compositions for use in surface mounted component assemblies. Background of the Invention

Referring to FIGURE 1 (Prior Art), many modern electronic cir¬ cuits feature surface mounted component assemblies 10 in which electrical components such as leadless ceramic chip carriers 12 are soldered directly to a printed wiring board 14, without through-hole mounting. A plur-ality of solder joints typically connect the leadless chip carrier 12 to the printed wiring board 14. Each solder joint typically consists of a thin (0.002 to 0.005 inch) rectangular solder layer 16 between an electrically conductive pad 18 on the underside of the carrier 12 and a corresponding conductive pad 20 on a conductor pattern 22 deposited on a circuit board substrate 24. In addition, an approxi- mately triangular solder fillet 26 is usually provided at each solder joint, sloping upward from the conductive pad 20 in contact with a metallized, semicircular castellation 28 that extends upwardly from the conductive pad 18 on the side of the carrier 12. The solder fillet 2S is provided in order to facilitate visual inspection of the solder joint. The solder joints 16, 26 in surface mounted component assemblies 10 provide mechanical as well as electrical connection between the chip carrier 12 and the printed wiring board 14.

Surface mounted technology lends itself well to miniaturization and provides other advantages. However, the solder joints 16, 26 are susceptible to fracture, particularly in environments where alternating stresses are trans- mitted into the joint. Thermal cycling failure due to differential thermal expansions of the component 12 and the substrate 24 is a recognized cause of solder joint cracking, especially in aerospace applications that repeatedly subject the surface mounted component assembly 10 to thermal cycles involving sub¬ stantial temDerature variation.

Many researchers in this field have concluded that solder joint fractures in such assemblies 10 are caused by a mismatch of the thermal coefficients of expansion of the leadless ceramic chip carriers 12 and the printed wiring board 14. This mismatch of thermal coefficients of expansion, or the fractional change in length per unit change in temperature, is significant for circuit board substrates 24 manufactured from conventional epoxy, polyimide, melamine, or silicone glass-reinforced board laminates. For example, the thermal expansion coefficients for the materials that make up a typical surface mounted component assembly 10 are shown in TABLE 1.

[0

TABLE 1

Leadless ceramic chip alumina carrier 7.0 lO -6 _s inch/inch°C

63Sn37Pb solder alloy 25.0 x 10 ^"6 ' iiinch/ϊnch°C

15 Copper (oxygen free; wrought) 17.64 x 10 -6 " inch/tnch°C

— ^'

Epoxy/glass laminate 10.0 x 10 inch/inch°C w/weave,

15 x 10 inch/inch°C crossweave

Such surface mounted component assemblies 10 are- subject to 0- shear strain-initiated fractures due to the above-stated mismatch of thermal expansion coefficients. Moreover, fractures occur more frequently during ambient to low temperature cycling than during ambient to high temperature cycling because solder alloys generally have much lower ductility (elongation or strain capability) at low temperatures than at elevated temperatures. 5 It was thought that the development of circuit board substrates 24 having thermal coefficients of expansion more closely matching those of the leadless ceramic chip carriers 12 would eliminate the problem of thermal cycling failure. To that end, several distinct circuit board substrates 24 have been developed: alumina ceramic substrates; porcelain-enamelled steel; glass- 0 reinforced and low-expansion alloy laminates, e.g., combinations of copper and nickel/iron alloys; a new family of quartz/epoxy and/or polyimide laminates; and graphite-reinforced laminates. Although some of these substrate compositions may ameliorate the problem of thermal cycling failure, specifically applying the criteria of extended life (greater than 1,000 cycles) when the assemblies are 5 subjected to low temperature rate thermal fatigue in the range -55°C to 125°C, those substrates present other disadvantages, including increased weight and cost. The low cycle rate is emphasized because it is the most damaging to contemporary tin/lead solder alloys. Reference is made to MIL-STD-883 Test

Methods for Micro Electronics METHOD 1010.4 Temperature Cycling; Condition B (August 31, 1977), hereby incorporated by reference herein. The referenced thermal cycling range is used generally to test all surface mounted component assemblies through 1,000 cycles. In addition to the extreme environmental thermal cyclings, experienced particularly in military appli¬ cations, a second operational condition associated with power cycling also contributes to thermal cycling failure in surface mounted component assemblies 10 generally. Power cycling refers literally to switching components 12 ON and OFF. When powered ON, high-powered components such as microprocessors, typically housed in 1.2 inch x 1.2 inch leadless chip carriers, may dissipate upwards of 3.0 to 5.0 watts. Such power dissipations cause the component 12 to be at a substantially higher temperature than the printed wiring board 14.

Moreover, although thermal cycling-induced strains in the solder joint 16, 26 may be substantially reduced in assemblies 10 in which the thermal expansion coefficients of the component 12 and substrate 24 are closely matched, a different fracture mechanism then becomes apparent. This fracture mechanism results from a thermal expansion coefficient mismatch between the component 12 and the solder in the triangular solder fillets 26. These strains are tensile throughout the low-temperature portion of a typical operating range and compressive in the high-temperature portion. This fracture mechanism is significant during the cooling process from vapor phase soldering to ambient conditions.

Referring now to FIGURE 2 (Prior Art), a second approach to the problem of thermal cycling failure in surface mounted component assemblies 10' has involved the development of printed wiring boards 14' having a resilient layer 30 between the circuit board substrate 24 and the conductor pattern 22 to which the leadless ceramic chip carriers 12 are soldered. This approach postulates that stresses in the solder joint 16, 26 are thereby eliminated because the electronic component 12 is allowed to "float" on a resilient compliant layer material 30.

In this regard, U.S. Patent No. 3,818,279 is of interest for dis¬ closing an electrical interconnection and contacting system comprising an insulator flexible plastic, most preferably elastomeric material substrate having at least one layer of electrically conductive elastomeric material embedded therein.

U.S. Patent No. 4,042,861 discloses an integrated circuit block assembly provided with a baseplate, a flexible printed circuit sheet, and

integrated circuit chip components. The flexible, non-conductive sheet is made preferably of polyester, polyimide or the like resin material and carries thereon several groups of conducting strips. This flexible printed circuit sheet reportedly helps, inter alia, to protect the integrated circuit components from adverse effects of outside mechanical shocks.

U.S. Patent No. 4,150,420 describes an electrical connector for joining microcircuit modules to circuit boards. The electrical contacts through which the generally coplanar module and board are connected are formed and etched in place on an overlying elastomeric material, the material reportedly acting as a restoring force to maintain connection in case of shock, vibration, or thermal expansion of the substrate used to carry the microcircuit module. The elastomeric material is preferably a 50 durometer silicone rubber compound with low compression set.

U.K. Patent Application GB 2 097 998 A is of particular interest for disclosing a method of surface mounting integrated circuit components including the step of providing between a rigid substrate base and a surface layer incorporating a conductor pattern, to which surface layer the components are secured by means of electrical interconnections between the components and the pattern, an intermediate layer of compliant insulating material. The inter- mediate layer reportedly absorbs differential thermal expansions which may occur between the components, when mounted, and the base. The compliant layer is described generally as a thin layer of insulating elastomer with a low elastic modulus. Because of the compliance of the elastomer layer, strain due to thermal expansion mismatch is reportedly not transmitted to the solder joints. The elastomer layer is stated to be preferably an uncured thermosetting polymer which when subsequently cured has suitable properties to accept the subse¬ quently deposited metal conductor pattern. Polymers with known electrical properties and applications are stated to comprise epoxy resins, polyimides, acrylonitrile butadienes, etc. The thickness of the elastomer layer reportedly depends on the requirement of the finished product. The thicker the layer the more stress relief there will be between the component and the rigid substrate. Conversely, the thinner the layer the better will be heat dissipation from the components via the substrate, particularly if the latter has a rigid metal base.

U.S. Patent No. 4,413,308 provides a mounting arrangement for an integrated circuit leadless chip carrier for providing compliance to prevent solder joint failure due to stress and differential thermal expansion. A supporting substrate board has bonded to one surface a flexible sheet carrying printed wiring to which the carrier is electrically connected by means of solder

pedest-als. Adjacent to the solder pedestals the board presents recesses over which the sheet is freely suspended to provide free sheet portions which absorb the stress and differential expansion to protect the solder connections. Any differential changes in the dimensions of the chip carrier and board as well as strains due to handling are reportedly absorbed by the aforementioned free sheet portions.

Another reported attempt to develop a circuit board with surface elasticity and characteristics that would accommodate the differences in thermal expansion between alumina ceramic leadless chip carriers and glass epoxy printed circuit boards recommends a resin layer having a Young's modulus fi 2 of elasticity equal to 8 x 10 lb/in as an intermediate compliant layer. For this purpose several laminated sheets of unreinforced epoxy or polyimide, e.g., a triple layer of 0.002 inch epoxy sheets, reportedly work better than a single uniform coating of low modulus epoxy. Thermal cycling failure in boards having the thicker, uniform epoxy layer is reportedly due to stiffness or high modulus of elasticity. International Journal for Hybrid Micro Electronics 6(l):21-26, 1983.

A very recent report of temperature cycling resistance in surface mounted component assemblies emphasizes the use of an unreinforced resin layer between the copper conductive material and the glass fabric reinforcing material. The ideal unreinforced resin material for this purpose reportedly has a modulus of elasticity of 2.60 x 10 5 lb/in 2 or less, e.g., a polyimide resin having a modulus of elasticity (E) of 0.61 x 10 lb/in , or an epoxy having E equal to fi 2

0.4 x 10 lb/in . The requisite thickness of a compliant layer having those elastic limits is also defined. Electronic Packaging <5c Production, pp. 84-90, January 1985.

While suitable for some applications, the foregoing assemblies do not provide complete solutions to the problem of thermal cycling failure of the solder joints between leadless ceramic chip carriers and printed wiring boards. Specifically, the compositions of the foregoing intermediate layers have not been precisely defined and tested in terms of their projected performance. Nor have the thermal management problems associated with the introduction of inter¬ mediate layers into surface mounted component assemblies been addressed.

Summary of the Invention An improved method is provided for surface mounting electronic components such as leadless chip carriers on circuit boards having an inter¬ mediate layer of resilient material between a circuit board substrate and a surface layer incorporating a conductor pattern to which the components are connected by a plurality of solder joints. One aspect of the improvement

involves selecting the resilient material such that the modulus of rigidity (G) of the intermediate layer has a maximum value that is defined in terms of the thickness of the intermediate layer, the component size, the cyclic temperature range, and the maximum permissible shear force on the solder joints, as follows:

^{G <} - τ ^{~ ω} wherein

F is the maximum permissible shear force on a solder joint located midway along a side of the component most remote from the component geometric center,

ΔT is the maximum temperature change experienced in the produc¬ tion and service history of the assembly, and,

^A s ^L P = — f— ( ^~ _b - ^~ ₍ .) + (l +v ) _l ( ^~ ₁ - . _Q ) (2)

wherein

A is the horizontal cross-sectional area of the solder joint, s

L is the distance beween the geometric centers of the component and the solder joint, t is the thickness of the intermediate layer, α. is the thermal coefficient of expansion of the circuit board substrate, α is the thermal coefficient of expansion of the component, u is the Poisson's ratio for the resilient material,

A, is the vertical cross-sectional area of the intermediate layer underlying the solder joint, taken transverse to a line between the geometric center of the component and the geometric center of the solder joint, and, α. is the thermal coefficient of expansion of the intermediate layer.

Also provided are improved surface mounted component assemblies having an intermediate layer characterized by a modulus of rigidity defined by Equations (1) and (2).

Selecting a resilient material such that the intermediate layer has a modulus of rigidity within the range defined by Equations (1) and (2) solves the problem of thermal cycling failure of solder joints in surface mounted component assemblies of single-, double- or multi-layer configuration. Suitable resilient materials for particular applications include adhesive/ elastomer blends wherein

the adhesive is selected from among epoxy, polyimide, phenolic, and elamine resins and the elastomer is selected from acrylonitrile butadiene, neoprene, rubber, and vinyl. In a preferred embodiment the elastomer acrylonitrile butadiene is admixed with one or more adhesives selected from epoxy resins, polyimide resins, and phenolic resins in order to formulate a resilient material for use as an intermediate layer having a requisite modulus of rigidity as calculated from Equations (1) and (2) for a particular surface mounted compo¬ nent assembly and application. A representative formulation useful for many aerospace applications is phenolic/acrylonitrile butadiene (1:1). Another aspect of the improvement involves the alleviation of thermal management problems by admixing the resilient material with a dielectric, thermally conductive material such as alumina flour. The alumina flour content of the intermediate layer can range from about 5 volume percent to about 40 volume percent, dependent upon the nature and adhesive/elastomer content of the resilient material.

Brief Description of the Drawings FIGURE 1 (Prior Art) is a perspective drawing with a partial cutaway showing two solder joints between a leadless ceramic chip carrier and a printed wiring board midway along adjacent sides of a conventional surface mounted component assembly;

FIGURE 2 (Prior Art) is a drawing like FIGURE 1 except that an intermediate layer of compliant insulating material is provided between the conductor pattern and the circuit board substrate in the printed wiring board;

FIGURE 3 is a graph showing representative modulus of rigidity (G) maxima as functions of component size and solder composition for resilient intermediate layers in representative surface mounted component assemblies of the invention;

FIGURE 4 is a section in the XY plane of FIGURE 1; FIGURE 5 is a detail of the solder joint shown in FIGURE 4; and, FIGURE 6 is a section taken in the XY plane of FIGURE 2.

Description of the Preferred Embodiment An improved method is provided for surface mounting electronic components such as leadless chip carriers onto circuit boards having an inter¬ mediate layer of resilient material between a rigid substrate base and a surface layer incorporating a conductor pattern to which the components are electrically and mechanically connected by solder joints. The elimination of thermal cycling-induced solder joint fractures in surface mounted component assemblies by resilient layer means requires that for any particular combination of circuit

board substrate and components used in the assembly there exists a maximum permissible value of the modulus of rigidity (G) of the resilient intermediate layer, wlύch G value can be defined in terms of the thickness of the intermediate layer, the component size, the cyclic temperature range, and a maximum shear force that is, by design, permitted to act upon the solder joints.

For the purposes of this disclosure the following parameter sym- bology is employed:

G = Modulus of rigidity of the intermediate lbs/inch 2 kg/cm 2 layer.

E = Modulus of elasticity of the intermediate lbs/inch 2 kg/cm 2 layer. μ = Poisson's ratio for the intermediate layer. Dimensionless t = Thickness of the intermediate layer. inches cm

L = Distance between the component geometric inches cm center and the geometric center of a solder joint located midway along a component side most remote from the component geometric center. α = Thermal coefficient of expansion of the inches cm component. inch ^u C cm ^u C o.. = Thermo coefficient of expansion of the inches cm intermediate layer. inch°C cm°C

< . = Thermal coefficient of expansion of the inches cm circuit board substrate. inch°C cm°C

A = Area identified by subscript. inches cm e

A. = The vertical cross-sectional area of the inches ^' ' cm intermediate layer underlying the solder joint, transverse to a line between the component geometric center and the solder joint geometric center (e.g., in plane YZ for the solder joint shown in FIG. 4). ε = Mechanical strain identified by subscript. Dim ensionless

F = Maximum permissible shear force on solder lbs kg joint.

Thermal tensile force. lbs k

F s = Thermal shear force. lbs kg

Δ T = Maximum temperature change experienced in °C °C production and service history of the assembly. c Subscript referring to the component. s Subscript referring to the solder joint. 1 Subscript referring to the intermediate layer. b Subscript referring to the circuit board substrate.

Pursuant to the invention, the resilient material is selected such that the modulus of rigidity G of the intermediate layer is as follows:

G < ΔTP (1)

wherein

A 3 L

P = ( — -( - o _c ) + (1 +μ ) A _j (.*. - c^) } (2)

It will be noted that the relationship defined above is primarily concerned with thermomechanical strains (P), since the fracture of solder joints subjected to thermal cycling is a strain fatigue rather than a stress fatigue failure; see Analysis 1 below.

The curves shown in FIGURE 3 define maximum permissible values of G obtained from Equations (1) and (2) when the stated parameters are given the following representative values:

ΔT = 238 °C This temperature change represents the difference between the eutectic point (183°C) of the most commonly employed 63Sn37Pb solder alloy and -55°C, the lowest temperature most commonly used in thermal cycle testing. This high Δ T value results in a conservative estimation of G.

A. 1.25 x 10~ ³ inches ² The product .050 x .025, being the hori¬ zontal cross-sectional dimensions of a typical solder joint between an electri¬ cally conductive pad on the underside of a leadless ceramic chip carrier and a corresponding conductor pad on a con¬ ductor pattern deposited on a circuit board substrate.

.005 inches Which value is compatible with the gauge thickness of adhesive films commonly available in industry.

α = 15 x 10 -6 inches inch ^u C The maximum value for the glass re¬ inforced epoxy resin substrates common in printed circuit board practice.

= 7.0 x 10 ^■ 6 inches inch ^u C A published value for alumina ceramic material used in leadless ceramic chip component manufacture.

= 0.4 The gener-ally accepted value for elasto¬ meric materials.

-4 . = 1.25 x 10 inches The product of .005 x .025, the thickness of the intermediate layer times the width of the solder joint.

Value is an average for phenolic or epoxy based elastomer modified adhesive films. For a typical surface mounted component assembly having the above-stated representative parameter values the magnitude of P according to Equation (2) is as follows:

P = { 2.0 x l0~ ⁶ L + 4.25 x lθ ^"8 } . (3)

Substituting Equation (3) into Equation (1) gives the following relationship:

F

G -

238(2.0 x 10 ^_6 L + 4.25 x 10 ⁸ )

G < 4.2 x 10 F

(2.0 lθ ^"6 L + 4.25 x 10 ^~8 ) (4)

Representative values of L and F can then be selected for particular components and applications in order to determine the requisite modulus of rigidity G for the intermediate layer.

For example, the curves in FIGURE 3 indicate the maximum values of G as defined by Equations (1) and (2) and as calculated using Equation (4) where L is varied in the range of 0.1 to 0.8 inches and F is varied in 0.25 lb increments from 0.25 to 1.25 lbs. These representative G maxima are also tabulated below in TABLE 2.

TABLE 2

7

Representative G maxima (lbs/in ).

L F →- .25 .50 .75 1.0 1.25

-t-

0.1 4340 8681 13021 17362 21703

0.2 2376 4753 7129 9506 11882

0.3 1636 3272 4908 6544 8180

0.4 1247 2495 3742 4990 6237

0.5 1008 2016 3024 4032 5040

0.6 846 1691 2537 ^■ 3383 4229 0

0.7 728 1456 2185 2914 3642

0.8 640 1280 1919 2559 3198

The representative range of selected L values encompasses typical leadless ceramic chip carriers having pad counts N where 20 ≤ N 84. By -5 L value is meant the horizontal distance (L) between a first point underlying the geometric center of the component and a second point at the geometric center of a solder joint midway along a side of the component most remote from the first point. It is understood that the envelope of G values may be expanded to include components having pad counts N greater than 84, which limit is pre- 0 sented for illustration only. It is also understood that the invention can be defined with reference to the L and F values incident to any other solder joint, e.g., at any corner of a rectangular component, by including an appropriate vectorial analysis into the derivation of Equations (1) and (2) as disclosed below.

The representative range of F values, meaning the maximum 5 permissible shear force on a solder joint midway along one of the sides most remote from the geometric center of the component, corresponds to solder joint shear stresses in the 200 p.s.i. to 1,000 ρ,s.i. range and encompasses the 10 minutes rupture stress values for the most commonly used tin lead solder alloys, i.e., 459 lbs/inc and 326 lbs/inch" for the 63Sn37Pb and 60Sn40Pb alloys, respectively. Those skilled in the art will realize that the assignment of F values should be conservatively made, as there is currently little data available on the variation of the solder properties during thermal cycling. The evaluation of joint stresses corresponding to particular strain values is made very complex due to the wide variation of the elastic properties of solder at differing strain rates, 5 especially when cyclic temperature variations are considered. It is nevertheless contemplated that even using 1,000 p.s.i. (1.25 lbs force) in the 238°C temper¬ ature step would yield a conservative design for 1,000 thermal cycles. Further¬ more, the typical cyclic stresses encountered during the service history of

surface mounted component assemblies corresponds to only a 35°C + 90°C pure stress reversal, as the 238°C step is applied but once during assembly production. Actual cyclic shear stress (-55 to +125°C) on the order of only 378 lbs/inch would thus be typically encountered. An important aspect of the invention is the discovery that, with respect to reducing solder joint stresses, the modulus of rigidity of the intermediate layer is of far greater importance than the modulus of elasticity of the intermediate layer; see Analysis 3 below. If the stress analysis is performed using terms that derive only the tensile force (F , as taught in the art, then the maximum tensile modulus obtained will be far greater than that permissible in an operating system. Specifically, such an overly simplistic analysis yields the following tensile force v-alue, as derived in Equation (26a) in Analysis 2 below:

E,A, ΔT

F = — ( ^α - - α }. ^r t 2 ^l 1 c "

If a unit force of 1.0 lb is permitted to act upon the solder joint in this expression, then the permissible value of E using the same data points is:

2 1.00

E ≤

1.25 x lθ ^"4 x 238 x 243 x 10 -6

E ≤ 276,653 lbs/inch ² .

Pursuant to the invention, what does solve the problem of thermal cycling failure are adhesive/elastomer blends selected to provide the requisite modulus of rigidity for the application considered. The adhesive can include one or more epoxy resins, polyimide resins, phenolic resins, and melamine resins. The elastomer can include acrylonitrile butadiene, neoprene, rubber, and/or vinyl. The elastomer content in the adhesive/elastomer blend is adjusted to lower the modulus of rigidity of the blend to within the operable range determined by Equations (1) and (2) in relation to the particular assembly and operating environment. Those familiar with the adhesive art will recognize that specifying an adhesive/elastomer blend by virtue of its modulus of rigidity being equal to or less than some particular lbs/inch 2 (kg/cm 2 ) value is a unique requirement except in applications for vibration damping, in which case the G value is usually combined with damping capacity and transmissibility require¬ ments.

In selecting the formulation of adhesive/elastomer compositions for use as the subject resilient material three criteria should preferably be met: First, and of critical importance, the resilient material must be formulated such that the modulus of rigidity of the resulting intermediate layer falls within the requisite envelope defined by Equations (1) and (2). Second, the resilient material, when cured, must be capable of withstanding exposure to the high temperatures and reactive chemicals that are encountered during printed circuit board manufacture. Third, the resilient material should have long-term resist¬ ance to the environmental conditions in which the particular assembly will operate.

Add to the foregoing three criteria the dielectrical properties required of the intermediate layer, and it is contemplated that adhesive/elasto¬ mer blends practically comprise the set of usable resilient materials, with the critical variable being the modulus of rigidity. Suitable resilient materials for meeting the foregoing second and third criteria include the following adhesive/elastomer blends that are widely used in aerospace applications: epoxy/phenolic, epoxy/polysulfide, epoxy/nylon, nitrile/phenolic, neoprene/phenolic, and vinyl/phenolic. Such adhesive/elastomer blends can be conveniently formulated, e.g., by varying the percentage content of the elastomer, to achieve the requisite modulus of rigidity once that envelope of G values has been calculated for a particular assembly and application.

Representative but nonlimiting examples of elastomer/adhesive blends suitable for use as the subject resilient layer in particular assemblies for particular applications are shown in TABLE 3.

TABLE 3

Alloy Formulation Youngs Modulus Mod. of Rigidity lbs/inch ² (E) lbs/inch ² (G)

AF 31 (3M) Nitrile Phenolic 41,900 13,666 * (high phenolic)

AF 30 (3M) Nitrile Phenolic 16,700 5,566 * (medium phenolic)

AF 30 (3M) Nitrile Phenolic 11,800 3,933 * (low phenolic)

F.M. 238 (AC) 50% Nitrile Phenolic No data Much lower than F.M. 123 below.

F.M. 123 (AC) Nylon Epoxy 321.000 * 107,000

F.M. 47 (AC) Vinyl Phenolic 351,000 * 117,000

F.M. 1,000 (AC) Nylon Epoxy 192,000 * 64,000

P.L. 639 (Goodrici Nitrile Phenolic 720 * 240

(Modified) (7% Alumina)

* Calculated from E = 3G.

(3M) = Minnesota Mining <5 Manufacturing.

(AC) = American Cyanamid Co.

P.L. 639 (Modified) is a material manufactured for the assignee of the invention by B.F. Goodrich.

For use in typical surface mounted component assemblies, such as those illustrated by FIGURE 3 and TABLE 2, nitrile phenolic blends are preferred by virtue of their commercial availability in formulations having relatively low moduli of rigidity that f-all within the requisite limits defined by Equations (1) and (2) as calculated using Equation (4).

In another aspect, the invention provides a method of alleviating thermal management problems in surface mounted component assemblies by admixing the resilient material with a dielectric, thermally conductive material such as alumina or the other oxides shown in TABLE 4.

TABLE 4

Thermal Conductivity

Material (Btu/hour fr°F/ft)

Beryllia (BeO) 95.2

Alumina (AUO 10.4

Calcia (CaO) 4.12

Magnesia (MgO) 1.47

Silica (SiO .8

Beryllia has the highest thermal conductivity but is considered a health hazard, and so alumina is considered to be preferred for most applica¬ tions, as calcia, magnesia, and silica when introduced into the intermediate layer would not give the same level of thermal management enhancement. The dielectric, thermally conductive material is preferably introduced into the intermediate layer as a flour that is admixed with the resilient material. The

flour content of the intermediate layer can range from about 5 volume percent to about 40 volume percent, dependent upon the nature and adhesive/elastomer content of the resilient material.

The inclusion of alumina flour impacts the intermediate layer in the following ways. With increasing content of alumina flour: (a) the thermal conductivity of the intermediate layer increases; (b) the elastic properties G and E of the intermediate layer increase; (c) the thermal coefficient of expan¬ sion of the intermediate layer is reduced; (d) the adhesive bonding efficiency of the intermediate layer is reduced; and, (e) production of an intermediate layer having a homogeneous and iso tropic distribution of alumina is rendered more difficult.

In a representative realization of the invention, a phenolic/acrylc- nitrile butadiene (1:1 wt%) blend (P.L. 639; B.F. Goodrich) is modified by the admixture of 7 volume percent alumina flour having a Screen Analysis % (Tyler Standard Screen) of 20-35% on a 325 mesh and 65% to 80% through a 325 mesh of average particle size = 20 microns. Such an alumina flour is commercially available: #H-36, Kaiser Chemicals. The resulting resilient material has a modulus of rigidity of 240 lbs/in , which makes it suitable for use as inter¬ mediate layers having thickness (t) in many surface mounted component assemblies.

The invention is further illustrated by the following An-alyses and Examples.

ANALYSIS 1 Analysis of the thermomechanical strains that occur in solder joints between leadless chip carrier components and printed wiring board substrates during thermal cycling. FIGURE 4 shows the area of the cutaway view in the XY plane of FIGURE 1. The solder fillet 26 is shown as an ideal triangular fillet. Because this assembly 10 is not provided with a resilient intermediate layer, the copper pad 20 beneath the solder joint 16, 26 is constrained to deflect with the circuit board substrate 24. The components are shown at room temperature (21°C). Determination of the shear strain in the solder joint through height "h".

When the assembly 10 is heated through a temperature change Δ T, the change in length (L) of the substrate 24 can be expressed as:

L. = L Δ T . inches. (5)

The corresponding change in length L of the component 12 is:

L = L Δ Tα inches. (6) c c

The differential expansion (e) of the substrate 24 and component 12 at L is:

e = L Δ.T ( - α ) inches. (7)

Shear strain (ε ) in the solder joint at L is

e , — L Δ , T (α, - ) inches/inch. (8) h h b c

10

Determination of the thermomechanical strains in the solder fillet.

Referring to FIGURE 5, the solder joint 16, 26 is shown in sche¬ matic detail. Note that, as typically occurs, the height (h) of the solder column 16 is much less than the height (oy) of the solder fillet 26; (h «oy). 15 Within the envelope defined by points o y x (where x depends on the copper pad extension 20 beyond the component 12 and y depends upon the amount of solder used in the fillet 26), the length xy can be defined:

(xy) = ^ x ² + y ² . (9)

20

The origin of the x and y coordinates is at o, located at B relative to the center of the component 12.

Assume that the configuration and dimensions shown in FIGURE 5 are those at a temperature T. which is above room temperature. If the 25 assembly 10 is then cooled through a temperature step Δ T where:

Δ T = (T. - T _Q ), in which T = Room Temperature;

Relative to the component 12 centerline:

30 Initial location of x is (3 + x). (10)

After cooling, the location of x is: x.. = (B + x)(l - Δ Tα, ). (11)

Initial location of point o is B.

After cooling, the location of o is: o., = B(l - Δ Tα ). (12)

By the same process, the location of y will be y ₁ , where y ₁ = y(l - ΔT ). (13) new length from o to x is:

__ _χ ^~ (B + χ)(i - ΔT _b ) - B(l - Δ Tα _c ) x ₁ = x(l - Δ T _b ) - B ΔT(α _b - _c ) . (14)

From (13) and (14) the thermal geometric change in the length xy given in (9) is:

Δ (xy) = ( /x ² + y ² - / + yf } • (15)

Since the solder has cooled, the contraction of the solder if not restrained would be:

solder)

where α is the solder's thermal coefficient of expansion. The change in length of the solder line between x and y can now be defined as e where: e _f = Δ (xy) - Δ (χy) . (solder)

The solder strain ε _* is: ε - ^β f

Substituting from the foregoing relevant equations: v x ^~ 2 + y ( ΔTα - 1) + . y (i ^• ΔT. + (x(l - Δ T _b ) - B Δ T(α _b e, = ' »0» (17)

The expression for a positive temperature step may be obtained in a similar manner.

Discussion

A comparison of the strains defined by Equation (17) and the shear strains defined by Equation (8) in the first part of Analysis 1 shows that the shear strains are more severe when a . b ≠ a c . For the condition when α . D = α c the shear strains evaluated from Equation (8) reduce to zero while those in the solder fillet e- remain finite and are directly proportional to the difference between the thermal coefficients of expansion of the component and the solder, it being common that > α . s c

ANALYSIS 2 An analysis of the action of a strain-relieving layer in absorbing thermomechanical strains in solder joints connecting leadless chip carriers to printed wiring circuit boards.

FIGURE 6 shows the area of the cutaway view in the XY plane of the assembly 10' shown in FIGURE 2, with an intermediate layer 20 of

thickness t introduced between the circuit board substrate 24 and the surface copper circuitry 20, 22. The configuration of the components is that existing after a negative temperature change is applied. The solder fillet is not shown because relief of the shear strains is of primary importance; see Analysis 1. The forces F and F. are the thermal shear and tensile forces exerted on the solder joint by the resilient intermediate layer.

To derive an expression for F„..

L = L(1 - ΔTα ) (18)

L _b = L(l - ΔT _b ) (19)

From which: e = L - L. = L ΔT(α _b - α _c ). (20)

The shear strain (ε ) in the intermediate layer 30 below the solder joint 20, the volume projected on the area (abed) is:

-s - ^r ^m - ^' ⁽²¹⁾

G.A ΔT The shear force is: F _g = -~~- ^~ ( ^α b ~ _c ^ ^ ²² - ⁾

in which G. is the modulus of rigidity of the intermediate layer and A is the horizontal cross-sectional area of the solder joint.

To derive an expression for F... In the volume of the intermediate layer projected on area (adfg) exist two tensile strain components: a mechanical strain due to the deflection e, and a thermal strain due to the difference in the thermal coefficients of expansion of the component 12 and the intermediate layer 30.

The mechanical strain is: = -- e-= ^■ = — Δ-—T (α - ). (23)

L ΔT The thermal strain is: ε „ Δ = — ^~ — (α.1 - αC J

ε ₂ = ΔT (α ₁ - α _< ). (24)

The total strain in the intermediate layer 30 is the sum of ε t ε :

ΔT ε ₁ + ^~ ₂ = — (α _b - _c ) + ΔT (a _χ - α _c ). (25)

From which the force F. can be stated:

( _h - α )

E,A, ΔT ^F t ⁼ ~^ — (2a ₁ + α _b - 3α _c ). (26)

In the foregoing derivation the value of Δ.T (o. - α )» ΔT (α ^" , - α ). Typically, α , = 250 x 10 ^" inches/inch °C, ^~ _h = 15 x 10~ inches/inch °C, and α = 7.0 x 10 ^"6 inches/inch °C. Therefore (α,- α ) = 243 x lθ ^"δ inches/inch °C fi and (α. b-α c ) = 8.0 x 10 ^~ inches/inch °C. It can therefore be seen that the differential thermal deflection between the component and the substrate contri¬ butes little to the tensile joint force being independent of the thermal coefficient of expansion of the layer. The thermal strain in the layer given in Equation (24) is the inextensional thermal strain caused by constraint of the intermediate layer's upper surface by the solder joint. This mechanism is better understood by the following analysis in which the inextensional strains within the volume of consideration are expressed so as to provide an explicit derivation of the origin of the primary tensile forces acting upon the said volume and hence upon the solder joint. The volume of the layer projected on area bcfg is constrained by the solder joint on the upper surface projected on line cf and by the substrate on the bottom surface projected on line bg when a temperature change is applied. The thermal strains in the layer are: Upper surface ε , = ΔT(α ^' - α ) (23a) Lower surface ε = ΔT(α. - a. )

~ f _[_ Mean strain in the layer ε, = ■=•

¹ 2

The average force in the layer F,

E A Δ T ^F l ^{= X} 2 f ^2α l ^{~ (α} b ^{~ α} c ^{) } (25a)}

Since this force is in equilibrium with the constraining forces exerted by the solder joint and the substrate, the solder joint force is expressed by:

^F t ^{= E} 1 ^A 1 ^ΔT ~— .{α , - } .

^{2 l c} (26a)

Note that the relationship between E and G is given by:

^• p

G = m/m ₊ ,, \ , where u is Poisson's Rdtio. (27)

Substituting 2G(1 +M ) for E:

F _t = G ₁ (l + U )A ₁ ΔT(α ₁ - α _c ). (28)

Summing the two forces, from (22) and (28):

(F _s + F _t ) = G _χ ΔT { ^A -fs- ^L (α _b - OL _Q ) + (1 + - α _c )} . (29)

If we put P = { ^A -s≥ ^L - (α _b - a _Q ) + (1 + μ )A _J { ^~ ₁ - a _c )} (2)

then: (F + F _t ) = G _χ Δ TP. (30)

Defining a maximum permissible value of (F 5 + F..) = F, then from (30):

F < G. ΔTP

^G ι ^{≤ (1)}

which, pursuant to the invention, defines the maximum permissible value of the modulus of rigidity of the intermediate layer 30, for an anticipated Δ T temper¬ ature change and limiting maximum force F applied to the solder column. Note that while F consists of both a shear force and a tensile force, they combine to produce a single shear force applied to the joint. To determine the maximum permissible Modulus of Rigidity for the elastomeric layer. The following representative parameter values were selected as discussed above: Δ T = 238°C; A = 1.25 x 10~ ³ in ² ; t = 0.005 in; α = 15 x 10~ ⁶ in/in°C; _c = 7.0 x lθ ^"δ in/in°C; μ = 0.4; A _j = 1.25 x lO ^-4 in ² ; and α _χ = 250 x 10~ ^δ in/in°C. In addition, the following representative values for F and L were determined: L = 0.55 in, for an 84 pad I/O L.C.C.; and F = 1.14 lbs. The F value is considered a conservative judgment based upon empirical data from published slow cycle strain fatigue test curves (R.N. Wild, I.B.M. Doc. # 74Z000481, I.B.M.

Federal Systems Div., Oswego, N.Y., 1975) and the component geometry, i.e., the span (L) between the component geometric center and solder joint geometric center.

Using the foregoing representative values, the maximum permis¬ sible modulus of rigidity can be calculated from Equations (1) and (2). Evalu¬ ating P from (2):

-6

P = 1.142 x 10

Then from (1):

1.14

^G l ^≤ 238 x 1.142 x 10 -6

G _j ≤ 4194 lbs/inch \

And from (27):

E ≤ 2 x 4194(1 + .4)

E < 11744 lbs/inch

Also note the following:

Evaluating F _g from (22) and F _t from (26a):

F = 4194 238 x 1, 1 x 10 ^"6 = 1.098 lbs s

F = 4194 x 238 x 4.2 x 10 -8 = 0.042 lbs

s 1.098

Their ratio: F _t 0.042 = 26.14

This confirms that the primary influence of the intermediate layer is the shear force from that volume below the solder joint, acting upon the solder joint.

ANALYSIS 3

Analysis showing the primary importance of the intermediate layer's modulus of rigidity (G) in comparison with its modulus of elasticity (E) in reducing solder joint stresses. The foregoing Analysis 2 implicitly demonstrates that the modulus of rigidity of the intermediate layer is of far greater importance than the

modulus of elasticity of the intermediate layer in reducing solder joint stresses, even though the two properties are interrelated. Consider that Equation (2) is a compilation of two terms, the first derived via Equation (22) from the modulus of rigidity, and the second derived from the modulus of elasticity via Equation (26a). Evaluating the first term in the range 0.1 ≤ L ≤ 0.8 using the other foregoing representative parameter values:

For L = 0.1, the first term = 0.2 x 10~ ⁶ (31)

For L = 0.8, the first term = 1.6 x 10 ^~6 (32)

Using the same parameter values, the second term has the constant value

-8 4.2 x 10 . Dividing (31) and (32) by the value of the second term yields the respective ratios of 4.76:1 and 38.09:1, indicating that the modulus of rigidity increases in importance relative to that of the modulus of elasticity as the component size increases.

EXAMPLE 1 Testing for Modulus of Rigidity.

The modulus of rigidity of candidate adhesive/elastomer blends, with or without admixture of a dielectric thermally conductive material, can be determined by conventional methods. For example, tensile lap shear specimens of overlapping strips of aluminum are bonded together using an intermediate layer of the candidate resilient material. The bonded specimens are pull tested in a tensile testing machine according to standard industry procedures. A plot of the machine load (P) versus the shear deflection (e) is thereby obtained. By direct measurement the overlap area (A) of the bond and the thickness (t) of the bonding layer are determined. By definition the modulus of rigidity is equal to the shear stress

2 divided by the shear strain. The shear stress is defined by P÷A (lbs/in ); the shear strain by e ÷t (inches/inch). The observed values of P/A can be plotted to a base of e/'t values, and the slope of the line so defined is equal to ^ = G lbs/in ² . (33) EXAMPLE 2

Testing for solder joint shear force F . Selected samples of electrical components are soldered to a Printed Wiring Board having suitable layouts of solder pads on the surface of the circuit board substrate. Such a board is mounted in a suitable holding fixture in such a manner that a shearing force 'P' lbs may be applied to a component of selected size in a direction parallel to the board surface upon which the component is mounted. The resulting shear deflection 'e' inches is measured by conventional methods. By adjusting the force P to the level at which the

deflecting 'e' is an average of the anticipated differential thermal deflection between the component and the substrate, a direct evaluation of the force F acting upon the joint may be made as follows:

If the number of pads on the component = N The anticipated differential thermal deflection = 'e' inches

The force required to produce 'e' = 'P* lbs. p

Then the solder joint force per joint = -ry lbs. (34)

And the anticipated solder joint stress = Pr~- ~ l-b~s~. ^~ s Testing by the methods given in Examples 1 and 2 above may also be performed at the temperature extremes to be expected in the thermal cycle testing. Such testing would permit an estimate of the influence of the resilient layer to be made.

While the present invention has been described in terms of pre- f erred embodiments, one of ordinary skill after reading the foregoing specifi¬ cation will be able to effect various changes, substitutions of equivalents, and other alterations to the compositions and methods set forth herein. It is therefore intended that the protection granted by Letters Patent hereon be limited only by the definition contained in the appended claims and equivalents thereof.