Title:
SUBSTRATE FOR WAFER CONVEYANCE
Document Type and Number:
WIPO Patent Application WO/2022/118468
Kind Code:
A1
Abstract:
A substrate for wafer conveyance is provided for conveying wafers on which multiple chips are formed with multiple integrated elements to be measured. The wafer conveyance substrate is provided with an evacuation hole for creating a vacuum around the wafer mounted on the wafer conveyance substrate, a wafer alignment guide for determining a prescribed position on the wafer mounted on the wafer conveyance substrate, and marks for determining the probe contact position. In this way it is possible not only to perform additional machining on a semiconductor wafer, but also to recognize a specific shot.
Inventors:
TATSUMI SHOKO (JP)
NADA MASAHIRO (JP)
NAKANISHI YASUHIKO (JP)
NADA MASAHIRO (JP)
NAKANISHI YASUHIKO (JP)
Application Number:
PCT/JP2020/045274
Publication Date:
June 09, 2022
Filing Date:
December 04, 2020
Export Citation:
Assignee:
NIPPON TELEGRAPH & TELEPHONE (JP)
International Classes:
H01L21/66; G01R31/26
Foreign References:
| JPS61263123A | 1986-11-21 | |||
| JP2001332490A | 2001-11-30 | |||
| JP2003234392A | 2003-08-22 | |||
| JP2009170730A | 2009-07-30 | |||
| JP2018013806A | 2018-01-25 | |||
| JP2010062405A | 2010-03-18 |
Attorney, Agent or Firm:
TANI & ABE, P.C. (JP)
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