Title:
SUCCESSIVE-APPROXIMATION REGISTER BASED A/D CONVERTER
Document Type and Number:
WIPO Patent Application WO/2023/033103
Kind Code:
A1
Abstract:
A capacitive array D/A converter 110 samples an input voltage IN and outputs a signal corresponding to a threshold voltage VTH based on the input voltage IN and control data ctrl. A comparison circuit 120, responsive to the output of the capacity array D/A converter 110, performs a comparison process in accordance with a comparison clock cmpclk. A clock generation circuit 130 generates a successive-approximation register clock sarclk. A logic circuit 140 supplies the comparison clock cmpclk based on the successive-approximation register clock sarclk to the comparison circuit. The logic circuit 140 makes a determination of normality if the successive-approximation register clock sarclk is detected for a predetermined second number of cycles before an external clock AD16CLK is detected for a predetermined first number of cycles since the start of an A/D conversion operation; if not, the logic circuit 140 makes a determination of abnormality.
Inventors:
NAKAMURA HARUAKI (JP)
Application Number:
PCT/JP2022/032933
Publication Date:
March 09, 2023
Filing Date:
September 01, 2022
Export Citation:
Assignee:
ROHM CO LTD (JP)
International Classes:
H03M1/10; H03M1/46
Foreign References:
| JP2010154441A | 2010-07-08 | |||
| JP2021064873A | 2021-04-22 |
Attorney, Agent or Firm:
MORISHITA Sakaki (JP)
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