Super CMOS (SCMOS ^{1 V1} ) Devices on a Microelectronic System

TECHNICAL FIELD

[001] The present application relates to semiconductor devices and circuit, and more particularly, to analog, digital and mixed signal integrated circuits (ICs) that employ Super Complementary Metal-Oxide-Semiconductor (SCMOS™) devices and thereby exhibit improved device performance due to improvements in power consumption, operating speed, circuit area and device density.

BACKGROUND

[002] Since the introduction of integrated circuits (ICs), engineers have been trying to increase the density of circuits on ICs, which reduces the cost of manufacturing of said ICs. One approach has been to put more components/functionality onto a chip. A second approach has been to build more chips on a larger wafer to reduce IC costs. For example, silicon wafer sizes have grown from averaging 3 inches in diameter in the 1960s to 12 inches today.

[003] Various attempts were tried in the past to improve IC functionality, performance, and cost figures. The early IC implementations were done via the bipolar junction transistors, where layers of various diffusion regions were stacked vertically, and isolated transistor pockets contain the three vital switching terminals, among other R and C circuit elements. Early IC implementations used bipolar junction transistors (BJTs), which have layers of various diffusion regions stacked vertically, and isolated transistor pockets containing the three switching terminals (base, emitter and collector), among other resistive (R) and capacitive (C) circuit elements. However, for the last decade of IC implementations, it was V-I signal and PHY parameter scaling that was used to house more components on a chip.

[004] CMOS technology came after and surpassed BJT technology, which was

relatively bulky, provided poor transistor yield, and exhibited high dc power usage. Device complexity has grown to over billions of circuit elements with Complementary MOS (CMOS) constructs. For more than 30 years a reduction in cost and increase in performance of CMOS technology has been achieved by shrinking the physical dimensions of CMOS transistors. These dimensions have shrunken to a size that is only a few molecular layers thick in critical device parameters. However, further shrinking of CMOS is running against limits imposed by the laws of physics. In addition to trying to manufacture tens of billions of these CMOS circuit elements with "molecular" dimensions, these dramatically smaller circuits operate with very low signal (voltage) levels, making their signal integrity susceptible to noise and causing speed degradation, and or power/heat run-off

[005] Specifically, FIGS. 1A-1D shows the schematics of the physical layout of the basic transistor in BJT and field effect transistors (FETs) or MOS (Metal On Silicon) eras. One can see that the FET is always more compact (by 2: 1 or more) than the BJT. The drawing showed the transistors with minimum number of contacts, therefore it is the smallest device possible. If one measures the transistor dimension with the minimum feature 'F' size (unit of length), the isolated BJT takes 20F ² area versus the MOST 10F ² . Other circuit components, which have more enclosure contacts in layout

implementations, may have more pronounced area difference.

[006] For the last decade of IC implementations, V-I scaling was required in order to house more components on a chip. The device complexity has grown to over billions of circuit elements with Complementary MOS (CMOS) constructs. Still more

complications were added to the devices; the Flash transistors as memory or storage blocks, almost doubled in process and mask steps and also added complicated circuit manipulations.

SUMMARY

[007] The disclosed teachings here in semiconductor process, circuit , component , chip manufacturing and system implementations methods are grouped and classified as the Super CMOS (SCMOS™) technology, which offers significant advantages in

performance, power, cost, reliability and improved system efficiency over the universally used CMOS IC approaches. The SCMOS™ device retains the very high speed of Bipolar Junction Transistor (BJT), without the penalty of high power. The SCMOS™ Circuit Architecture consists of a combination of standard CMOS circuits and a super set of SCMOS Macros (circuits) with the new and simpler sbDTL™, Schottky Barrier Diode Transistor Logic. This Architecture enables a quantum jump in higher performance, lower cost advantages for the foreseeable future.

[008] The application of the SCMOS™ techniques is not only applicable to Crystalline Si devices, , but also includes low cost amorphous Si (A-Si) devices and materials made of A-Si, GeSi, GaAs thin film layers on glass or metal panels. Furthermore, it includes techniques to alter localized crystalline structure variations by oxidation, metal silicidation, ion-implantation, thermal annealing.. etc. to alter localized device physics properties from pure Si crystal. Therefore, SCMOS™ can add value to solar cells and engines. The overall solar energy conversion efficiency can be improved beyond the well known conventional means.

[009] SCMOS™ Technology adds value to ICs such as microprocessors, memory, flash storage, wireless and wired communication; to sub-systems such as hybrid assembly of chips and Printed Circuit Boards; and to Systems such as Computers, Data Centers, Cellular Network (including base stations), Network Switches, Fabric, Routers and Interconnects. In addition SCMOS™ Technology can add value to solar systems and medical systems. Total market potential may grow to fourteen trillion dollars worldwide.

[0010] This application discloses device structures, key process steps and physics

parameters related to super CMOS/SCMOS™ devices. All IC device technologies to date are using transistors as the main circuit element. We propose low threshold Schottky barrier diodes (LtSBD™) and transistor as main elements to implement all IC functions. We build chips in (shallow and deep) Oxide Trench Isolation. SBDs may reside in diffusion, and/or well pockets, and over thin Poly Si film layers. Benefits in PPA efficiency are orders of magnitude better than same with CMOS devices. The process and EDA tools are mostly compatible to existing CMOS processes. We yield the smallest bulk areas for transistors, with SBDs integrated. And use tightest wiring rules (Metal, contact, and vias) in the vertical thin film planes, such that we can improve IC net density with least bulk areas to yield smallest chip sizes. SCMOS™ will keep all progresses in FinFET (3D) technique, and is more cost effective than CMOS. However, SCMOS™ has sweet spots for all 2D transistors from Si-nodes 250 nm down to 20 nm. Our advantages are agnostic to process nodes, always 30-50% better along Power-Delay- Area axis.

[0011] Further, LtSBD™ are added to existing transistor based circuit as basic switching elements or ALMS macro sets for advanced circuit functionalities of the mixed signal IC chips. In analog circuit, SBD can be used for electrostatic discharge (ESD) protection circuit for inputs and outputs (10), power ladder or multipliers, charge pumps, and as resistors in a class-B operational amplifiers. In digital logic circuitry, SBD can be a switch, signal coupler and de-coupler. It is about 3-10 times smaller in size than a transistor switch. It greatly enhanced the net efficiency of switching network with least total nets, and capacitances associated with the bulk, and wiring parasitics. It doubles speed, saves 75% the ac power, and offers zero leakage of the idled diodes. For the synchronous logic gates, SCMOS™ gates offer huge benefits in speed, power, and leakage parameters. High Fanin and Fanout are greater than 50-80% compared with CMOS gates. NAND9, and NOR9 can be realized in one stage logic. For the

asynchronous logic gates, SCMOS™ gate is a draw compared to CMOS for low inputs gates but gain significantly for high Fanin and Fanout gates. SCMOS™ logic gates always have least bulk areas and wiring tracks. It never uses stacked transistors in data/control paths. It always uses single phase clocks, thus circuitry size and wiring traffics are greatly reduced. Connections and congestions are eliminated. In SRAM bit cell and periphery circuitry, it offers significant PPA savings as well. A 4-transistor-2- diode (4T2D) SRAM cell is efficient in cell area 30-40% smaller, and faster for both 2D and 3D implementations. Processors with a embedded memory multiplexer (MUX) network will be a big winner over CMOS same. FPGA will include many efficient SCMOS™ hard macros that gain PPA significantly. 12] Super CMOS/SCMOS™ Devices are powerful candidate to replace CMOS as general microelectronics IC solutions for the Internet of things (IOT) applications. SCMOS™ devices keep all good part of CMOS process and circuits developed in the past 40 years. CMOS are being overly matured and pushed to the wall of nature limits. Continuous shrinking below 20 nm Si-node faces challenges for shrinking the PHY parameters to be near molecular distances. Specifically, the example challenges include cost of fabrication facility and engineering resource to maintain device yield, and new skills to manage process, device, and circuit simulation based on two dimensional (2D) devices to three dimensional (3D) devices. CMOS circuit has inherent weakness in using stacked transistors. It is always bigger than minimum sizes. On the other hand,

SCMOS™ offers new alternatives to improve new device implementations with new ideal switching element, new circuit configuration sbDTL (Schottky Barrier Diode DTL), and introduce new mixed signal solutions with powerful processors and local memories and semiconductor storage entities. These new solutions improve PPA merits of CMOS systems and subsystem components. For the high end applications, SCMOS™ devices offer better efficiency, speed, and low power than CMOS FinFET chips. It allows the 20nm wafers to make SCMOS™ hardware perform better than FinFET at 16 nm. It saves development cost, and time to market now.

[0013] If we apply SCMOS™ to other low end chip sets, we save the manufacturer to use his existing facility and engineers to port SCMOS™ specification, and making new products that exceed older products. Their businesses get a boost in the arm, boom again. This covers all semiconductor chips from 180 nm up to 20 nm Si-nodes. SCMOS™ devices also support large IOT basic applications. As such, SCMOS™ devices not only improve productivity of personal computing systems by providing local memory and storage chips, but cuts down Internet traffics greatly. SCMOS™ systems allow more traffic to go through major trunks of the IC/IT networks.

[0014] Specifically, the present invention relates generally to the Super CMOS

(SCMOS™) semiconductor techniques for making low power, high performance and low cost mixed signal analog, logic, memory, and storage (ALMS) Integrated Circuits (IC, also known as chips) or electronic devices in a microelectronics system, including the methods of designing and manufacturing certain chip sets, modules and PCB (Printed Circuit Board) sub-assemblies. More details have been explained in: (1) U.S. Patent Application No. 12/343,465 (now U.S. Patent No. 8,476,689), titled "Super CMOS Devices on a Microelectronics System," filed on December 23, 2008; (2) U.S. Patent Application No. 6,852,578, titled "Schottky diode static random access memory

(DSRAM) device, a method for making same, and CFET based DTL," filed January 15, 2003; (3) U.S. Patent Application No. 6,590,800, titled "Schottky diode static random access memory (DSRAM) device, a method for making same, and CFET based DTL," filed June 15, 2001; U.S. Patent No. 9,077,340, titled "Super CMOS Devices on a Microelectronics System," filed on June 28, 2013.

(4) an article titled "The Giga Hz 1 Mb Mask programmable ROM chip with SBD array, logic gate, and SRAM cores," published in Proceedings of 10th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), pp.154-158, November, 2010; and (5) U.S. Patent Application No. 4,005,469, titled "P -type-epitaxial-base transistor with base- collector Schottky diode clamp," filed June 20, 1975.

[0015] All circuit and process designs mentioned here are expanded from the SCMOS™ principles and guidelines defined by US pat. 8,476,869. By using powerful core circuit libraries based on the technology described in the above US Patent, we can generate a new series of disruptive IC family of chip sets, Modules and PCB (Printed Circuit Boards whose performance can be up to 100 times faster than the equivalent circuit being used today. These products exhibit the industry's best Performance Over Cost Ratio (POCR).

[0016] In particular, we introduced some exemplary design of macros that can be reused and are scalable for a wide range of ASIC applications including generic computer systems-processors, memory and disk-caching sub-systems, I/O units, hard wired or field programmable assemblies.

[0017] The SCMOS™ technology, and its value proposition, is agnostic to any CMOS Process, whether it be 120 nm, 40 nm, 16 nm, or future nodes such as 10 nm or 7 nm, etc. It is equally applicable to Planar, FinFET and FD-SOI (Fully Depleted Silicon on Insulator) semiconductor processes.

[0018] In 2012, the famous Moore's law of "the number of transistors doubles every 18 months" has run its course. The Industry can no longer shrink the 2 dimension planar transistors as they have done for 50 years. The only way forward is to build, for the first time, 3 dimension transistors called FinFET. By adding a third dimension, the Industry is moving to unknown and risky frontiers of science. There are real questions, such as can one build these 3D structures, can one continue to shrink these 3D structures and offer gains in speed, density and power savings every 2 years as the Industry has done for 50 years? Recent literature states that 3D FinFET promises higher speed and lower power, but for the first time, a new process node will not reduce the cost.

[0019] Our new circuit design innovation, SCMOS™, enables ICs using older

generation process nodes ( 2 to 6 generations older) to outperform even the new FinFET Process Node's speed, power AND CHIP COST. [0020] For the first time in 50 years, part of Moore's Law has reached its limits. The number of transistors per unit area is no longer doubling every 18-24 months. In other words the cost per chip is not going down anymore. The invention of SCMOS™ extends Moore's Law beyond the physical limitations as we know it today. SCMOS™ enables chips using a much older 90 nm process node to compete against chips using the upcoming 65 to 40 nm CFET process node . This has huge benefits to the entire microelectronics industry. SCMOS™ has the potential to supersede almost all, if not all, CMOS chips, much like CMOS superseded BiPolar Circuits over 30 years ago.

[0021] In various embodiments of this invention, SCMOS™ technology is employed to build circuit blocks based on low threshold Schottky Barrier Diodes (LtSBD™s), thereby addressing the above deficiencies and problems associated with an increasing demand for higher semiconductor efficiency and upcoming physical limits on CMOS transistor dimensions. This application teaches manufacturing processes, circuit implementations, and system integration associated with SCMOS™ technology. This application also discusses circuit performance (e.g., power consumption, cost efficiency, device reliability and efficiency) for SCMOS™ technology in view of the conventional CMOS technology. In some implementations, SCMOS™ circuit is solely made of SBDs. Alternatively, in some implementations, SCMOS™ circuit still includes one or more transistors (e.g., BJTs or MOSFETs), and takes advantage of switching speeds of the LtSBD™s or minimum sized MOSFETs, so that to yield huge advantages in IC area, delay, and power consumption reductions simultaneously.

[0022] In some implementations, the SCMOS™ technology is modified from

conventional CMOS technology for the purposes of integrating the LtSBD™s with planar (2-dimensional) or 3D non-planar transistors made by a CMOS™ manufacturing process. Like CMOS technology, the SCMOS™ technology is used to manufacture semiconductor devices on a substrate made of crystalline silicon, amorphous silicon (A- Si), glass, metal panels and the like. The resulting semiconductor devices include on the substrate planar thin films or non-planar structures, each made of different

semiconductor materials or compounds (e.g., A-Si, GeSi, GaAs, Si0 ₂ , Al, Cu, Au and the like). In a specific example, the SCMOS™ technology is modified from CMOS technology used to manufacture a solar cell and engine device. The CMOS technology integrates SBDs on the solar device, and could add value to the solar device by improving the efficiency of solar energy conversion.

[0023] In one aspect, a low threshold voltage integrated circuit is disclosed, comprising a single crystalline silicon, poly-crystalline silicon, or oxide-on-insulator (SOI) substrate, one or more low barrier or high barrier Schottky diodes formed within the substrate, and one or more fixed threshold or variable threshold complementary transistors formed within the substrate, where a respective Schottky diode shares a common terminal with a respective complementary transistor. In some implementations, the one or more Schottky diodes and one or more complementary transistors are formed and interconnected to create one or more macro circuit blocks.

[0024] In another aspect, a low threshold voltage integrated circuit is disclosed,

comprising a substrate, a non-planar fin-type field-effect-transistor (FinFET) structure formed over the substrate comprising one or more fin structures, one or more low barrier or high barrier Schottky diodes formed with the FinFET structure and one or more fixed threshold or variable threshold complementary 3D-transistors formed within the FinFET structure.

[0025] In another aspect, a low threshold voltage integrated circuit is disclosed,

comprising a fully depleted silicon-on-insulator (FD-SOI) substrate, one or more low barrier or high barrier Schottky diodes formed within the substrate, and one or more fixed threshold or variable threshold complementary transistors formed within the substrate.

[0026] In another aspect, a low threshold voltage integrated circuit is disclosed,

comprising a substrate, one or more low barrier or high barrier Schottky diodes formed within the substrate, where the one or more Schottky diodes comprise a mid-band barrier metal or metal silicide, and one or more fixed threshold or variable threshold

complementary transistors formed within the substrate. In some implementations, the mid-band barrier metal or metal silicide comprises one or more of the group consisting of: Ti, Co, Ni, WSi2, CoSi2, NiSi2, TiSi2 and TaSi2.

[0027] In some implementations, the integrated circuits include a 4T2D-SRAM™ macro circuit block including four complementary transistors and two Schottky barrier diodes. [0028] In some implementations, the one or more Schottky diodes and one or more complementary transistors are formed and interconnected to create one or more macro circuit blocks. In some implementations, the integrated circuits further comprise poly- silicon film resistors, diffused ion-implanted pockets, capacitors and metal wiring tracks to interconnect with the one or more Schottky diodes and one or more complementary 2D-transistors to deliver specific analog, logic, memory, storage (ALMS) and timing control macro functions.

[0029] In some implementations, at least one macro circuit block is from the group of RF, analog and digital circuit blocks consisting of: a hardwired or field programmable memory device, a timing detector, a phase detector, an audio signal detector, a video signal detector, a text signal detector, a wireless signal detector, a rectifier, a decoder, a mixer, a multiplexer, a multiplication and divider, a signal filter, a separator, a charge pump, a delay element, a circulator, a phase splitter, a frequency synthesizer, a phase locker, a D-type flip flop register, a latch, an inverter, a buffer, a counter, a demultiplexer, an encoder, an adder, a phase coupler and a comparator.

[0030] Various advantages of the disclosed technology will be apparent in light of the descriptions below.

BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The aforementioned features and advantages of the disclosure as well as

additional features and advantages thereof will be more clearly understood hereinafter as a result of a detailed description of preferred embodiments when taken in conjunction with the drawings.

[0032] To illustrate the technical solutions according to the embodiments of the present disclosure more clearly, the accompanying drawings needed for the embodiments are introduced briefly in the following. The appended drawings, however, merely illustrate the more pertinent features of the present disclosure and are therefore not to be considered limiting, for the description may admit to other effective features.

[0033] FIG. 1A is a top view of a bipolar junction transistor (BJT) that is manufactured on a semiconductor substrate in accordance with some implementations of the application. [0034] FIG. IB is a cross sectional view of BJT along a A-A' line in accordance with some implementations of the application.

[0035] FIG. 1C is a top view of a metal-oxide-semiconductor field effect transistor

(MOSFET) that is manufactured on a semiconductor substrate in accordance with some implementations of the application.

[0036] FIG. ID is a cross sectional view of MOSFET along a B-B' line in accordance with some implementations of the application.

[0037] FIG. IE is a top view of a low threshold Schottky barrier diode (LtSBD™) that is manufactured in the N-well region of the P-type semiconductor substrate for ESD input protection. Like wise, there is P-type LtSBD™ for ESD protection in the P-well region (not shown in figure). Besides ESD protections, the N-well and P-well LtSBD™ pair may be used in input filters as RF signal amplifiers to render high-speed microwave communications on a P-type semiconductor substrate in accordance with some implementations of the application.

[0038] FIG. IF is a cross-sectional view of LtSBD™ along a C-C line in accordance with some implementations of the application.

[0039] FIG. 1 G illustrates a N-type LtSBD™ device and a N-type MOSFET device (NMOS) are integrated in the drain diffusion region associated with a drain of NMOS device in accordance some embodiments of the application.

[0040] FIG. 1H illustrates a P-type LtSBD™ device and a P-type MOSFET device

(PMOS) are integrated in the drain diffusion region associated with a drain of PMOS device in accordance some embodiments of the application.

[0041] FIG. II illustrates a flow chart of a manufacturing process that completes the 4T2D SRAM™ bit-cell wiring, in accordance with some implementations of the application.

[0042] FIG. 1J-1P are cross-sectional views of a planar FET and one or more LtSBD™s that are integrated on a substrate in accordance with some implementations of the application. [0043] FIG. 2A is an isometric view of a FinFET device in accordance with some implementations of the application, and FIG. 2B is a cross sectional view of FinFET device along a D-D' line in accordance with some implementations of the application.

[0044] FIG. 2C illustrates a N-type FinFET that is integrated with a single-terminal N- type LtSBD™ on the same substrate in accordance with some implementations of the application.

[0045] FIG. 2D illustrates a P-type FinFET that is integrated with a single-terminal P- type LtSBD™on the same substrate in accordance with some implementations of the application.

[0046] FIGS. 3A and 3B illustrate two exemplary SCMOS™ synchronous logic gates (e.g., a 4-input NOR gate and a 4-input NAND gate) in accordance with some implementations of the application.

[0047] FIG. 3C illustrates a circuit diagram for an inverter in accordance with some implementations of the application.

[0048] FIG. 3D is a circuit diagram for an asynchronous 6-Input NAND Gate with 4X drive in accordance with some embodiments.

[0049] FIG. 3E is a circuit diagram for an asynchronous 6-Input NOR Gate with 4X drive in accordance with some embodiments.

[0050] FIG. 3F is a circuit diagram for an asynchronous 4 to 1 Multiplexer with 2 X drive in accordance with some embodiments.

[0051] FIG 3G shows a SCMOS™ 4T2D-SRAM™ Cell Layout at Si-28 nm.

[0052] FIG. 3H compares propation delays associated with precharge low of

synchronous NAND Gates that are implemented based on SCMOS™ and CMOS technologies, respectively.

[0053] FIG. 31 compares propation both high-to-law and low-to-high propagation delays of asynchronous NAND Gates that are implemented based on SCMOS™ and CMOS technologies, respectively. [0054] FIGS. 4A, 4 A' and 4B illustrate circuit diagrams of SCMOS ^1M bit cell and a conventional CMOS bit cell in a static random access memory (SRAM) array in accordance with some implementations of the application, respectively. In Fig. 4A', the bit cell configuration exchanges N-type SBDs with P-Type SBDs and both diodes are integrated with the P-transistors and have cathodes connected to the bit lines.

[0055] FIGS. 4C and 4D illustrate exemplary layout schematics corresponding to bit cells 500 and 550 in accordance some embodiments of the application, respectively.

[0056] FIGS. 4E and 4F illustrates two exemplary memory array controllers 582 and 584 that are configured to drive SCMOS™ bit cell and CMOS bit cell in a SRAM array in accordance with some implementations of the application, respectively.

[0057] FIG. 4G illustrates a block diagram of a simplified SRAM module for reading data from bit cells of a SRAM column in accordance with some implementations of the application.

[0058] FIG. 4H illustrates an exemplary write circuit for a bit cell in accordance with some implementations of the application.

[0059] FIG.4I illustrates an exemplary SCMOS™ dual port SRAM (DPSRAM) bit-cell in accordance with some implementations of the application.

[0060] FIGS. 4J and 4K illustrate layout schematics of two exemplary DPSRAM bit-cell 560 without and with the decoupling SBD pair (D17 and D18) in accordance with some implementations of the application, respectively.

[0061] FIGS. 4L, 4M and 4N are circuit diagram for 6T or 8T DPSRAM cells in prior art.

[0062] FIG. 40 is a circuit diagram of a SCMOS™ dual port SRAM (DPSRAM) array cell in accordance with some implementations of the application.

[0063] FIG. 5A illustrates a block diagram of an exemplary Mask-programmable Readonly Non- Volatile Memory (NV-SMROM™) 900 in accordance with some

implementations of the application. [0064] FIG. 5B illustrates a layout schematic of part of a NVMROM array in accordance with some implementations of the application.

[0065] FIGS. 5C and 5D illustrate a pair of inter-digitized NOR64 decoder gates 9042 and 9062 of the NVMROM™ implementation. It shows the combined 64 WL decoder and drivers have the perfect pitch of 2F. The layout can be easily extended to NOR10 decoders for 1024 WLs in accordance with some implementations of the application, respectively.

[0066] FIGS. 5E and 5F illustrate a NOR10 row address buffer and a NAND 10 column address buffer 9064 for the NVMROM™ design. This design supports fastest and lowest cost NVMROM™ I n the world that runs at GHZ speed and array density is 4F ² /bit. in accordance with some implementations of the application, respectively.

[0067] FIG. 5G illustrates the core schematic block diagram of the GHz 1Mb

NVMROM™ from WL and BL decoders to Sense Amp out in accordance with some implementations of the application.

[0068] FIG. 5H illustrates time diagrams of seven signals of MROM in accordance with some implementations of the invention.

[0069] FIGS. 6A and 6B illustrate two exemplary I-V curves for Ht and LtSBD™s of various contact metals since 1972, together with its theoretical forward and reverse I-V data points and models, and background concentration profiles in accordance with some implementations of the application.

[0070] FIGS. 6C and 6D show area comparison between the bit cells of SCMOS™

4T2D twin word line (TWL) SRAM and the CMOS 6T-SRAM implementations in accordance with some implementations of the application.

[0071] FIGS. 7A-7E illustrate FPGA and Flash blocks and corresponding wiring

schemes in a PCB/module/chip environment implemented in SCMOS™ technology in accordance with some implementations of the application.

[0072] FIGS. 7F-7H illustrate building blocks of FPGA chips with various SCMOS library Mux, SRAM, NV MROM, and Standard Cells hardwired macros in accordance with some implementations of the application.

[0073] FIG. 8A illustrates a major IC circuit innovations orthogonal to the process and signal scaling trend over the past five decades.

[0074] FIG. 8B illustrates performance matrices of SCMOS™ and CMOS IC based on system speed, area, power saving, and cost advantages of the SCMOS™ over the CMOS technology and chips.

[0075] FIGS. 9A and 9B illustrate power consumption sources of a CMOS state-of-the- arts cell phone chip set system.

[0076] FIGS. 10A and 10B compare the performance gaps between various on chip functional units that hinder low power and compact integration.

[0077] FIGS. 11 A-1 ID illustrate the RFID circuit implementation comparison between MOS transistor based (0.8V PN junction) diode rectifier and the LtSBD™ based (0.1V) rectifiers in accordance with some implementations of the application.

[0078] FIGS. 1 IE and 1 IF illustrate on chip charge pump chain or voltage multiplier or voltage rectifier that are made of the Ht or LtSBD™ and capacitor ladders in accordance with some implementations of the application.

[0079] FIGS. 12A-12D describes a PLL and frequency multiplier implementation using SCL™ macros in accordance with some implementations of the application.

[0080] FIG. 13 illustrates a Controller for DRAM SIMM and corresponding

performance in accordance with some implementations of the application. .

[0081] Like reference numerals refer to corresponding parts throughout the several views of the drawings.

DESCRIPTION OF EMBODIMENTS

[0082] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the subject matter presented herein. But it will be apparent to one skilled in the art that the subject matter may be practiced or designed without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the embodiments.

Trademarks designated herein with the "TM" symbol are the property of Schottky LSI, Inc.

[0083] The technical solution of the present disclosure will be clearly and completely described in the following with reference to the accompanying drawings. It is obvious that the embodiments to be described are examples and only a part rather than all of the embodiments of the present disclosure. All other embodiments obtained by persons skilled in the art based on the described embodiments of the present disclosure shall fall within the protection scope of the present disclosure.

[0084] A low cost IC solution is disclosed in accordance with embodiments to provide Super CMOS microelectronics macros. Hereinafter, the Super CMOS or Schottky CMOS all refer to SCMOS™. The SCMOS™ device solutions divide into process means, and an orthogonal circuit means. In process means, we build a niche circuit element, the complementary low threshold Schottky barrier diodes (SBD) made by selected metal barrier contacts (e.g., Co/Ti) at the surface of P- and N- Si beds of the CMOS transistors. In circuit means, we build DTL like new circuit topology for digital gates and designed a broad range of ASIC product library macros, which used the integrated SBD and transistors (BJT, CMOS, and Flash versions) as basic components. The macros are logic gates, SRAM, DRAM, NV MROM, Flash Memory, and FPGA. Collectively they support processors, embedded memory, IO SSD, and MUX units for the best microelectronics implementation of SCMOS™ computing engines.

[0085] SCMOS™ will be a unique answer for the IC and IT industry after CMOS

Moore's law stopped in 2012 at the Si-20 nm node. It offers new circuit innovations and revives new hardware constructs and software integration with a different architecture, and start implementations with easier design rules than deep nano-meter. It shall overhaul CMOS IC/IT products with a face lift and extend forward and backward for Si product spinning range from Si-nodes 16 to 250 nm. Besides Internet computers, SCMOS™ may create new product surge into two emerging fields; Solar photon voltaic electricity conversion and bio-lab-on-a-chip, marching towards a fourteen trillion dollar IOT market cap in the next 2 decades.

[0086] The Super CMOS (SCMOS™) technology disclosed herein, and its value

proposition, is agnostic to any CMOS process, (e.g., 120 nm, 40 nm, 16 nm, etc.). It is equally applicable to transistors and substrates that are planar, polysilicon, FinFET and FD-SOI (Fully Depleted Silicon on Insulator) semiconductor processes.

[0087] The present disclosure relates generally to SCMOS™ implementations of low power and mixed signal analog, logic, memory, and storage (ALMS) devices in a microelectronics system environment, including novel methods of designing (process and device profile simulations, design rule layout checks, Verilog logic synthesis, and SPICE circuit simulations, macro place and route checks, etc.), and manufacturing (process and equipment means) to make the most competitive IT products, such as chip sets, modules, and PCB sub-assemblies.

[0088] In various embodiments of this application, low threshold and high threshold Schottky Barrier diodes are incorporated in a new family of integrated circuit chips as the best microelectronics implementations to form the lowest power consumption, highest compactness, and highest speed in device hardware solutions. When utilized with CFET, the new series of IC chips are based on the newly invented SCMOS™ technology platform, and CMOS compatible SCMOS™ EDA tools are re-developed for users designing SCMOS™ chip series with wide analog-logic-memory-storage(ALMS) reusable macro functional blocks. The SCMOS™ construct is basically process compatible with CMOS but has simplified structures and super efficient circuit configuration, and has performance matrices 100s fold better than the CMOS same. SCMOS™ is 100% compatible with CMOS but cost much less to manufacture its parts using less aggressive design rules. General rule of thumb in design is 2 Si

technologynode better than the CMOS arts.

[0089] Using SCMOS™ EDA tools will enable system users extend Moore's law

making better component solutions in a new performance track. Significant performance and cost controls are achieved via these circuit design innovations. This is the only alternative other than deep nm process parameter and signal scaling via the current

CMOS device approach, which is hitting the wall at 16 nm Si process node with the 3D transistors. The stiff barrier on deep nano-meter process shrinking faces strong resistance due to performance saturation and molecular PHY layer process control yield limitations. The SCMOS™ device solution alternative offers breakthrough in both fronts. It created new market space, where performance jump can be delivered by foundry lines with much less expensive equipment and facilities.

[0090] The present disclosure describes several implementations of integrated circuits incorporating low voltage threshold and high voltage threshold Schottky Barrier Diodes with CMOS technology (SCMOS™). SCMOS technology allows for circuits with lower power consumption, smaller area and higher speed than their CMOS counterparts.

SCMOS™ technology is compatible with a variety of substrates, two-dimensional or three-dimensional, such as single silicon, polysilicon, FinFET or FD-SOI. SCMOS™ technology can be used to form macro circuit blocks including FPGA's, memory cells, analog circuits and digital circuits. SCMOS™ technology offers ease of manufacturing using existing CMOS foundry processes.

[0091] The present invention relates generally to the SCMOS™ implementations of the low power and mixed signal analog, logic, memory, and storage (ALMS) devices in a microelectronics system environment, including the novel methods of designing

(software and circuit means) , manufacturing (process and equipment means) to make the most competitive IT products; certain chip sets, module, and PCB sub-assemblies.

[0092] The following description is presented to enable one of ordinary skilled in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the preferred embodiment and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the present invention is not intended to be limited to the embodiment shown but is to be accorded the widest scope consistent with the principles and features described herein.

[0093] FIG. 1A is a top view of a bipolar junction transistor (BJT) 100 that is

manufactured on a semiconductor substrate in accordance with some implementations of the application, and FIG. IB is a cross sectional view of BJT 100 along a A-A' line in accordance with some implementations of the application. BJT 100 includes contacts of a collector (C), two base (B), and an emitter (E), each having a respective doping concentration. When the collector, base and emitter are biased according a predetermined BJT biasing condition, carriers flow vertically (e.g., holes or electrons) from the emitter are emitted from the emitter, pass the thin base region, and collected by the sub-collector. Thus, a based current injected to the base is amplified to a collector current by an amplification coefficient. BJT 100 was used as digital switch and also widely applied in analog circuit to provide amplification to electrical signals.

[0094] FIG. 1C is a top view of a metal-oxide-semiconductor field effect transistor

(MOSFET) 150 that is manufactured on a semiconductor substrate in accordance with some implementations of the application, and FIG. ID is a cross sectional view of MOSFET 150 along a B-B' line in accordance with some implementations of the application. MOSFET 150 includes a gate (G), a source (S) and a drain (D) contact terminals. When a gate-to-source voltage and a drain-to-source voltage are properly applied, a channel is formed between the source and the drain, and a current (I _ds ) flows near the surface laterally in the channel region between the source and the drain. In accordance with the magnitudes of the gate-to-source and drain-to-source voltages, MOSFET 150 functions in a linear region or a saturation region. Since its introduction into the semiconductor industry, MOSFET 150 has been widely applied in both analog and digital circuit.

Well Schottky Barrier Diode

[0095] FIG. IE is a top view of a low threshold Schottky barrier diode (LtSBD™) 180 that is manufactured on a P-type semiconductor substrate in accordance with some implementations of the application, and FIG. IF is a cross-sectional view of LtSBD™ 180 along a C-C line in accordance with some implementations of the application.

LtSBD™ 180 includes a barrier metal 182, a doped semiconductor well 104 and a Schottky diode silicide layer 186 at the interface of barrier metal 182 and N-type semiconductor well 104. In some implementations, the doped semiconductor well of LtSBD™ 180 is formed in an epitaxial layer on the semiconductor substrate and isolated by a doped isolation ring. When a current flows through the diode junction, there is a small voltage drop across the diode terminals. A conventional silicon diode formed between p-type and n-type semiconductor materials has a voltage drop of 0.7-0.8 volts across its junction; however, the voltage drop for the silicide between barrier metal 182 and doped semiconductor well 104 in LtSBD™180 is between 0.15-0.3 volts. Such a voltage drop results in higher switching speed and better system efficiency for LtSBD 180 as a RF input diode at the 10 block.

[0096] In some implementations, SBDs may be integrated in the extended area of the transistor drain bed, barrier metal 182 is selected from a material group that consists of molybdenum, platinum, chromium or tungsten, making silicides (e.g., palladium silicide and platinum silicide, Co silicide, or Ni silicide), and the like. Optionally, doped semiconductor well 104, or lightly doped drain region is made of n-type silicon.

Therefore, in some implementations such as in FIG. 1G, barrier metal silicide 182 and n- type semiconductor drain 104. Or silicide 182 A in the N- region 104 A act as the anode and the cathode of LtSBD™ 180, or LtSBD™ 180A, respectively. Alternatively, in some implementations such as in FIG. 1H, when a proper metal material and a proper doping concentration are selected for barrier metal 182 and p- type semiconductor drain 104B, they would act as the cathode and the anode of the P-type LtSBD™ 180 in the P- drain region, or the P-type LtSBD™ 180B, respectively. In all cases, The silicide with lightly doped Si form rectifying SBD, The heavily doped Si terminal is the common anodes of the P-type LtSBD™ 180B, or the common cathodes of the N-type LtSBD™ 180A. Furthermore, the common terminal is also the drain terminal of the respective N- FET150A, or P-FET150B. The LtSBD rectifying effect at the drain terminal is suppressed but showing Ohmic property.

[0097] As shown in FIGS. 1A-1F, semiconductor devices 100, 150 and 180 are two- dimensional (2D) thin- film devices (sometimes called planar devices) manufactured on the surface of their respective semiconductor substrate. It is also noted that that

MOSFET 150 is more compact (e.g., by a factor of 2: 1 or more) than the BJT 100, and that diode 180 is even more compact than MOSFET 150. In a specific example, each transistor in FIGS. 1A-1H includes a minimum number of contacts (e.g., one for each terminal) allowed by a certain semiconductor manufacturing process, and has a smallest device size that could be accomplished under the corresponding technology. In this example, the sizes of devices 100, 150 and 180 are measured with a preferred feature size F (e.g., a minimum feature size), and BJT 100, MOSFET 150 and diode 180 have sizes of 24F ² , 12F ² and 4F ² , respectively. If used in circuit components, BJT based circuit and MOSFET based circuit have to include more electrical contacts than the SBD in their respective layout implementations, and thus, could have more pronounced area differences.

[0098] FIG. II illustrates a flow chart of a manufacturing process that produces a

LtSBD™ 180 in accordance with some implementations of the application. An old Damascene scheme is applied to make midland metal SBDs on Si diffusion beds, and connect it to the top of a silicided poly-silicon film. As such, the sizes of various circuit blocks (e.g., 4T2D-SRAM™ bit cell and other structures) could be reduced.

Diffusion Bed LtSBDs

[0099] In some implementations of this application, LtSBD™ 180 is used to obtain the same functions that transistors 100 and 150 could provide, and such diode based circuit has a better form factor (e.g., a smaller chip area) than the corresponding BJT or MOSFET based circuit.

[00100] In various embodiments of the application, LtSBD™ 180 may integrate with other semiconductor devices (e.g., BJTs and MOSFETs) to create complicated digital, analog and mixed-signal circuit. LtSBD™ 180 is used to serves miscellaneous functions in such circuit. Optionally, LtSBD™ 180 is used as a small logic switching element, a load resistor in analog signal amplifier having a high Gm parameter (ΔΙ/AV), or as a signal coupler or a signal decoupler. In some implementations, LtSBD™ 180 is also used as a Non- Volatile Read Only Memory (NVROM) bit cell to store a data bit. Compared with a transistor based NVROM bit cell, the LtSBD™ based NVROM bit cell occupies a smaller area (e.g., 4F ² ), and allows a higher memory density. Due to LtSBD™'s low turn-on voltage and small parasitic capacitance, the LtSBD™ based NVROM bit cell could be accessed with a faster rate (e.g., 1-10 GHz) than many transistor based

NVROM bit cells manufactured from similar CMOS technology using P-N junction diodes. More details on LtSBD™ based NVROM bit cells are explained below with reference to FIGS. 5B-5H.

[00101] FIG. 1G (SCMOS™ LtSBD™ and CFET structures for Si-55 nm node)

illustrates a N-type LtSBD device 180A and a N-type MOSFET device 150A (NMOS) are integrated in the drain diffusion region associated with a drain of NMOS device 150A in accordance some embodiments of the application, and FIG. 1H (SCMOS™ LtSBD™ CFET structures for Si-55 nm node) illustrates a P-type LtSBD™ device 180B and a P-type MOSFET device (PMOS) 150B are integrated in the drain diffusion region associated with a drain of PMOS device 15 OB in accordance some embodiments of the application. Here, NMOS device 150A has a n-type drain region 102A that has a high doping concentration, and LtSBD™ device 180A also has a lightly doped n-type cathode region 104A in parallel with a heavily doped sub-implanted region, which effectively lowered the cathode body resistance. Likewise, PMOS device 150B has a p-type drain region 102B that has a high doping concentration, and LtSBD device 180B has a lightly doped p-type anode region 104A which includes a P+ sub-implant region for reducing the anode body resistance of the P-LtSBD 180B.

[00102] In some implementations not shown in FIG. 1G, NMOS device 150A and

LtSBD™ device 180A are located separately on two distinct areas of the semiconductor substrate. Drain region 102A of NMOS device 150A and cathode terminal 102A of the N-LtSBD™ device 180A are electrically coupled to each other via an interconnect wire. Further, in some implementations, drain region 102A of NMOS device 150A is not coupled to any other device except LtSBD™ device 180A, and therefore, another contact access 108 A could be saved. Therefore, when LtSBD™ device 180A and NMOS device 150A are electrically coupled on the same substrate, the chip area is saved not only for using LtSBD™ device 180A that has a relatively small size, but also for avoiding the use of first contact access 106A, second contact access 102A can be combined.

[00103] Similarly, when LtSBD™ device 180B and PMOS device 150B are electrically coupled on the same substrate, p-type drain region 102B of PMOS device 150B and anode region 102B of LtSBD™ device 180B are combined. In particular, drain region 102B and anode region 102B are optionally coupled by an interconnect wire or combined. As explained above with reference to FIG. 1G, in some implementations, the chip area is saved not only for using LtSBD™ device 180B that has a relatively small size, but also sharing SBD and FET contacts and eliminating wirings.

[00104] Stated another way, cathode region 104A of N-LtSBD™ device 180A is

extended to encompass drain region 102A of NMOS device 150A, and anode region 104B of P-LtSBD™ device 180B is extended to encompass drain region 102B of NMOS device 150B.

[00105] In some implementations, PMOS and NMOS transistors 150 are flash transistors that are used in single-level cell (SLC) or multi-level cells (MLC), and optionally include floating gates. In a specific example, the gate oxide is a layer of tunnel oxide that has an approximate thickness of lOnm or less.

[00106] Generally, in some implementations, LtSBD™ device 180 (e.g., device 180A or 180B) is added adjacent to on a diffusion bed of an integrated transistor (e.g., NMOS device 150A or PMOS device 150B). Optionally, the integrated transistor is selected from a group consisting of a MOSFET device 150, a GaAs based transistor, a SiGe based transistor or a Flash transistor. During the course of manufacturing the integrated transistor, the diffusion bed of the integrated transistor is extended to encompass one or more LtSBD™ devices; 180, 180A, 180B. In some implementations, LtSBD™ 180 uses mid band barrier metal silicides (e.g., Co, TiW and Ni) that are oftentimes used as the source/drain (S/D) contacts of the integrated transistor as well. However, the regions lying underneath the silicides are distinct, and specifically, are lightly doped

semiconductor well 104, 104A, 104B or highly doped drain 102A, 102B for LtSBD device 180 and the integrated transistor, respectively. The barrier metal silicide area of LtSBD™ 180 is substantially covered and surrounded by insulating dielectrics formed on top of the semiconductor surface, and the distance between LtSBD™ 's contacts to its anode and cathode (i.e., the width x of the insulating dielectrics in FIG. IF) is limited by the photolithographical techniques applied in the corresponding manufacturing process.

[00107] Alternatively, in some implementations, the silicide area has a thickness of 300 A, and is surrounded by oxide on three of its four sides and a buffer space SABS on the fourth side. In a specific example, we desire to keep a lightly doped tail region from surface down to 600 A, then to see heavily implanted P+/N+ region with sheet resistance of 50-500 ohm/square or less for N/P body-resistors of the N/P LtSBD™. Peak concentration is Ixl0 ¹⁶ -7xl0 ¹⁶ cm ^"3 . In some implementations, semiconductor well LtSBD™ device 180 has a concentration that is approximately 10 ¹⁶ cm ^"3 , and drain region 102 of integrated transistor 150 has a doping concentration that is approximately 10 ²⁰ cm ^"3 . Upon direct contact, drain region 102 of the integrated transistor 150 become an Ohmic contact with semiconductor well 104 of LtSBD™ device 180. Therefore, when LtSBD™s are integrated into the integrated transistor's drain bed, each LtSBD™ 180A or 180B only needs a single anode or cathode terminal, and shares a common cathode or anode with a drain terminal of the integrated transistor, respectively. [00108] The positions of drain region 102 of integrated transistor 150 and LtSBD sub- implant regions are used to control vertical and lateral doping profiles of LtSBD™ device 180. The body resistance between the LtSBD™ terminals 106 and 110 is thereby adjusted by sub-implant doping profiles. As such, LtSBD™ device 180 is substantially compatible with the conventional CMOS technology used to manufacture integrated transistor 150, except that under some circumstances, the integration of LtSBD™s 180 and transistors 150 needs minor modification of the sub-implant options.

[00109] In some implementations, LtSBD™ barrier metal 182 is selected from Co/Ni silicide, Er and TiN. Further, in some implementations, the LtSBD™ is made on a polysilicon thin film layer.

[00110] Further, FIGS. 1J - IP are cross-sectional views of a planar FET and one or more LtSBD™s that are integrated on a substrate in accordance with some implementations of the application. As shown in FIGS. 1J and IK (SCMOS™ LtSBD™ and CFET structures for Si-55 nm node Process option based on SASB mask - P02), the drain region of a transistor (e.g., PMOS transistor in FIG. 1J or NMOS transistor in FIG. IK) is associated with a diffusion bed that includes a common SBD terminal. The LtSBD™s only require a single terminal per channel. Further, as shown in FIGS. 1L and 1M (SCMOS™ LtSBD™ and CFET structures for Si-55 nm node Process option based on Damescene M0 mask - POl), the substrate that includes the transistor and the LtSBD™s is further covered by a first layer of metal. In accordance with design rules for Si-55nm technology node, the metal layer is patterned to form interconnects to the source of the transistor and the SBD terminal.

[00111] As shown in FIG. IN (SCMOS™ LtSBD™ and CFET structures for Si-55 nm node P+ and N+ Buried Contacts of Polysilicon to Diffusion Tubs Specification), in some implementations, a poly-silicon film is deposited over the diffusion pocket, and make direct contact. Optionally, the poly- silicon film is doped by N+ or P+ atoms. Gate oxide is removed by sacrificial etching to enable a smaller bit-cell dimension. Also, as shown in FIGS. 10 and IP (SCMOS™ LtSBD™ and CFET structures for Si-55 nm node P+ and N+ Buried Contacts of Polysilicon and Damescene M0 to Diffusion Tubs - POl), transistors and LtSBD™s are coupled in an O-metal wiring scheme with

Damascene connection, and thereby form 4T2D-SRAM™ bit-cells. [00112] As such, FIGS. 1G, 1H, 1J, 1L, IK, 1M, IN, 10 and IP show optional CLtSBD structures (mask flows) for the 4T2D-SRAM™ bit-cell layout. In some implementations, buried contact layers are used between doped thin poly-Si (-1000 Ang thick) to N- pocket (BPCN) and doped thin poly-Si to P- pocket (BPCP). In some implementations, NiSi is used for the CLtSBD™ P/N type buried contact and the S/D ohmic contact. In some implementations, Damascene structures are used to make CoSi CLtSBDV and connect the SBDs to the Poly-Si top layer of metal silicide. Such implementations would result 25 to 35% of array core size reduction for

the 4T2D-SRAM™ bit-cell areas compared to the CMOS 6T bit-cells. The speed and power advantages are also obtained accordingly.

Integration with Non-Planar Transistors (e.g., FinFET)

[00113] FIG. 2A is an isometric view of a FinFET device 200 in accordance with some implementations of the application, and FIG. 2B is a cross sectional view of FinFET device 200 along a D-D' line in accordance with some implementations of the application. FinFET device 200 is a non-planar and double-Fin transistor built on a silicon-on-insulator (SOI) substrate. Gate 202 is configured to wrap around a conducting channel formed between a source 204 and a drain 206 and provide better control over a current flowing through the conducting channel. Unlike MOSFET 150, the gate of FinFET 200 has an effective gate width of 2H _gat e+W, where H _gat e and W are the actual height and actual width (thickness) of the Fin, respectively. The gate dielectric 208 is optionally a layer of silicon oxide or a layer of high-k dielectric material that has a higher dielectric constant than silicon oxide. Exemplary gate dielectrics include, but are not limited to, oxynitride and hafnium-based dielectrics (e.g., nitrided hafnium silicates HfSiON). Further, FinFET 200 includes fully depleted source and drain beds 204 and 206 each optionally including a stacked epitaxial region. In one example, source 204 or drain 206 includes a stacked epitaxial silicon (Si) and germanium silicon (GeSi) region grown on a shallow silicon substrate, and the respective epitaxial region is formed by sputtering or chemical vapor deposition that enables in-situ doping concentration control over source 204 or drain 206. In some implementations, the epitaxial regions of source 204 and drain 206 have a tapered shape to reduce their respective capacitance with respect to gate 202. [00114] In general, leakage current in a conducting channel increases as transistor gate lengths decrease. However, FinFET 200 keeps gate 202 in closer proximity to the whole channel for the purposes of controlling short-channel effects and suppressing leakage. As such, the three-dimensional (3D) or non-planar structure of FinFET 200 enables the use of smaller gate area with short channel CFET transistors, while maintaining desirable switching speeds and power consumption. In some implementations, FinFET 200 is applied in place of a conventional MOSFET device in an analog, digital and mixed- signal circuit component as disclosed in any of the U.S. Patent Nos. 8,476,689;

6,852,578; and 6,590,800; each of which is incorporated by reference in its entirety. Specifically, FinFET 200 could be used to form a logic gate, a flip flop, a memory cell, a frequency synthesizer, a Schmitt trigger, a voltage rectifier and many other analog, digital and mixed-signal circuits.

[00115] In some implementations, the SOI substrate includes a plurality of faceted S/D islands to contain integrated LtSBD™s. Optionally, a non-planar FinFET includes a single fin, and is coupled to a single contact SBD switch. As such, the switching speed of the resulting circuit block is improved.

[00116] FIG. 2C illustrates a N-type FinFET 200 A that is integrated with a single- terminal N-type LtSBD™ 180C on the same substrate in accordance with some implementations of the application, and FIG. 2D illustrates a P-type FinFET 200B that is integrated with a single-terminal P-type LtSBD 180D on the same substrate in accordance with some implementations of the application. N-type LtSBD™ 180C includes a n-type doped diffusion bed 104C, and p-type LtSBD™ 180D includes a P- type doped diffusion bed 104D. In some implementations, LtSBD™s 180C and 180D are integrated on the surface layer of the stacked drain regions of FinFETs 200A and 200B, respectively, and therefore, LtSBD™s 180C and 180D are located adjacent to the FinFET sharing drain contacts. Optionally, each of LtSBD™s 180 and FinFET 200 is surrounded by oxide sidewalls, and separated from the semiconductor substrate by a BOX layer 220. BOX layer 220 is made of dielectric material, e.g., silicon oxide. We can place the LtSBD™s to the FinFET technology in the similar way as in planar CFET technology with Oxide defined drain walls, SABS, BOX in the drain bottom, FD channel regions with sub-implanted low value SBD body resistance. Single FinFET 200A has a n-type drain region 206A that has a high doping concentration, and LtSBD™ device 180C also has a n- cathode region 21 OA, and N+ sub-implant region (all within diffusion bed 104C). In some implementations not shownin

FIG. 2C, FinFET 200A and LtSBD™ device 180C are located separately on two distinct areas of the semiconductor substrate. Drain region 206 A of FinFET 200 A and cathode region 21 OA of LtSBD™ device 180C are electrically coupled to each other via an interconnect wire. Alternatively, in some implementations as shown in

FIG. 2D, FinFET 200B and LtSBD™ device 180D are located adjacent to each other, and P-type drain region 206B is formed inside or next to P-type cathode region 210B. In particular, drain region 206B of FinFET 200B and cathode region 210B of LtSBD™ device 180D are directly coupled to each other, and a first contact access is not needed on anode region 206B of LtSBD™ device 180D. Further, in some implementations, drain region 206B of FinFET 200B is not coupled to any other device except LtSBD™ device 180D, and therefore, another contact access to drain region 200B could also be saved. Therefore, when LtSBD™ device 180D and FinFET 200B are electrically coupled on the same substrate, the chip area is saved not only for using LtSBD™ device 180D that has a relatively small size, but also for sharing drain and SBD combined contacts and saved wiring area.

[00117] Similarly, when LtSBD™ device 180D and FinFET 200B are electrically

coupled on the same substrate, p-type drain region 206B of FinFET 200B and an anode region 210B (diffusion bed 104D) of LtSBD™ device 180D are electrically coupled, and they are optionally coupled by an interconnect wire or by being located adjacent to each other. In some implementations, the chip area is saved not only for using LtSBD™ device 180D that has a relatively small size, but also for sharing drain and SBD combined contacts and saved wiring area.

[00118] As shown in FIGS. 2A-2D, FinFETs 200 have a non-planar (sometimes called 3D) structure compared with conventional planar devices as shown in FIGS. 1A-1H. Source region 204 and drain region 206 are coupled to metal connect structures 212 and 214, respectively. When LtSBD™ devices 180 are integrated with non-planar FinFET 200 on the same diffusion bed, barrier metal 182 is also coupled to metal connect structure 216 on the surface of the substrate. In some implementations, metal connect structures 212-216 have substantially vertical sidewalls. [00119] Further, in accordance with some implementations of this invention, gate 202 of FinFET 200 (e.g., FinFET 200A or 200B) has only one fin. Alternatively, in some implementations, gate 202 of FinFET 200 includes two or more fins. In general, the FinFET SOI structure does result in further miniaturization of the transistors, so their gate, S/D capacitance and components are substantially reduced than the planar structures. Nevertheless, we expect the SCMOS™ techniques we developed based on CLtSBD™ properties remain to hold improved PPA advantages like what we see in planar transistors. But SCMOS™does offer alternative advantages to use less advanced production facility to make the best PPA chips today with much cheaper costs.

[00120] In various embodiments of this application, SCMOS™ refers to "super

complementary metal oxide semiconductor" or "Schottky based complementary metal oxide semiconductor. SCMOS™ technology integrates high threshold Schottky Barrier Diode (HtSBD) and/or low threshold Schottky Barrier Diode (LtSBD™) into existing CMOS technology. A HtSBD normally has a higher turn on voltage than a LtSBD™. Exemplary turn on voltages for a HtSBD (using PtSi and CoSi) and a LtSBD™ (using Vtd) are equal to 0.7V and 0.1V, respectively.

Synchronous Dynamic Logic Gates

[00121] FIGS. 3A and 3B illustrate two exemplary SCMOS™ synchronous logic gates (e.g., a 4-input NOR gate 300A and a 4-input NAND gate 300B) in accordance with some implementations of the application. Each logic gate 300 A or 300B includes two cross-coupled inverters, i.e., a forward inverter INV1 and a feedback inverter INV2. An input of inverter INV1 and an output of inverter INV2 are coupled to an internal voltage node IG, and an input of inverter INV2 and an output of inverter INV1 are coupled to an output node OUT of logic gate 300 A or 300B. In some implementations, NOR gate 300A further includes a NMOS transistor MN3 that is coupled in parallel with a NMOS transistor MNl of feedback inverter INV2, and the gate of NOR gate 300A is driven by an inverted clock signal CLKB. Cathodes of four LtSBD™s D1-D4 are integrated into MNl or MN3, and the common cathode node coupled to internal voltage node IG, and corresponding anodes of LtSBD™s D1-D4 are coupled to receive four logic inputs A, B, C and D, respectively.

[00122] Likewise, in some implementations, NAND gate 300B further includes a PMOS transistor MP3 that is coupled in parallel with a PMOS transistor MP2 of feedback inverter INV2, and the gate of NAND gate 300B is driven by a clock signal CLK.

Common anodes of four LtSBD™s D1-D4 may be integrated into MP3 or MPl, and is coupled to internal voltage node IG, and corresponding cathodes of LtSBD™s D1-D4 are coupled to receive four logic inputs A, B, C and D, respectively.

[00123] From another perspective of the dynamic logic gates, each logic gate 300A or 300B includes a feedback inverter INV2 that forms a latch with another forward inverter INV1. A synchronous dynamic clock serves to retain the "1" or "0" state by maintaining a Quiescent (Q) state by charging up or draining the internal voltage node IG. During the Q state, the logic gate's logic function is blocked, and output OUT turns out to be a voltage rail reference opposite to internal voltage node IG. When clock pulse is asserted, the diode generates the corresponding OR or AND functions, and a strong forward inverter INV1 delivers NOR or NAND function, secured by a weak feedback inverter INV2 to form a latch with the right logic value. So the logic truth table only valid during the synchronous clock window. It is invalid outside the window deemed Q-state.

Nevertheless, data/control paths can be chained and finally end into static latch or DFF. The advantage is fast and small areas, big Fanin and Fanout capability.

[00124] It is noted that during the Q-State, all input diodes are synchronous with internal voltage node IG determined by the clock Q-state. This is to assure the zero stressed biasing (ZSB) condition is satisfied, and there is no leakage current flow between input diodes. These gates may have no dc currents.

[00125] In some implementations, cathode regions of LtSBD™s D1-D4 are integrated with (i.e., located adjacent to) the drains of transistors MNl and MN2 of feedback inverter INV2 in NOR logic gate 300 A. In some implementations, anode regions of LtSBD™s D1-D4 are integrated with (i.e., located adjacent to) the drains of transistors MPl and MP2 of feedback inverter INV2 in NAND logic gate 300B. In these exemplary logic gates, the gates have only one internal gate net (IG node) that drives a forward inverter INV1. The output drives a feedback inverter INV2, whose output is the IG net. Under some circumstances, high-speed operations are needed, and it is important to a small capacitive load at internal voltage node IG.

[00126] When LtSBD™s D1-D4 are used to implement synchronous logic gate 300A and 300B, only a single small transistor MN3 or MP3 is needed to couple a clock signal CLKB or CLK to corresponding logic gate NOR 300A or 300B, respectively. In contrast, if implemented by CMOS logic gate transistors, each synchronous logic NOR and NAND gate requires a huge transistor pair (including a PMOS transistor and a NMOS transistor) to couple a clock signal. The SCMOS™ logic gates reduce area and power substantially for on-chip clocking facilities.

[00127] In some implementations, at the Q-state, inputs A-D coupled to LtSBD™s Dl- D4 are set either at the ground (GND) for NOR logic gate 300A, or at a high power supply voltage (VCC) for NAND logic gate 300B. As such, each diode is biased with equal voltage potentials at its respective two terminals, and therefore, drains no direct current. Each gate exhibits dual functions depending on whether its respective clock signal CLK or CLKB is active or quiescent. At the Q-state, the respective logic function of each gate is blocked, and the output OUT is reset to VCC or GND, and at an active state, LtSBD™s Dl-D4 are optionally biased to enable the logic function of the respective gate. Idled logic nets may serve as additional synchronous biasing voltage supply resources.

[00128] It is noted that NOR4 gate 300A and NAND4 gate 300B are configured to

become a four-input NOR gate and a four-input NAND gate, respectively. NOR4 gate 300 A and NAND4 gate 300B could be easily modified to couple more SBDs at their respective internal voltage node IG and become other multiple-input (e.g., eight-input) logic gates. For example, in some implementations, additional four LtSBD™s are coupled at voltage node IG of NAND gate 300B, and form an eight-input NAND gate together with the existing LtSBD™s D1-D4. In the prior art, the eight-input NAND gate is implemented in MOSFETs, with two or more stages of CMOS NAND gates each having less inputs (e.g., 2-3 inputs). The transistors of the NAND gate have relatively large intrinsic capacitances (e.g., gate capacitance and gate-to-source capacitance). Thus, if implemented in one stage, the eight-input NAND gate made of transistors would result in a large delay for some of its inputs and create a large fanout load for a logic stage preceding to this NAND gate.

[00129] Unlike the prior art NAND gate made of transistors, NAND gate 300B uses

SBDs that have small sizes and fast speed. The total capacitance at the inputs is much smaller than the capacitance at the inputs of a corresponding transistor based NAND gate, such that a stage that drives this NAND gate 300B would be loaded with a moderate capacitive load even if the NAND gate 300B includes multiple inputs (e.g., eight inputs). Furthermore, LtSBD™s have a relatively low turn-on voltage, and can provide a large current to switch the logic levels in a faster speed. As such, basic logic gates 300 A and 300B that include LtSBD™s improves the speed of digital circuit compared with corresponding digital circuit that is made of transistors only.

[00130] Further, in some implementations of synchronous SCMOS™ NOR gate 300A, if inputs A-D are at a low voltage level, node IG is at a low level. Thus, at a Q state, LtSBD™s Dl-D4 are biased with GND at both ends. When one of inputs A-D switches to a high voltage level, node IG is driven to a high voltage level via previous stage totem pole P-Tx, resulting in the functionality of NOR gate 300. In some implementations, transistors MP1, MN1 and MN2 have relatively small transistor sizes. "No stacking transistor chain" rule of SCMOS circuit is not applicable for SCMOS™ asynchronous logic gates. Rather, the capacitance load at IG node has to be kept to ensure a fast speed of the corresponding logic gate. In some implementations, transistor MP1 of NOR gates 300A is eliminated. The latch works with three transistors MP2, MN1 and MN2, if a preceding input drive is strong, and the equivalent resistance of LtSBD™s D1-D4 are relatively low (e.g., less than 50 ohms).

[00131] Furthermore, as explained in FIGS. 1A-1H, SBDs use smaller chip area than a planar transistor or a non-planar device (e.g., FinFETs). SCMOS™ logic gates 300 are therefore smaller than corresponding CMOS logic gates. To build a digital circuit block, logic gates 300 A and 300B would reduce the chip area and increase the device density of the circuit block. In some implementations, transistors MP1-MP3 and MN1-MN3 are implemented using 3D transistor devices (e.g., non-planar FinFETs), and the chip area and the device density of logic gates 300A and 300B could be further improved.

[00132] In some implementations, the LtSBD™s applied in logic gates 300A and 300B are free of leakage during idled states, occupy a small circuit area, render a high switching speed, and are compatible with token control clock loads. In some

implementations, inverters in logic gates 300 A and 300B is used with totem pole LtSBD™s. In some implementations, the power supply VDD is a pulsed supply. In some implementations, the output OUT node is associated with a substantially low capacitive load.

Hard Wired SCMOS Logic Gate Blocks (e.g., for use in FPGA devices)

[00133] In some implementations, wide input signal channels are accommodated by wide synchronous SCMOS™ logic gates 300. LtSBD™s are used to carry digital signals in SCMOS™ logic gates, and result in fast speed, small footprints, and Fan-in and Fan-out immunity for the resulting SCMOS™ logic gates. Exemplary performance matrices demonstrate that a field programmable gate array (FPGA) implemented in hardcoded SCMOS™ logic gates 300 has a 2-5 x times improvement in speed (or delay), a 2-5 x improvement in space, and a 4-8 x improvement in power savings over conventional FPGAs.

[00134] FIG. 3C illustrates a circuit diagram for an inverter 300C in accordance with some implementations of the application. Inverter 300C includes at least two LtSBD™s D5 and D6 that are coupled in series. Optionally, inverter 300C further includes two complementary PMOS and NMOS transistors (e.g., MP4 and MN4) that are driven by an input signal, and the two serial LtSBD™s are coupled between the PMOS and NMOS transistors. An output node OUT is coupled at an intermediate node between serial LtSBD™s D5 and D6. In some implementations, inverter 300C is configured to drive a latch or a random access memory (RAM) cell. With one bulk layout, and various metal tapings, the inverter may support CMOS signal levels with totem pole, or with

SCMOS™ output levels (1 Vtd offset from the rails). And the LtSBD™ may isolate either CFETs to the SCMOS™ net at the LtSBD™ center tap. Still another new feature is that the VDD does not have to be a fixed power supply, but it can be a controlled pulse signal. When the pulse collapsed, the LtSBD™ isolates the CFET output capacitance to the load line. This is explained in the Sense Amp part of the SRAM blocks.

[00135] In some implementations of the asynchronous NOR4 logic gate 400A (see FIG.

3G, SCMOS™ 4T2D-SRAM™ Cell Layout at Si-28 nm), a diffusion bed of a drain region of NMOS transistor MNl or MN3 is extended to encompass one or more of SBDs

D1-D4. In some implementations of the asynchronous NAND logic gate 400B (Not shown), a diffusion bed of a drain region of PMOS transistor MPl or MP3 is extended to encompass one or more of LtSBD™s D1-D4. Optionally, barrier metal silicides of LtSBD s D1-D4 are formed on the same layer of material from which the source and drain contacts of the corresponding transistor (MN1, MN3, MP1, or MP3) are made, except that the regions underneath the metal silicide material are the diffusion bed and the drain region for LtSBD™s D1-D4 and the corresponding transistor, respectively.

[00136] FIG. 3D is a circuit diagram for an asynchronous 6-Input NAND Gate with 4X drive in accordance with some embodiments. FIG. 3E is a circuit diagram for an asynchronous 6-Input NOR Gate with 4X drive in accordance with some embodiments. FIG. 3F is a circuit diagram for an asynchronous 4 to 1 Multiplexer with 2 X drive in accordance with some embodiments.

[00137] The main purpose of Low-threshold Schottky diodes is to replace MOSFET's for common Logic operations. As shown in FIG. 3D, P-type Schottky diodes (P-LtSBD™'s) are used to implement a NAND function. Further, as shown in FIG. 3E, N-Type

Schottky diodes (N-LtSBD's) are used for a NOR function. In order to perform these operations asynchronously, i.e. without a Clock Sequencer, it is necessary to add a Source Follower tree/stack of NMOSFET's (SFN) in a NAND Gate and of PMOSFET's (SFP) in a NOR Gate. SFN's and SFP's are non-inverting. In the case of a NAND Gate, a SFN pulls up the IG Node or drives the Output Totem Pole (OTP, schematics device names MP1 and MN1) towards VDD, when all

the P-LtSBD™'s are turned-off by the entire set of input signals at the Logic 1 State. In the case of a NOR Gate, a SFP pulls down IG/OTP towards VSS, when all

the N-LtSBD™'s are off when all the inputs are driven to the Logic 0 State.

The electronic properties of a SFN and SFP make this action faster than the usual pull- up/down action of a Common Source inverting stack of N/PMOSFET's (CSP and CSN) in a pure CMOS Logic Gate. There is no Miller Effect. Consequently, the equivalent on- resistance of the SFN and SFP may be set higher. The PMOSFET/NMOSFET width and the overall size of a CSP/N can be smaller, while still driving IG/OTP and propagating the Logic signal with a delay, which is sufficiently, low for the SCMOS™ Gate to be faster than its pure CMOS counterpart. A pure CMOS Logic Gate with many inputs must be implemented with several stages of CSN and CSP's, especially when VDD, the Supply Voltage is reduced to or below 1.0 V. In contrast, the corresponding SCMOS™ Gate is built with a single inverting stage, its OTP. A slower signal transient on IG is still faster than the sum of two or more CSP/CSN Logic inversion delays. [00138] Furthermore, as shown in FIG. 3F, complex gates can be implemented by connecting in series blocks of P-LtSB™'s with their CSN performing AND operations and of N-LtSBD™'s with their CSP performing OR operations.

[00139] In accordance with some implementations of the application, FIG. 3H compares propagation delays associated with precharge low of synchronous NAND Gates that are implemented based on SCMOS™ and CMOS technologies, respectively, and FIG. 31 compares propagation both high-to-low and low-to-high propagation delays of asynchronous NAND Gates that are implemented based on SCMOS™ and CMOS technologies, respectively.

[00140] FIGS. 3A-3C and 3F are the feature highlights of the SCMOS™ logic gate

devices for comparison with the CMOS logic gate implementations. This gate uses pulsed ac clock. It requires ac current flow during the active state.

[00141] From this layout drawing, it is obvious that the SCMOS™ gate has small

footprint advantage due to SBD replacing many transistor switches as in the

conventional CMOS logic gate on the right side. Also, the big RC delay path due to stacked larger transistors has disappeared. The SCMOS™ gates only has simplified clock and inverter constructs with no stacked transistors in either N or P transistor legs. Another attribute of merit for SCMOS™ gate is due to Fan-in loads are greatly reduced for SBD is a lean circuit element, with little capacitance and small body size occupies a couple contact and space for anode or cathode, and sharing the same Drain contact with the transistors and other SBDs. The elegant layout insures node 1 capacitance is low compares to any CMOS circuit nodes, and even it requires dc current during the asserted window, it appears worthy for the other advantages.

[00142] Fan-out Immunity. The total capacitance that the output of SCMOS™ sees is approximately 10% of what the output capacitance of CMOS. Each output load of a

SCMOS™ circuit is only the input of a SBD, which is about the size of a contact hole.

This compares against a CMOS input, which sees gate to drain, gate to channel and gate to source for the p-Channel transistor and also sees the equivalent 3 capacitances for the n-Channel transistor. Since the Output sees such a small load capacitance, the size of the

Output p-transistor and the Output n-transistor can be made much smaller. In addition the Output has one p-transistor and one n-channel transistor drain, the Output transistor Drain Capacitance is also a lot smaller. Therefore SCMOS has Fan-Out immunity. In other words we can have a very large number of Fan-Outs before we start impacting speed. This compares very favorably with CMOS, whose performance slows down dramatically with increased Fan-Outs. Fan-In Immunity. As can be seen in FIG. 3B, Adding an additional input to the SCMOS™ Circuit (the left figure) only adds a

Schottky diode to Node 1. This does has minimal impact on performance, power or chip area. So the speed is roughly the same whether you use 1 input or 10 inputs(SBD).

Whereas in the CMOS circuit, for every additional input we need to add a new p- Transistor and an n-Transistor, with significant penalties in speed, chip area and power. Therefore we claim the SCMOS™ has Fan-in Immunity.

[00143] In some implementations (as shown in FIGS. 3A and 3B), we show another type of SCMOS™ logic gates, using internal feedback inverter to form a latch with the forward inverter. The asynchronous dynamic clock only serves to retain the "1" or "0" state by maintaining a Quiescent (Q) state by charging up or drain the internal node 1 , so the gate's logic function is blocked, the output turns out to be a voltage rail reference opposite to node 1. When clock pulse was asserted, the .diode tree generates the OR or AND functions, the strong forward inverter delivers NOR or NAND function, secured by the weak feedback inverter to form a latch with the right logic value.

[00144] It must be observed that during the Q-State, all input diodes are synchronous with the node 1 voltage determined by the clock Q-state. This is to assure the zero stressed biasing (ZSB) condition is met. And there is no leakage current flow between input diodes. These gates may have no dc currents.

[00145] Several options are available for implementing the above asynchronous logic gates. One option is to implement simplest circuit of CMOS (like DFFs as shown in FIG. 7E), only use NAND2 or NOR2 for set/reset controls, attach SBD to the output Tx drain for SCMOS™ interfaces. All transistors can be small size since we are not driving big CMOS nets. Another option is enabled when source followers(SFs) are used to the diode ORing nodes. The SF string is complementary to the diode summing nodes at each internal nodes and can use minimum size stacked transistors without hurting speed, this is very different from standard CMOS circuit where stacked transistors must suffer large sizes for area and speed double penalties. Therefore, our SCMOS™ Asynchronous solutions are still smaller than CMOS circuits, only they are more expensive than our synchronous gates, which require economical clocks.

SRAM bit-cell

[00146] FIGS. 4A, 4 A' and 4B illustrate circuit diagrams of SCMOS™ bit cell 500 and a conventional CMOS bit cell 550 in a static random access memory (SRAM) array in accordance with some implementations of the application, respectively. SCMOS bit cell 500 includes four transistors (two PMOS transistors MP5 and MP6 and two NMOS transistors MN5 and MN6) that are configured to form two cross-coupled inverters (i.e., a latch). The two identical inverters are coupled in the same manner as the forward and feedback inverters in basic logic gates in FIGS. 3A and 3B. The two cross-coupled inverters are driven between a word line write (WLW) signal and a word line read (WLR) signal. SCMOS™ bit cell 500 further includes two LtSBDs D7 and D8 whose cathodes are coupled at output nodes of the two cross-coupled inverters. The cathodes of the N-type LtSBD™s D7 and D8 are integrated into the drain node of MN5 and MN6, while their anodes receive a bit signal BL and an inverted bit signal BLB. In this application, SCMOS™ bit cell 500 is also called 4T2D-SRAM™ bit cell 500. Another design option of the 4T2D bit cell 500 is shown in Fig. 4A'. Here, the anodes of the P- type LtSBD™s D7 and D8 are integrated into the drain node of MP5 and MP6, while their cathodes receive a bit signal BL and an inverted bit signal BLB. In this application, SCMOS™ bit cell 500 is also called 4T2D-SRAM™ bit cell 500 (where "4T2D" means 4 transistor, 2 diode).

[00147] Like SCMOS™ bit cell 500, CMOS bit cell 550 also includes transistors MP5, MP6, MN5 and MN6 that are configured to form the two cross-coupled inverters.

However, the two cross-coupled inverters are driven between two power supplies (e.g., VDD and VSS) or between a power supply (e.g., VDD) and a ground (i.e., GND). The output nodes of these two cross-coupled inverters are coupled to drains of another two pass transistors MN7 and MN8, rather than LtSBDs D7 and D8. Gates of transistors MN7 and MN8 are controlled by a word line (WL) control, and sources of transistors MN7 and MN8 are coupled to receive bit signal BL and inverted bit signal BLB. In this application, CMOS bit cell 550 is also called 6T bit cell 550.

[00148] It is noted that in some implementations, transistors MP5, MP6, MN5 and MN6, and LtSBDs D7 and D8 have preferred device sizes (e.g., minimum sizes) that the corresponding SCMOS™ manufacturing process could accommodate. However, transistors MN5 MN6,MN7and MN8 normally have relatively large sizes compared with minimum dimension transistors MP5, MP6, MN5 and MN6, such that their equivalent resistances are reduced for the purposes of increasing the access rate to bit cell 550. FIGS. 4C and 4D illustrate exemplary layout schematics corresponding to bit cells 500 and 550 in accordance some embodiments of the application, respectively. Due to the use of LtSBD™s D7 and D8 in place of transistors MN7 and MN8, SCMOS bit cell 500 has an exemplary area of 1 OOF ² and saves 20% of the chip area compared to CMOS bit cell 550. Further, in some implementations, transistors MP5, MP6, MN5 and MN6 are implemented using non-planar (or 3D) semiconductor devices (e.g., FinFETs), and the chip area and the device density of the resulting SRAM array could be further improved. Our experience are the 4T2D-SRAM™ bit-cells are 20-39% smaller than the 6T same.

[00149] FIGS. 4E and 4F illustrates two exemplary memory array controllers 582 and 584 that are configured to drive SCMOS™ bit cell 500 and CMOS bit cell 550 in a SRAM array in accordance with some implementations of the application, respectively. Memory array controller 584 uses two power lines (VCC and GND), a word line control (WL) and two complementary bit line controls (BL0 and BL1) to drive CMOS bit cell 550. In comparison, memory array controller 582 uses a word line write control (WLW), a word line read control (WLR) and two complementary bit line signals (BL and BLB). Bit line controls are individualized for each bit cell on a row of memory cells, and however, bit cells on the same row share the power lines and the word lines. Therefore, SCMOS™ bit cell 500 allows to save one signal line for bit cells one each row of memory cells.

[00150] The word line write control, the word line read control, and the complementary bit line signals change in accordance with an operation mode (Read, Write or Stand-by) of SCMOS™ bit cell 500. More details on these signals are explained with reference to U.S. Patent Serial No. 6,852,578, titled "Schottky Diode Static Random Access Memory (DSRAM) Device, a Method for Making Same, and CFET Based DTL," which was filed on January 15, 2003 by the inventor of this application.

[00151] In general, compared with the 6T SRAM bit cell, the 4T2D-SRAM™ array can use minimum dimension transistors in the latch, but 6T SRAM has to use larger cell sizes. This results in significant area savings. Furthermore, the P and N well reference biasing is separate from the VCC and GND. The Twin Word line pairs are operated independently from power supplies, allowing for more control over cell operations with enhanced noise margins and reduced leakages.

[00152] FIG. 4G illustrates a block diagram of a simplified SRAM module 50 for reading data from bit cells of a SRAM column in accordance with some implementations of the application. In this specific example, the SRAM column includes 32 bit cells (BL0- BL31), and one of the 32 bit cells is selected for outputting the datum stored thereon. As explained above, "4T2D-SRAM™ bit cell" is sometimes called "SCMOS™ bit cell." Each of the transistors in bit cells BL0-BL31 is optionally made of planar transistors or non-planar transistors (e.g., FinFETs).

[00153] In some implementations, SRAM module 510 includes a bit line equalizer 510 that precharges and equalizes the complementary bit signals for the SRAM column (i.e., /BL0 and /BL0) during a write or read cycle.

[00154] In some implementations, SRAM module 50 includes a readout circuit 520.

Readout circuit 520 further includes a sense amplifier 522 and a latch 524. Sense amplifier 522 is coupled to the two complementary bit signals, and amplifies the bit signal to a high or low power supply level (e.g., VDD, VSS or GND) according to the datum stored in a selected bit cell. Latch 524 is further coupled to the output of sense amplifier 522 and latches the amplified bit signal. In some implementations, latch 524 includes two inverters that are cross-coupled to each other (i.e., an output of a first inverter is coupled to drive a second inverter, and an output of the second inverter is coupled back to drive the first inverter). Optionally, sense amplifier 522 includes one or more LtSBD™s. Optionally, latch 524 includes one or more LtSBD™s.

[00155] The power supply of the sense amp is driven by a synchronous pulse from the column decode (Cdec). When activated during Read cycle, the selected BL/BLB pair will sense selected Bit-cell 50 for the 0 side low and let the 1 side to move up. Once the Sense amp 522 kicked in, it will amplify the input difference by the local cross coupled inverter, and the output diode pair will pass the information to the Latch 524. [00156] In some implementations, bit line equalizer 510 and readout circuit 520 are part of memory array controller 582.

[00157] LtSBD™s are used to replace some transistors (e.g., pass transistors) in both SCMOS™ bit cells and readout circuit 520, and serve both the switching and/or signal coupling functions. Due to the use of LtSBDs, bit cell 500 is created with a smaller size and smaller stray capacitance on the bit line. In addition, LtSBD™s enable sense amplifier 522 and latch 524 to provide better circuit performance with respect to their respective speed, circuit area, and power consumption. As shown in FIG. 4G, in some implementations, the LtSBD™s are used to couple the complementary bit signals (BL0 and /BL0) to the input of sense amplifier 522. In some implementations, the LtSBD™s are used to couple sensor amplifier 522 and latch 524.

[00158] FIG. 4H illustrates an exemplary write circuit 540 for a bit cell in accordance with some implementations of the application. In some implementations, write circuit 540 is part of memory array controller 582. Write circuit 540 is configured to receive input data Din and write the input data to a bit cell, e.g., SCMOS bit cell 500 or CMOS bit cell. In some implementations, write circuit 540 includes one or more LtSBDs. In a specific example shown in FIG. 4H, LtSBD™s D9-D12 are used to replace pass transistors at the interface of write circuit 540, and configured to couple the input data DIN to write circuit 540. Alternatively, in another example, decoupling LtSBD™ pair (e.g., D13 and D14, D15 and D16) are added at the output, and used to isolate capacitor loading among transistors coupled at an output node. Bit control DBen is provided by a bit line decoder to select a pair of complementary bit lines for writing data into a corresponding bit cell. FIG. 4H shows that LtSBD™s could be used to implement logic gates, memory cells, signal switching, coupling, and decoupling, and therefore, deliver logic, peripheral and array functions of a memory module.

[00159] All BL/BLB are relatively heavy capacitive metal bus lines. For high speed

switching in Reading or Writing, the drivers need to be strong totem poles. So the output transistor of the data bus (BL/BLB) are multi-finger wide transistors, D13-15 also need to be big LtSBD™s. DOUTt should routed from LtSBD™ center rather than transistor center to save light loading for the data bus lines. And when the data is not needed, all the VDD supply collapsed, D13-D15 serve the purpose to decouple totem transistor loading to the BL/BLB during the read cycle operations.

[00160] FIG.4I illustrates an exemplary SCMOS™ dual port SRAM (DPSRAM) bit-cell 560 in accordance with some implementations of the application. DPSRAM cell 560 includes six transistors. Optionally, DPSRAM bit-cell 560 is coupled to receive a write port control WL, and a bit select signal BL, and a read port control RE, and outputs a read output OUT. DPSRAM bit-cell 560 includes a four transistor latch (including transistors Tpl, Tp2, Tnl and Tn2) for writing data and another transistor string

(including Tp7, Tn4 and Tn3) for reading data stored in DPSRAM bit-cell 560. Both the latch and the transistor string are manipulated by the SCL™ type two port decoders, which are independently addressable without collisions. In some implementations, transistor Tp7 is shared by bit-cells in a row of memory cells. A PMOS based feedback transistor Tpl is applied to charge up node Nl to a high voltage, while in prior art, a NMOS based feedback transistor is used to discharge node Nl . If a pass transistor is using a N-type transistor, node Nl could only be charged up to one threshold voltage (Vt _h ) below the VDD without using Tpl, but Tnl has no problem to discharge node 1 to ground. Hence the best design goes with using Tpl rather than using a feedback pull down transistor.

[00161] In some implementations, a decoupling LtSBD™ pair (including LtSBD™s D17 and D18) is coupled to the output OUT, and a similar LtSBD™ pairs (D3-D16) are used at the output of write circuit 540 in FIG. 4H. Specifically, LtSBD™s D17 and D18 are used to isolate parasitic capacitance that could be coupled from transistors Tp7 and Tn4 at the output, and thereby reduces the parasitic capacitance at the output node OUT'. FIGS. 4J and 4K illustrate layout schematics 570 and 580 of two exemplary DPSRAM bit-cell 560 without and with the decoupling LtSBDv pair (D17 and D18) in accordance with some implementations of the application, respectively. By arranging transistors differently, one renders same schematics with different packing layout sizes of 154F ² and 134F ² , respectively.

[00162] Another big advantage is using LtSBD™ coupling to the bit line pair, to sense amplification, latch signals, decode, and gate data. This implementation can be expanded to improve DRAM, NV ROM, Flash arrays, FPGA, and peripheral circuitries, and high capacitance (HiC) bus lines and interconnections. LtSBD™s can be used for signal coupling and decoupling, in these and other macro circuits.

[00163] Adding LtSBD™ as a basic circuit element of an IC device changes CMOS chip area, speed, and power consumption significantly to the point we have a new branch of IC classes in microelectronics, and have a new market space delivering more advanced system components that perform better, and cost less, and extend longer life spans way beyond than today's CMOS devices can be.

[00164] Various embodiments of this application expand the inventions disclosed in U.S.

Patent Serial No. 8,476,689, titled "Super CMOS devices on a microelectronics system," by introducing low threshold Schottky barrier diode (LtSBD™), SCMOS™ process, and LtSBD™ based circuit implementations. Optionally, LtSBDs are integrated with planar CMOS transistors and non-planar (or 3D) deep-nm transistors. Some exemplary

LtSBD™ contact barrier metals are mid-band metals such as Ti, Co, Ni, WSi2, CoSi2, NiSi2, TiSi2, TaSi2, each having a Fermi level around 0.52 eV, to improve P and N type LtSBD™ forward and reverse I-V curves, one may alter localized Si crystalline parameter changes such as Ion-implant Ge atoms, As, or B underneath the barrier Silicides, use rapid thermal anneal (apply few seconds laser beam),..etc. to yield spike free and smooth silicide surface and side walls. Richardson constant of forward I-V curve may drop by half for P type LtSBD™. In some implementations, surface doping concentration is around 1.3 x 10 cm ³ for both N and P type LtSBD™s. In some implementations, the silicide thickness is around 300 A, and sub-implant peaks at 10 ²⁰ cm ^"3 . For the sheet resistance to be under

10 ohm/square, the shoulder from beneath the Schottky silicide to sub-implant should be around 1000 A. In some implementations, masks are used to define the areas for N+ and P+ sub-implants. This is to enable a substantially low LtSBD™ body resistance for the semiconductor well of a LtSBD™, such as less than 100 ohm running transient up to ΙΟΟμΑ peak.

[00165] It should be noted that at the deep-nm process nodes are less than 28 nm, the LtSBD™ and SCMOS™ design principles disclosed herein, can be implemented by using the 3D transistor process means. In some implementations, all transistor process steps are otherwise kept the same as for CMOS or FIN-FET, FD SOI Technology, and thermo implant, electro-chemical treatment is identical to the Logic, RAM, and NV Flash devices. Some exemplary design principles for implementing 3D LtSBD or SCMOS™ integrated circuits include the following: the LtSBD™ can be placed in the drain diffusion region of a transistor, if it is deep enough to allow sub-implant be placed, and keep a low surface concentration region a couple hundred Angstrom deep, a stacked epi region can be used by dividing it into drain and SBD sub-regions by sub-implants, and an optimal gate length is found to be around 20 nm, where the Fin FET gate is 80 nm tall and the stacked epi drain pocket is 40 nm thick.

[00166] In some implementations, Complementary LtSBD™s (CLtSBD™s) are

integrated in a Silicon CMOS processing flow that manufactures transistors having more than one threshold voltages. In some situations, a CLtSBD™ has a turn-on voltage of at ±0. IV at room temperature, and drifts to ± 0.2V at 0 °C at a corner case. In some implementations, a transistor is isolated by oxide sidewalls, and its drain bed contains N and P type LtSBD™. Optionally, the LtSBD™ includes a barrier metal made of Co, silicide or the like, and exhibits a rectification property, i.e., sharp forward IV

characteristics. When reversely biased up to 2.5V, this exemplary circuit has a substantially low (e.g., less than 10 nA) leakage current at an exemplary operation temperature of 85 °C.

[00167] A feature size of a CMOS or SCMOS™ technology represents a size of a

smallest physical feature (e.g., a contact, or a line width). Optionally, the feature size is greater than 28 nm for use in some low end products. Optionally, the feature size is less than 20 nm for use in some high end product. Planar transistors and gate structures are measured by 2D parameters on a corresponding semiconductor substrate. Non-planar transistors and gate structures (e.g., FinFET 200) are measured by 3D parameters while taking into consideration of other factors, such as the shape of the gate, the sub-channel doping profile, whether the source and drain are fully depleted, and whether the source and drain are fully isolated by dielectric structures.

[00168] In various embodiments of the invention, CMOS technology is modified to

enable SCMOS™ technology that integrates planar and non-planar transistors with LtSBD™s. In some implementations, the resulting SBD-based memory and its controller are configured to be biased with a power supply of 0.5-0.6V, and operate under the control of either a synchronous or asynchronous clock. Alternatively, in some implementations, LtSBD based dynamic and static circuit blocks are created to replace existing transistor based CMOS, NV MPROM, and Flash circuit. Thus, LtSBD™ and SCMOS™ technology would enable another LtSBD™ based version of all previous transistor based circuit implementations. When such LtSBD™s are integrated with planar and non-planar transistors in the SCMOS™ technology, they would reduce the physical area, increase the device density and raise the operating rate of the resulting circuit.

Mask Read-Only Memory (MROM)

[00169] FIG. 5A illustrates a block diagram of an exemplary Mask Read-Only Memory 900 in accordance with some implementations of the application. MROM 900 is optionally used to store program codes in a microprocessor. MROM 900 includes a nonvolatile MROM (NVMROM™) array 902, a row controller 904, a column controller 906 and a readout circuit 908. MROM 900 contains audio, video, and data files that are accessible with a high speed clock signal having an exemplary frequency of 1-10 GHz. In some implementations, such a MROM 900 is packaged in a memory module that is further mounted on a printed circuit board (PCB) unit, and the PCB unit includes dozens/hundreds of MROM chips like MROM 900. MROM 900 is optionally used to store data associated with educational materials, medical records, scientific data, books, notes, reports, manuals, records, movies, musicals, movie clips, sport recordings and the like. MROM 900 could be installed on microprocessor of any computing device, and used to store the aforementioned different types of data.

[00170] FIG. 5B illustrates a layout schematic of part of a NVMROM™ array 902 in accordance with some implementations of the application. In some implementations, NVMROM™ array 902 is accessed at a rate of 1-lOGHz, and used to store embedded program codes. NVMROM array 902 includes an array of LtSBD™ bit cells, each including a LtSBD™ device and occupying an exemplary area of 4F ² (F is a feature size of the corresponding CMOS manufacturing process). Regions of the chip are masked off during a photolithography process. Specifically, contacts are defined or blocked by a photolithographic mask to enable a data bit "1" or "0" on the LtSBD™ bit cell, respectively.

[00171] In some situations, due to the use of LtSBD™s in MROM array 902, both a first pitch of the memory rows and a second pitch of the memory columns are reduced to twice a feature size (i.e., 2F) of the corresponding CMOS technology. Each MROM memory cell made of a LtSBD™ occupies an area of 4F ² , and operates at a fast rate (e.g., 1-lOGHz). Once NVMROM™ array 902 is implemented in such a small area and operates in such a fast speed, it would be used in many applications, e.g., an embedded memory and storage unit in a microprocessor. For example, MROM 900 has been used as a technology bench marker driver in IBM because it could be made to comply with the most stringent design rules. In some implementations, MROM 900 is configured to store source codes for an operating system (e.g., Microsoft Windows 7), Internet packet protocols, video programs, media data (e.g., pictures and video clips), games, smart card information, private documents and the like. It is noted that SCMOS™ technology allows MROM 900 to gain more advantages on device size, device density and operating speed, because if implemented by conventional CMOS transistors and PN junction diodes, MROM 900 would have a large chip size, operate at a slower speed, and be incompatible with corresponding interface controllers that often operate at a data rate of 1-10 Gbps (gigabits per second).

[00172] In a specific example, NVMROM™ array 902 includes a plurality of memory cells that are arranged in a two-dimensional array having 1024 rows and 1024 columns. Each of row controller 904 and column controller 906 includes a respective 10 bit decoder. In accordance with data received at the input of the respective 10 bit decoder, row controller 904 and column controller 906 selects one of the 1024 rows and one of the 1024 columns, respectively. The bit cell located at the cross point of the selected row and column is thereby selected, and readout circuit 908 is configured to read out the data stored in the selected bit cell. In various embodiments of the application, SBDs are applied in at least one of MROM array 902, row controller 904, column controller 906 and readout circuit 908. When SBDs is applied in MROM array 902 or specifically in each bit cell therein, row controller 904 and column controller 906 are configured to generate proper biasing voltages to select a targeted LtSBD™ based memory cell for read, and readout circuit 908 is configured to read the output voltage provided by the selected LtSBD™ bit cell.

[00173] In some implementations, the LtSBD™ based bit cell 902 is substantially smaller than a typical DRAM cell. NVMROM™ array 902 could be 8000 times faster than a flash nonvolatile memory.

[00174] FIGS. 5C and 5D illustrate a NOR gate 9042 and a NAND gate 9062 in

accordance with some implementations of the application, respectively. The 10 bit decoder of row controller 904 is made of NOR gates 9042 arranged in a X-direction parallel to the rows, and the 10 bit decoder of column controller 906 is made of NAND gates 9062 arranged in a Y-direction parallel to the columns. In a specific example, both the NOR and NAND gates in 10 bit decoders have a pitch of 2F.

[00175] FIGS. 5E and 5F illustrate a row address buffer 9044 and a column address buffer 9064 in accordance with some implementations of the application, respectively. Row address buffer 9044 is part of row controller 904, and provides a row address input to the row decoder that is optionally made of NOR gates 9042. Column address buffer 9064 is part of column controller 906, and provides a column address input to the column decoder that is optionally made of NAND gates 9062. Each buffer includes two serial CMOS inverters in which a first inverter converts an input clock to an internal node IG and a second inverter continues to convert the internal node IG to another internal node IH. Each buffer further includes two LtSBD™s (D19 and D20, D21 and D22) that are electrically coupled to the input and the output of the buffer, respectively. Specifically, for row address buffer 9044, the anode and cathode of LtSBD™ D19 are coupled to a buffer input IN and internal node IG, respectively; and the anode and cathode of SBD D20 are coupled to internal node IH and a buffer output OUT (i.e., the row address input to the row decoder), respectively. For column address buffer 9064, the cathode and anode of SBD D21 are coupled to a buffer input IN and internal node IG, respectively; and the cathode and anode of SBD D22 are coupled to internal node IH and a buffer output OUT (i.e., the row address input to the column decoder), respectively. Thus, LtSBD™s are applied to couple at the input/output (I/O) interfaces of a buffer that is optionally coupled to a NOR based decoder or a NAND based decoder.

[00176] In some implementations of MVMROM™ array 902, row controller 904, and column controller 906, two terminals of the SBDs are biased with equal voltage potentials (i.e., the SBDs have a ZERO VOLTAGE BIAS across their diode junctions), when the SBDs are not selected and stay in the Q-state. Therefore, for those inactive row controllers 904, column controllers 906 and memory cells, the corresponding LtSBD™s do not have any leakage current or consume a substantially low leakage current.

Conversely, when a specific memory bit cell is selected and accessed, each SCMOS™ circuit block that is impacted (e.g., row controller 904, column controller 906 and the specific memory bit cell) includes an internal node (IG) whose voltage changes as a result of selecting and accessing the specific bit cell. The capacitance load at this internal node IG is driven by synchronous clock signals during a memory read cycle, and affects the overall speed of the corresponding circuit block. Here, when transistors coupled at node IG are replaced with LtSBD™s, the overall speed of the corresponding block is enhanced.

[00177] FIG. 5G illustrates a block diagram of another exemplary Mask Read-Only

Memory 900 in accordance with some implementations of the application. MROM 900 also includes a NVMROM array 902, a row controller 904, a column controller 906 and a readout circuit 908. NVMROM™ array 902 includes bit cells 902A-902I, each further including a SBD. Bit cell 902A-902I stores a bit datum of "1" or "0" in accordance with a corresponding masking operation that creates or blocks a contact on the corresponding LtSBD™, respectively.

[00178] Row controller 904 is coupled to receive a plurality of parallel row inputs, and column controller 904 is coupled to receive a plurality of parallel column inputs. Row controller 904 includes a NOR gate that uses two or more coupling SBDs to receive the row inputs. A WL output of row controller 904 is coupled to drive a row of bit cells (e.g., 1024 bit cells). Column controller 940 includes a NAND gate that uses two or more coupling LtSBD™s to receive the column inputs. A BL output of column controller 906 is coupled to drive a column of bit cells (e.g., 1024 bit cells). In a specific example, for each bit cell, a WL output and a BL output are coupled to drive an anode and a cathode of a LtSBD™ included in the respective LtSBD™ bit cell, respectively.

[00179] Readout circuit block 908 includes a sense amplifier 908A and a latch 908B. In some implementations, each column is associated with a respective sensor amplifier 908A and a respective latch 908B. Respective sensor amplifier 908A is coupled to the respective bit line that is optionally coupled to the cathodes of the LtSBD™s included in the bit cells in the corresponding column. Sensor amplifier 908A amplifies (i.e., digitalizes) the bit datum read from a selected bit cell. Latch 908B is further coupled to sensor amplifier 908A, and outputs the read bit datum. From another perspective, MROM 900 includes a memory array controller, and the memory array controller further includes row controller 904, column controller 906, and readout circuit block 908.

[00180] FIG. 5H illustrates time diagrams of seven signals of MROM 900 in accordance with some implementations of the invention. MROM 900 includes a system read clock (e.g., Bit ck) configured to synchronize circuit operations in MROM 900. MROM 900 further includes a word line address (WLad ck), a word line decoder control (WLdec ck), a bit line address (BLad ck), a bit line decoder control (BLdec ck), a sensor amplifier control (SA ck), and a latch output (Latchout). During a read cycle 920, these signals are synchronized to control row controller 902 and column controller 904 to select a bit cell in MROM array 902, and enable readout circuit 908 to extract the datum stored in the selected bit cell. Specifically, in this embodiment as shown in FIG. 5H, the bit datum stored in a specific cell is read out at the latch output during a time period 922 of read cycle 920. The above control signals used in MROM 900 are synchronized with respect to a system clock.

[00181] In some implementations, given a feature size of F, a MROM bit cell made of a LtSBD™ device occupies an area of 4F ² . In contrast, a SCMOS 4T2D-SRAM™ bit cell 500 made of LtSBD™s and transistors have an exemplary size of 1 OOF ² , and a conventional SRAM 6T bit cell 550 made only of transistors have an exemplary size of 120F ² . Even for a dynamic random access memory (DRAM), the smallest DRAM cell approximately occupies an area of 10F ² . Therefore, SBD bit cells 902 occupy

substantially smaller areas, and increase storage density for the resulting MROM 900. In a specific example, MROM 900 is manufactured by 28 nm manufacturing technology. Resulting MROM 900 could accommodate 20GB source codes on a chip area of 1cm ² , which is sufficient to enable an entire operating system (e.g., iOS™ and Android™).

[00182] More details on a mask programmed ROM core in the low cost SoC device are explained with reference to Figs. lOa-lOe in the U.S. Patent Serial No. 8,476,689, titled "Super CMOS Devices on a Microelectronics System," which is hereby incorporated by reference in its entirety.

Design Guidelines [00183] Various integrated circuits utilizing Schottky Barrier Diodes disclosed by the embodiments of the present disclosure are introduced in detail above. The principle and implementation of the present disclosure are described herein through specific examples. The description about the embodiments of the present disclosure is merely provided for ease of understanding of the method and core ideas of the present disclosure. Persons with ordinary skill in the arts can make variations and modifications to the present disclosure in terms of the specific implementations and application scopes according to the ideas of the present disclosure. Therefore, the specification shall not be construed as a limit to the present disclosure.

[00184] In this patent filing, the center subject is the SCMOS™ SRAM embedded

memory core array and its peripheral control circuitries. The SCMOS™ techniques include both structural and logical architectural changes to the CMOS same. Both are critical important basic features to enable widest ALMS product implementations for optimized PPA (Power, Performance (speed), and Area) advantages.

[00185] The PHY structure areas are reduced to practice by additional process means; refine process flows, use new barrier contact metals, and add newer electro-chemical- mechanical treatments for making CFETs and concurrent CLtSBD™ with optimized SBD I-V characteristics.

[00186] The sbDTL™ allows new circuit architecture changes from traditional CMOS transistor coupling techniques, whereby a huge number of transistors are replaced by CLtSBD™s, and the CLtSBD™s are further integrated into the drain bed of the transistors, and bunches of diode and transistor terminals can be shared with least space for connection and wiring. The new circuit possess leaner circuit elements, less area and stages, faster speed, and huge saving in chip area and power consumptions.

[00187] Generic IC solution options utilizing mixed analog, logic, memory, and storage blocks are proposed with the following niche features that often better than the best CMOS similar. More details of the process, and circuit design guidelines in chips, modules, and PCB hardware are detailed below with reference to various embodiments as illustrated in the figures of this application.

[00188] First of all, the main emphasis is to utilize the Complementary Low Threshold SBD (CLtSBD ) and transistors of various thresholds to make broad range of functional blocks on a common substrate wafer containing thousands of repetitive chips that perform various computer functions. The chips often contains billions of switches and a collect of switches may perform analog, logic, memory, and storage (ALMS) functions. Units and sub-units of preferred interconnected blocks are call macros. These macros are repeatedly reused, have as much as possible layout compactness, extremely high speed (in Giga Hz per second on/off operations), low operating current typical (+/- 1-100 uA) and voltages (+/- 0.1 -0.2V), and burning least power in operation. System power supply can be 1.25 V or lower, Li-ion battery may backup system operation.

[00189] Fast computer speed includes quick milli-sec system wake-up, execute multi- thread, multi-task, parallel data processing and networking, large on chip Cache eliminating non-responding times (less than 1 sec) when conducting data streaming and processing, accessing large memory and IO disk resources, support personal data computing and server networking, Internet searching, routing, and bridging .

[00190] Further, Schottky CMOS and Super CMOS are used interchangeably here as the "SCMOS™" technology. The Logic gates are classified as the Schottky CMOS Logic (SCL™) for it is based on using the threshold voltage difference between CLtSBD™ and CFET as basic circuit elements to implement various switching, memory, storage, and field programming functions. Super CMOS technology means all the SCMOS™ circuit innovation ideas are designed with the assumptions that the circuits are compatible with CMOS in fabrication processes (electro-chemical and thermo-mechanical) and line equipment settings. This means least alternation to produce similar IC devices using current CMOS state of arts, with equal or more relaxed design rules and physical parameters. Even the EDA software ought to be adjusted from current CMOS design kits by experienced process and EDA engineers with little adjustments.

[00191] However, certain Hi-niche SCMOS™ hard macro constructs [REF 1-5] have to be developed and simulated in detail. They are based on a new LtSBD™-DTL

(sbDTL™^ architecture totally different from any CMOS TTL circuit configuration. Due to extensive swap of transistors with simple LtSBD™ diodes, the SCMOS macros possess high speed (GHz) property, less total nets, less transistor counts and stray capacitances, smaller footprints, slight signal offsets -0.1V offset to rail to rail signal levels, burns only fraction of power from similar functional CMOS macros. Therefore, SCMOS™ circuits shall serve as super set macro solutions for chips which contain both types of circuitry to the designer's discretion. In our design bench mark study, it was found that the performance matrices are highly in favor of the SCMOS™ blocks (See FIG. 8 A bar chart). More advantages if the functional blocks are more sophisticated with big Fan-in and Fan-out signals, employs stacked transistors and has complex wiring tracks. Because of using LtSBD™ as the inter-block coupler rather than Transistor direct coupling, the SCMO™S implementation always exhibits enormous immunity for input and out loadings. Except it is highly sensitive to the only internal node 1 capacitance, and to the diode body resistance if the LtSBD™ size was small and the transient current spike is big in 100s μΑ. The golden rule of thumb is to keep node 1 small net

capacitances.

[00192] In some implementations (e.g., SCMOS™ circuits as shown in FIG. 2), SBD serves 4 distinctive functions. It is the smallest logic switching element, the analog signal amplifier with high transconductance/Gm parameter (Delta I/Delta V), and signal coupler and de-coupler. It also stores a NV ROM bit with GHz speed and 4F ² per bit density (See FIGS.5A-5H). The beauty is its tiny PHY size, practically, one contact per signal channel with little transit capacitances from the bulk or the parasitic.

[00193] In some implementations, the LtSBD™ can also be crafted onto the S/D bed in the 20-nm Fin-FET structures. In a specific example, FIG. 2A shows the bulk structure of a 20 nm gate length FIN FET(160 nm tall), the oxide isolated drain wells and Si02 Box floor, ideal sub-channel implant. The source/ drain is made of tapered EPI stack of 40 nm tall. FIG. 2B shows the Drain region may contain sub-regions for the Drain contact and for the lightly doped LtSBD™ contacts, which may have heavily doped bulk resistance bodies.

[00194] Further, in some implementations, the clocking schemes of each SCMOS™ gate functions further enables it to provide the zero-stress-biased (ZSB) interface condition for selected circuitries. It enhances leakage limited yield control, and device reliability. This is a unique property non-existed in any normal CMOS logic gates. Which only provides logic functions but do not provide dc biasing options.

[00195] In some implementations as shown in FIGS. 3A and 3B, one type of the dynamic logic SCMOS circuits driven with pulsed asynchronous clock. The prorated asynchronous clock with low duty cycles can reduce the chip power consumption to 10-50% (100-500 ps windows). The clock circuit runs with small dc currents, which is limited by the sourcing current provided by the long channel clock transistors. The diodes in the diode tree are often integrated into either common anode/drain of the P- FET, or common cathode/drain of the N-FET. Both save the node 1 capacitance and avoid wiring capacitance added to the only internal node 1. The LtSBD™ not only is conductive with its little inherent capacitances when active, but also decouples the hi-C nodes, such as S/D to gate nodes or array bit line or word line, to the (inverter) driver's output node when it is inactive or reverse biased.

[00196] Further, in FIGS. 3A and 3B, we have another type of logic gate configured by back to back inverters. The weak feedback inverter is formed by two long channel transistors driven by the strong inverter (output), which are composed of two short channel transistors. The output totem pole may also have an option with a coupling LtSBD™ pair if SCMOS™ signal levels are required.

[00197] There is no need to provide major external clock here, except to keep a known Q- state to assure all diodes are biased off. Diode inputs may drive the Latch directly during the active state. When the clock was inactive (Q-state), the clock charges node 1 to VDD or GND, all diodes are biased at same potential at both ends. This fulfills the ZSB conditions. These macros have no dc current flow. It reduces clock resource to the bear minimum. This is a big relief for all ASIC chips which demand a huge clock resource and power budget!

[00198] In various embodiments of the application, the LtSBD™ 's forward I-V electrical property follows Richardson equation that is displayed in FIGS. 6 A and 6B for various metal barriers (PtSi, Co-Si) and 3 diode area sizes. Other metal ought to be considered if the Vtd of the N or P type LtSBD™ needs to be optimized, i.e. Er can make extremely conductive N-SBD. Or Pt for P-SBD. The body resistances are dependent on the surface and sub-implant concentration profiles for the entire diffusion bed region from beneath the barrier metal to the drain contact of the CMOS transistors. The barrier metal material, thin film deposition, electro-chemical t etching, and thermo sintering treatment, and the 3D resistor implant body shape determine the diode I-V behaviors, forward and reverse breakdown, and leakage currents.

[00199] Further, in some implementations, the LtSBD™'s device physics and properties are applied in two important new business sectors. First, the Photovoltaic properties are used to render power storage subsystem for the Auto industry and power management infrastructures. Second, the LtSBD™s could also be applied in Bio-medical, life science instrumentation for health care and maintenance, organ disease (for instance, bird's flue, Mad Cow, human cancer cell, DNA identification., etc.) detection and control equipment and system development. These are two double digit growths, booming business sectors which microelectronics components may add great values to hardware and software data processing, sensors, and information storage needs. These subjects are beyond the scope of the present patent application, they will be explored later after we get SCMOS™ device established in computer and Internet applications.

[00200] Further, in some implementations, as summarized in FIG. 9, the LtSBD™s are applied to construct a NV mask programmable ROM (MROM) for code storage purpose in a microprocessor. This NVM offers the world's tinniest memory and fastest bit cell (4F ² /bit), and the densest decoder-pitch (2F) hard macro and runs in GHz range. It incorporates all essential SCMOS macros which have wide system applications as any embedded memory and storage units in a processor. The MROM chip was used as a technology bench marker driver in IBM for it uses tightest design rules everywhere. Business wise, the codes may be the Windows7™ OS source code, Internet packet protocols, video programs, music and pictures, games, smart card, or private documents. Note that the simultaneous advantages apply only for the SCMOS™ technology. If implemented by CMOS-TTL and PN junction diodes, the NV ROM is slow and bulky, not attractive at all to be embedded with GHz controllers.

[00201] In some implementations, FIGS. 6C and 6D show area comparison between the bit cells of SCMOS™ 4T2D twin word line (TWL) SRAM and the CMOS 6T-SRAM implementations. Note that in 4T-cell, transistor and diode sizes are minimum

dimensioned. However, in 6T-cell where the pass transistor is used, the latch transistor has to use larger size (Tl, T3 will be 4X bigger).

[00202] FIGS. 4G and 4H shows the 4T2D-SRAM™ array and sense amp and latched output. All comparable construct was based on SCMOS™ implementations. Because of using the LtSBD to serve the switching and signal coupling functions, we realize the smaller bit cells (compared with prior art of 6T SRAM cell), less stray C for the bit lines, more elegant sense amp and latch interfaces. There is no question to yield significant overall gains (orders of magnitude better in performance indices) for speed, area, and power savings simultaneously. The data-enable gate and driver design for the array bit lines includes a bit line equalizer 510 as shown in FIG. 4G. Control signals come from selected bit line decode, so only selected bit line pairs are charged up or down.

[00203] Again, SBD are neat to deliver Logic, peripheral and array functions with the most efficient implementations for logic gates, memory cells, signal switching, coupling, and decoupling. FIG. 41 describes the SCMOS™ dual port RAM bit cell constructs. Direct comparison is made to the prior art CMOS counterpart as shown in FIGS. 4L-40. FIGS. 4L, 4M and 4N are circuit diagram for 6T or 8T DPSRAM cells in prior art. FIG. 40 is a circuit diagram of a SCMOS dual port SRAM (DPSRAM) array cell in accordance with some implementations of the application. The cell includes two parts - the 4T latch for writing data and 2T for reading data out. Both parts are manipulated by the SCL™ type two port decoders, which are independently addressable without collisions. Tp7 is shared by all bit cells in the selected word. More details are explained with reference to U.S. Patent No. 7,116,605.

[00204] Specifically, as shown in FIG. 40, the feedback Tpl is helping node 1 to charge up, whilst in prior art, the feedback transistor (N20) is helping to discharge node 1. We know that if the pass transistor is using a N-Tx, node 1 is in difficulty when it is reaching to one Vt below the VDD in up-swing, but Tnl has no problem to discharge node 1 to ground. Therefore, the inventor's prefers to help charging up in this case. Furthermore, in layout, the dual port bit cell layouts are shown in two versions FIGS. 4 J, 4K for the size of 154F ² , and 134F ² respectively. There is an option here that the decoupling LtSBD™ pair can be added between the totem pole Tp7 and Tn4. A LtSBD™ is used to isolate capacitor loading among transistors in the bank.

[00205] The Schottky Pass Transistor Logic (SPTL™) macros are added with many

exemplary implementations for designs that need clock and small dc currents. For example, in FIGSS. 3A and 3B, however, we show designs using the SBD coupler to feed a 4T latch, where we use strong forward and weak feedback inverters, the external clock is eliminated. The strong forward inverter employees short channel transistor, the weak feedback transistors are narrow width or long channel. Both are minimum dimensions. These circuitries reduce the clock driver resource of the entire chip;

contributing to a huge saving in area and power budget.

[00206] The hard wired compact SCMOS™ micros have orders of magnitude advantages in speed, area, and power saving matrices. Complete functionality includes embedded ALMS library units which can support any ASIC chip sets in a PCB/module system, and it is field programmable with abundant CMOS wiring tracks now freed for flexible and instance design changes or maintenance services. The FPGA system design methodology can be upgraded if the CMOS based design library and on chip resource are partially or fully replaced by SCMOS™ based standard logic cells for processors, RAM and NV ROM, GHz buses and super efficient MUX constructs. These features are depicted in FIGS. 7A-7E.

[00207] In FIGS. 7F-7H, we have Si-28 nm design simulation analysis done with the leading customer and alpha FPGA partner on MUX4:1, MUX 8:1, MUX20: 1 network. Because of our smaller foot prints, inherently ultra high speed, less net counts, less transistor counts, and superior immunity to big Fan-in and Fan-out, we showed remarkable bench mark design gains over existing CMOS FPGA design records. The upper end gains are some 6X improvement in speed, 5X in area reduction, and 8X in power saving.

[00208] The performance drive on CMOS for the past 3 decades was based on physical size and process parameter reduction, and electrical I-V signal scaling. The industry was booming for 40 years until 2012 when it butt against the natural wall, and the famous Moore's law stopped spinning. The law of physics cracked when we re-engineering the same experience in building complex chips that contains billions of transistors and complicated wiring structures and expect cost reductions via operating costly fab facilities, and highly skilled labors. The laws of economics cracked for performance tend to flatten out and costs are running up drastically once the material process is reaching molecular dimensions, the equipment facility, and labor cost become horrendously high.

[00209] Unless we re-invent a new way of doing the microelectronics hardware, the deep nano-meter game has no hope to see new lights in the dark tunnel. Even the 3D FinFET or fully depleted FET on SOI technology will not stand a chance to continue breaking the Moore's law in a long run.

[00210] No technology and materials could be economically developed to function

beyond its molecular barrier with conflicting boundary conditions. We have been piling up the complex structures and immense capacity, and demand GHz speed together, and expect plain and economical solutions without equipment and resource cost adders. You may beat the horse to death; he just cannot run with the heavy load.

[00211] The only hope to re-start a new method continuing the microelectronics games is to device an orthogonal new approach, such as to add new circuit elements like the LtSBD™s, start new circuit architecture-Schottky-CFET DTL, making implementations with quantum jumps in performance and efficiency while does not impact costs. As indicated in FIG. 8A; the major IC trend and circuit road map. The semiconductor IC and IT industry has 4 times in history to adopt new circuit design concepts, and develop new product for continued miniaturization. It is ready to jump shift to SCMOS™ gear, so more relaxed design rules can be re-engineered for a new brand of customized system components, that surpasses current ones at less costs. And the Moore's law can be extended for two more decades bringing more opportunities to all workers.

[00212] The three major shifts in IC history using big value add circuit innovations along with orthogonal drive in device miniaturization and signal reduction. The 1 ^st revolution occurred in the 1960s using vertical current based Bipolar transistor technology to make PN junction transistors, making DTL, TTL, and ECL configured IC for generic computer chips. In the second phase of the Bipolar device era in mid 1970s, this author invented the oxide trench isolation techniques and high threshold Schottky diode clamped TTL that offered low cost but better speed MSI devices. The 3 ^rd wave of IC implementations started by Intel pushing surface channel based CMOS transistors and offering LSI based IC system chips for the PC and work station computers. It enjoyed big wins in system applications for its endless scaling and re-spinning newer designs over 30 years. By year 2010, worldwide IC and IT sales revenue reached a trillion dollar marker.

[00213] For the detail discussion given above, the author believes the SCMOS™

technology will start a new era making the best microelectronics system component for the Internet and cloud computing, and personal business networking. There are compounded advantages in SCMOS systems several orders (200X+) of magnitude over the current CMOS system. If Moore's law with SCMOS™ can be re-established at the 90 nm Si-node within a year, and due to the CMOS compatibility, we can create new brand IC components by stretching forward and backward at least 10 Si-nodes to license SCMOS™ design library for custom chip design and foundry services. The upside worldwide market boom can be $60B in 10 years, and $3T in 20 years. This offers the best incentive to customers and VCs join the SCMOS™ motion, and wining their commitments.

[00214] One of the major advantages of SCMOS™ products is its strong power saving for battery backup operations. In FIGS. 9 A and 9B, we took a snap shot of active power consumption waveform during a CMOS cell phone or I-pad operation. We estimate close to 90% power can be cut if SCMOS™ parts are in place. Further, in some

implementations not shown in any figure, simple SCMOS™ circuits can directly drive an ear plug or microphone. FIGS. 10A and 10B compare the performance gaps between various on chip functional units that hinder low power and compact integration. CMOS hardware chips must be upgraded by SCMOS™ replacement to deliver higher throughput in bandwidth and housing more storage and memory capacity.

[00215] In some implementations, IO cells are implemented by SCMOS™ chips. The Hi- Z Buffer and the Schmitt trigger are important to interface high capacitive bus lines at chip or internal wires. In the Schmitt Trigger Input Buffer (STIB), two diodes and their series resistances may be implemented to enhance the turn on voltage threshold references.

[00216] FIGS. 11A -1 ID discloses two basic circuit configurations of the bridge diode circuits of an RFID circuit implementation in accordance with some implementations of the application. In both circuits, RF signals are coupled via dipole antennas to MOS input transistors. FIGS. 11 A and 1 IB show where diodes are wired by 3 terminal MOS transistors. In FIGS. 1 IC and 1 ID, however, the SBD was used directly for rectifier operations. One can obviously see the advantages when the bulky PN junction parasitic capacitance was eliminated, because the power conversion efficiency was greatly improved. The SBD version implementation has almost no backgate leakage effects, and its forward resistances are orders of magnitude smaller than the MOS channel resistances.

[00217] Although dipole and monopole antennas are not necessarily the best candidates for UWB antennas, they are easy to manufacture and low cost. FIG. 11C is the electrical equivalent of a half wavelength dipole antenna presented in "Modeling and Simulation of A Dipole Antenna for UWB Applications using equivalent spice circuits" John F.M. Gerrits, Andreas A. Flutter, Jaouhar Ayadi, John R. Farserotu, Centre Suisse

d"Electronique et de Microtechnique SA (CSEM) Neuchatel - Switzerland. The Voltage source VTX and Rs represent the output signals. The Rl stands for the antenna loss resistance. Rr is the radiation resistance of the antenna. The Rl, which is lMeg ohm, is used for Spice convergence. The C2 is used to improve the performance of the antenna above resonant frequency fO. Since the antenna is a linear network, we can use a voltage source for Vrx to simulate the antenna receive. The input signal level from the MOST version is about 1 V peak-to-peak at 150 uW input power, assuming Cin=l pF at 915 MHz, Vtd=0.5V. The LtSBD™ version shall work with much less input power, and input signal required is about 0.5V, the Vtd=0.2V, the power conversion efficiency PCE > 50%.

[00219] FIGS. 1 IE and 1 IF illustrate on chip charge pump chain of the LtSBD™ and capacitor ladders in accordance with some implementations of the application. This is handy for on-chip power reference to bias local P-well or N-well that would adjust Transistor threshold voltages in accordance with some implementations of the application. In some implementations, the LtSBD™ ladder circuit works with both phase AC signal generators, which are 180° apart. The body resistor can be as low as 10s ohms, the C of the charge pump can be 2 pF, the source impedance can be 70 ohm, this makes the time constant of 200 ps. Note that the diodes only see no more than 1 Vpk reverse biasing, and the on chip/module charge pump operation can be in the Giga-Hz range.

[00220] FIGS. 12A-12D describes a PLL and frequency multiplier implementation using SCL™ macros. All the TTL NAND gates are implemented by the SCL™ NAND/NOR gates. The feedback inverter (as shown in FIGS. 3A and 3B) can adjust the delay of each TD buffer, hence the frequency of the oscillator. And the FPGA local wiring tracks can provide best loop and frequency. Very wide signal MUX schemes can be implemented by the simple SCMOS choppers shown in FIG. 12A. 30 MHz crystal oscillator can be multiplied to form GHz bit clock chains by the wave combiner shown in FIG. 12D.

[00221] In some implementations, nice and sharp pulses can be obtained by adjusting the 30 MHz crystal oscillator wave forms with one or a few stages of inverter delays. This is shown in FIGS. 12B and 12C. These pulses can feed into the big OR tree which are the MUX implementations described here and also in FIGS. 7G and 7H of FPGA

applications for several GHz bit clocks.

[00222] There are two types of SCMOS™ dynamic clock and feedback (FB) inverter schemes: (1) with clock and small dc biasing current from the long channel clock transistors to pull up or sinking node 1 (e.g., FIG. 3B with forward inverter only), and (2) with clock and no direct current as depicted in FIG. 3D (a) or (b). Both schemes employ a feedback inverter to source/sink biasing currents during the transients. This is a preferred scheme. The user is advised to apply ZSB conditions for all input diodes.

[00223] Further, in some implementations, the delay line synthesis block is implemented by the inverter strings with external crystal for stability. This low frequency loop offered 30 MHz oscillators. Other means of generating 30 MHz loops may use the CMOS TTL gates, and/or SCL™ gates, the present invention. Here the feedback delay line leads are muxed by transistor-diode pairs, One Hot Selection (OHS) cell, where only one of the control signals determines the low frequency pulse width. In some implementations, the 30 MHZ wave form (Pulse width is 16.7 nS) are shifted to form 208 ps pulses by firstly the NA2 gates, followed by the NOR tree to generate the 2.4 GHz bit clock at 2.4 GHz.

[00224] The proposed high frequency generation described above is based on the

controllable phase splitting and simple SCL™ type logic circuit for signal processing. Rather than generating high frequency directly with higher jitter, a secure lower frequency oscillation is controlled, then manipulated with the lower range oscillatory circuit waveforms to composite and synthesize very high frequency signals. The procedures from the above embodiments may be altered to yield equally spaced switching edges with the combination of fine granular segment delays and simple mathematical divisions. Simple D-flip flop stages will yield dual or quad-phase division, the inserted SCL™ inverters will match and patch any timing gaps with fine granularity under 100 ps. [00225] The SCMOS macros can also apply to improve the peripheral and 10 blocks such as in the Flash and DRAM chips, modules or cards. For example, FIG. 13 showed the Controller for the DRAM SIMM -. By using a SCMOS™ controller, lower bus signal wires can be designed, lowering it to 1.0 V, the DRAM chips are also accept this lowered address and data signals, and there are internal peripheral circuit with SCL™ interfaces. This new controller and chips will operate at DDR3 and DDR4 speed while burning much less power.

[00226] If all high capacitance bus lines (both inter and intra chip address and IO data signals) are swapped with SCMOS™ constructs, we can scoop up big economical and speed gains to the memory and storage chips, modules, and PCB cards. In general, the IO and decoders occupy more than 50% areas and speed delays. In service business sense, there is a great value add to win business in these business sector without touching the guts to redesign the bit cells. We know that Flash and RAM cards have a $60B market today, and for decades no one has any clear technology superiority in these product lines to get ahead of tough competitions from peers. We can license our SCMOS™ solutions with any of the product leaders to co-develop optimized new implementations and gain significant market shares in these important business sectors. If we have Cache controllers in each card driving the SCMOS™ RAM/Flash chips with low swing signals, we will win big margin in system speed, cost reduction, and power savings for all high and low end applications.

[00227] There are also opportunities to over haul the DRAM and Flash (especially the MLC) bit-cell structures and their electrical operations via SCMOS™ process means. This is a much more aggressive goal involving process flow and device physical parameter changes. These subject matters can be pursued as the second phase leg after the peripheral circuit changes. It is desirable that DRAM and Flash cells can be operative with embedded lower voltage power supply.

[00228] The process means to improve Flash and DRAM controllers is based on making the Schottky CMOS devices, which are comprised mainly of CMOS transistors, added with newly developed low barrier Schottky diodes (P and N types of Co LtSBD™ with sub-implant options), and multi-level cell (MLC) FLASH transistors. Still another niche implementation may be based on the embedded Mask ROM, the Schottky Pass Transistor Logic (SPTL ^1M ), and the Schottky CMOS Logic (SCL ^1M ) gate arrays shown in FIGS. 3A-3F. Still another implementation is based on the Programmable Schottky CMOS Logic (PSCL™) SPTL™ (Not elaborated here) switching circuits, gate arrays shown in FIGS. 7A-7E, wherein a variable threshold NMOS transistor may replace the regular switching transistor. During the initialization windows, the existing scan ring in the PCB chips and/or the FPGA programming arrays can selectively adjust the Vt of the switching transistor, re-configure the intra-connections of the simple SCL™ gates, and complete all global interconnections of various units. Embedded hardware arrays, soft macro constructs all in one chip, and protocols are parsed instantly in milli-seconds.

[00229] The Variable threshold transistors thus serve three distinct functions. First, TNI acts (focus 531) as an analog information storage device to store various chunk of charges directly programmed onto the variable threshold gate. This is to store/write and read out nonvolatile information in a SCL™ gates. Second, the diode tree couples the logic signal directly to the single threshold transistor in the forward inverter with or without feedback inverter. This type of constructs can deliver widest multiplex functions achieve big space saving, GHz speed, and consumes only a fraction of CMOS power consumptions. Third, the Flash and/or FPGA may store and operate on large amounts of information in megabytes efficiently with other local embedded RAM units.

[00230] Therefore, the mixed SCL™ type FPGA and MLC storages may emerge as the most compact logic and memory devices embedded on chip in Si technology. This is especially true for hand held small systems. Large server systems may still require many module or PCB packages of various chip sets.

[00231] A simple device implementation may involve fastest (GHz) Mask ROM state machines, which can be high capacity and achieves speed as fast as the CPU. Before this time, ROM (like Flash memory) was operated with relatively slow speed in the uS range, simultaneously write and read (Dual port) on-chip Cache arrays, registers, LI, L2, L3 for instruction codes and data storages, and logic gate arrays for CPU data and control paths. The SoC device may build with Giga Hz USB2+ IO, Giga-Hz speed gate array logic arrays, Mega Byte NV machine codes and using process from logic product line, low cost Si+2Metal layers.

[00232] Once again, via the SCMOS™ circuit means the low power consumption, high performance, and high capacity ICs are designed to achieve the best system integration and it can mix and replace portion or full conventional CMOS-TTL circuits with less parts. The idea of multi-value logic composed of binary, ternary, and quaternary hardware and firmware is also introduced. FIG. 8A summarizes comparison of system merits in bar charts between the chips from current CMOS TTL and the emerging SCMOS™ implementations.

Advantages of SCMOS™ Technology

[00233] While the industry is continually driving the IC with CMOS Si technology

towards further miniaturization, further scale down of I-V operating conditions, shown in FIGS. 8A and 8B, have met stiff resistance in lowering supply voltages and physical dimensions further down to molecular distances (~20 nm or below). However on the other extreme, we observed that while the power supply in logic device is winding down from 5 volt to 1.8V (with 0.1 μιη design rules), some important memory core building blocks (i.e. MLC Flash) still requires conflicting higher on-chip working voltages to the range of 10/20 volts. On this end, complex circuit and mode of multi-threshold operations requiring higher voltage ranges to satisfy biasing and noise margin conditions. On the other end, lowering supply voltage and signal margins create formidable constraints in complicated CMOS-TTL circuits, which often have high serial transistor paths due to stacked transistors with high RC time constants, and self biasing body effects. There are severe conflicts that increased device functionality and capacity are against voltage scale down.

[00234] Addition orthogonal innovation, such as ours by changing circuit topology, and invoking a niche LtSBD™ element becomes a only critical and viable alternative to find a breakthrough in search of design creativity in a new dimension.

SCMOS™ Low Power Solutions

[00235] Our efficient solution to alleviate the inherent CMOS-TTL design and processing problems is to use an innovative active component element Low Barrier Schottky Diodes (LtSBD™) in CMOS. This was firstly disclosed in US patent 6,590,000 and U.S. patent no. 6,852,578, "Schottky diode static random access memory (DSRAM) device, a method for making same, and CFET based DTL", issued February 8, 2005, Subsequently the "Super CMOS devices on a microelectronics system." US Patent No. 8,476,689 was granted on July 2, 2013. This was filed on Dec.23, 2008.

[00236] The applications are expanded using a niche device, low threshold Schottky

barrier diode (LtSBD™), SCMOS™ process, and special sbDTL™ circuit means.

[00237] First of all, LtSBD™ may be integrated with 2D CMOS transistors and 3D deep- nm transistors. First, to cover the new trend in device miniaturization, all components in the chips are down sized structurally by process means, At older process Si-nodes, where the minimum feature size F were larger than the 28 nm, we are using the 2D transistor (FIG.2) process means. Keep all transistor fabrication process steps the same as in CMOS products; thermo implant, photo-resist lithographical, and electro-chemical treatments identical to the Logic, RAM, and NV Flash devices.

[00238] The only process adjustments are the LtSBD related portions. See FIG. 4A and 4B. The oxide trench is -3000A deep, the poly thin film may be 2000A thick and dope can be adjusted by localized implant at the buried contacts. LtSBD™ contact barrier metals are mid band metals Co, Ni, Ti. silicide. Femi-level is around 0.52 eV. Surface concentration is around 1-3E16 for both N and P type Schottky. The silicide thickness is around 30θΑ. Sub-implant is peaking at 1E20 for the sheet rho be under 10 ohm, the shoulder from beneath the Schottky silide to sub-implant should be around ΙΟΟθΑ. There are optional masks for N+ and P+ sub-implants. This is to prepare the LtSBD™ body resistance (anode or cathode) low, less than 100 ohm running transient up to ΙΟΟμΑ peak.

[00239] At the deep nm process nodes less than the 28 nm, we are using the 3D transistor

(FIG.2A, 2B) process means. Keep all transistor process steps the same as CMOS or

FIN-FET, FD SOI Technology; thermo implant, electro-chemical treatment identical to the Logic, RAM, and NV Flash devices. The only process adjustments are the LtSBD™ related portions. See FIG. 2A and 2B. Some of these implementations are partially supported by the following references: a dissertation titled "Advanced MOSFET Designs and Implications for SRAM Scaling" by Changhwan Shin and published by UC

Berkeley in Spring, 2011; a publication titled "28 & 20nm FDSOI Technology

Platforms" by Giorgio Cesana and published at Technology R&D, ST, 2012; a publication related to "Enhancement of Program Speed in Dopant-Segregated Schottky- Barrier (DSSB) FinFET"; an article titled "SONOS for NAND-Type Flash Memory" by Sung- Jin Choi, et al, publiced on IEEE Electron Device Letters, VOL. 30, NO. 1, JANUARY 2009; and U.S. Patent Application No. 8,004,058, titled "Schottky diode for high speed and radio frequency application," filed December 14, 2009.

[00240] The LtSBD™ can be placed in the Drain diffusion region if it is deep enough to allow sub-implant be placed, and keep a low surface concentration region a couple hundred Angstrom deep. Otherwise, we can make stacked epi region, divide it into Drain and LtSBD™ sub -regions by sub-Implants. Gate length is around 20 nm, the Fin FET gate is 80 nm tall, the stacked epi drain pocket is 40 nm thick.

[00241] Further, to keep the new trend in PHY scaling, we can make simultaneous gains in speed, area, and power saving by circuit design means. In some implementations, as shown in FIGS. 3A and 3B, long channel or narrow width transistor designs are used for the feedback inverter. Clock biasing transistors that require only small ac current drives are used. In some implementations, as shown in FIGS. 3 A and 3B, short channel transistor designs are used for the forward inverter that requires strong current drives.

[00242] Further, in some implementations, types of Logic Gates may apply to everywhere in the system. First, use dynamic clock, forward inverter only, FIG. 3B. has dc current flow during pulsed windows. Burn prorated power. All diode inputs ought to be synchronously biased at VCC at Q-state. This is the ZSB condition [REF.4] to assure no leakage current between any SBD. Second, use dynamic clock, feedback inverter, FIG. 3D, (a) and (b) types. Have no dc current flow during pulsed windows. Burns only little ac power. This is a big relief for it relieves the huge clocking resource requirement for all digital processing hardware, in addition to speed, area, and power saving advantages. The clock resource has been the main pains for VLSI digital chips. It demand big area, and drain huge current as speed cranks up in GHz operations.

[00243] In some implementations, LtSBD™ pair coupling is particularly attractive

because it isolates output drain capacitance to next stage gate loads, and the N and P type

LtSBD™ protect each other by clamping the most reverse biasing is always less than one diode drop. If the VCC is a pulsed level, the totem pole presents an open circuit drive at

Q-state. The LtSBD™ pair coupling can direct drive 3T or 4T latches without using a pass transistor as interface. This macro is extensively applicable to 4T SRAM, 6T Dual Port SRAM, NV Flash array, NV ROM, FPGA, MUX, all array and peripheral circuits. It is elegant and has powerful advantages.

[00244] In some implementations, LtSBD™s are used in Schottky Pass Transistor Logic (SPTL™). Both transistor and LtSBD™ are active circuit elements. They can connect to each other forming efficient functional macros. The transistor counts are reduced and speed power saving are realized over CMOS solutions.

[00245] In some implementations associated with 4T2D-SRAM™ cells, we can use

minimum dimension transistors in the latch, but 6T-SRAM has to use larger cell sizes. So the area saving are much bigger than obviously conceivable. The P and N well reference biasing is separate from the VCC and GND. The Twin Word line pairs are operated independently from power supplies. One has more controls for leakage and cell operations. The biggest gain on this cell is using SBD coupling to the bit line pair. To sense amp, to latch, decoders, and data gate. This can be expanded to DRAM, NV ROM, Flash arrays, FPGA, and peripheral circuitries, and HiC bus lines and interconnections. Use SBD for signal coupling and decoupling..

[00246] In some implementations associated with 6T Dual Port bit cells, our invention is using Pull up feedback for the same intention. We give the reasons for the right choice. And the layout is shown for two options with area 154 F ² and 134F ² . In comparison, the prior art (US pat.7,116,605) used 4T Write cell with N-pass transistor and pull down feedback.

[00247] Further, in some implementations associated with NV Schottky MROM or Flash devices, a. Mask programmable ROM, using LtSBD will yield the GHz NV memory that holds biggest capacity storage next to only MLC Flash NAND devices. The bit cell is at 4F ² feature size, and decoder pitch is 2F ² . However, Flash is awful in reliability, endurance, and too low speed ^Sec) in read or write. One can never to house it with the processor chips, but MROM can. Therefore, we propose it for embedded chip for fixed data and graphics storage, single chips for OS, video, data processing as well as part of the chip set for powerful network search engine and storage chips. Data and IO instruction caching.

[00248] Fixed data array contains proprietary information that does not need to change but uses quite often for read only purposes. The author believes it has great market as I- cache resource leaving more room for data local store and serve as D-Cache unit in large or small controller chips. As the chips may contain huge switches and data, embedded cache units become more useful for LI storage for the single chip small machines, and also for chip sets in large system modules, and PCBs. So SCMOS™ may have big impact to upgrade all computer devices, for optimized system performance and lowest costs.

[00249] Further, in some implementations associated with Schottky FPGA and MUX, field programmable devices saves time to implement system with quickest changes for functionality or any reasons. It is desirable to also incorporate the popular ASIC macros so the speed will not be sacrificed. The biggest advantage each FPGA chip may have is its signal connectivity and selectivity in the network. Both the capacity and the speed is also the most important consideration in large network and complex routing paths, and the ability to resolve data packet traffic congestions. We found that in each device it provides localized MUX functions with 2-4 input signal or select codes, and wiring tracks to facilitate instance connections, some resource are allocated to provide global connectivity.

[00250] The wide signal channels can be accommodated by our SCMOS™ logic gates.

LtSBD™ happens to be the ideal circuit element to carry digital signals. The logic gates were simulated to offer fastest speed, smallest footprints, forgiven Fan-in and Fan-out immunity. All due to using the effective LtSBD™ and the sbDTL™ circuit

configurations. Our bench mark, FIG. 7F-7H with SCMOS™ MUX implementations, the sweet spot indicated a quantum jump in system merits to employ SCMOS™ FPGA ("SFPGA™") devices. The performance matrices are 2-5X in speed, 2-5X in space, and 4-8X in power saving.

Conclusion

[00251] In this invention, SCMOS™ circuit means and exemplary designs are disclosed. sbDTL™ gates formed various space, speed and power efficient implementations for Schottky based GHz logic gates, SPTL™ switching circuits, several SRAM bit cell and array circuits, NV MROM, Flash cell, and FPGA MUX device are examined. [00252] We also disclosed all emerging concepts and techniques that SCMOS Process means are updated to form LtSBD™, and CFET element in the modern foundry line. These line facilities support CMOS digital logic product, embedded NV ROM, SRAM, DRAM, SLC and MLC flash cells and SSD chips, and FPGA products. The process support Si-bulk and thin film wafer processing. The capability spans from Si-nodes 250 nm to 16 nm. The technology covers 2D planar transistors to 3D Fin-FET, and FD CFET SOT structures. In all cases, we can port SBD to integrate it with CFET for making generic computers.

[00253] The SCMOS™ technology described herein will open a new era to continue semiconductor device design and fabrication of IC components that are better and cheaper than current CMOS TTL chips delivered.

[00254] New VLSI product design libraries will be started and licensed to customers making possible new classes of microelectronics IT products. New series of SCMOS™ chip sets will be available within a year. More powerful system products will be available with affordable pricing. All of these SCMOS™ implementations, products and devices will possess the following attractive component and system attributes:

• Use the tiniest digital switch with smallest physical size of a contact hole, carrying a channel of independent electrical signals. Typical ac response times will be less than a nano-sec. Frequency response is beyond 1 GHz.

• Have the lowest on-off switching threshold - around 0.1 -0.25V. Have extremely simple circuit architecture using only CMOS inverters, integrated LtSBD™ tree, and CMOS pass transistors.

• Have reduced total transistor counts, net counts, gate counts, and wiring distances in a chip that housing billions of switches and other circuit elements.

• Have built-in zero power control scheme. And each cell has a single phase of asynchronous Clock or Enable controls.

• Insure zero stress biasing (ZSB) conditions for any selected circuit element(s) for any leakage sensitive circuitry. • Provide nearly zero wake up times. Both the inter and intra circuit nets will have much lower RC time constants than provided by current technology (10s of pico-sec).

• All functional blocks are operative with single voltage supplies down to 0.7V, consume least amount of AC power. The chips are equipped with charge pumps for various on-chip biasing supplies.

• Supports concurrently static CMOS-TTL and dynamic Schottky DTL circuit interfaces.

• Support embedded super macros for SPTL cell, gate array Standard cell, NV ROM, SRAM, DRAM, Flash Memory, and FPGA devices. Combined speed, space, power saving, matrices are 16-160X better than CMOS Si hardware of the same grade. Besides the powerful ALMS for computer processor, memory, and storage unit, the Schottky DTL is especially powerful to upgrade CMOS FPGA devices boosting its MUX/LUT functions. Our SFPGA™ and MUX solutions are attractive to all FPGA Internet system users and chip designers. The ROI is extremely high for relative simple work but maximum return on system speed and bandwidth congestion relief that are valuable to a vast OEM and service providers. They can sell SCMOS™ solutions for millions products, thousands license copies, and it is an ice breaker to get into SCMOS™ and design service business.

[00255] The product applications may cover storage disks, multimedia cards, RF signal processors, to graphics and display, and fully buffered DIMM, SSD card for laptop, PC and server, i-phone i-pad, camera, and many hand held computing devices.

[00256] The SCMOS™ device specifications are summarized as follows.

A. SCMOS™ Process Specifications

• Provide the state of art process means for making CLtSBD™ in a Si CMOS process line, that supports single or multi-value Vt for logic, analog, and floating gate transistors. See FIG. 2.

• The CLtSBD™ is having typical Vtd at +- 0. IV at room temperature, worst process window is +- 0.2V at 0C.

• The transistors are isolated by oxides. Its drain bed may contain N and P type LtSBD™ with Co or similar barrier metal and silicide to behave rectifier property with sharp forward I V characteristics following the specified curves. When reverse biased it conduct less than 10 nA leakage current up to -2.5V and at 85 0C ambient.

• Special process flow and thermo-electro-chemical treatments, implant mask and

sequence and operations may be required to insure acceptable SBD property is obtained, along with all reasonable transistor properties.

• Depends on the maturity of given SBD and transistor properties. The process means may be applied to various lines for making IC's at various design or line grades. The minimum lithographical grades are classified by the smallest physical size "F" that a contact or line length or width can be resolved. Currently, SCMOS™ process requires F to be from 16 nm up to 500 nm range.

• The state of the art further progressed to "F" being greater than 28 nm (low end

products) or less than 28 nm (high end products). Transistor and gate structures are measured by 2 (X-Y planes) or 3 (X,Y, Z)dimensional built, among other detail properties, such as the gate shape (Fin-FET), and sub-channel region and source/drain fully depleted and isolated by Oxide floor (FD FET SOI) structures. See FIG. 2A, 2B.

• The SCMOS™ device desires to support both high end and low end product applications mentioned above.

B. SCMOS Circuit Specifications

1. The CLtSBD™ serves 4 distinctive functions. It is a digital switch, a I-V amplifier (Gm), and signal coupler and de-coupler. It is a single contact device element if one terminal is shared with the group of other devices.

2. The CFET performs same functions as the LtSBD™ except it is a bulky circuit element with 3 terminals (Not counting backgate well terminal for Body isolation).

[00257] The transistors and LtSBD™s need to have matched different Vt values. In the sub-threshold region when either device begins conducting, Vtt needs to be 300 mV bigger than the Vtd. This is to insure that diode output can couple or decouple with the gate terminal of the transistor inverter. It must have sufficient Noise Margin for a simple NAND or NOR gate to operate correctly. See FIG. 3B, 3D.

3. All SCMOS™ macros are based on the principle that a LtSBD™ tree can be biased by hi-impedance transistor governed current source when selected. The tree is activated when terminal conditions was sound, and deactivated also when all terminals met by ZSB conditions. ZSB is important in a sense that all LtSBD™ are protected and no leakage current flows in Q-states. The simple logic gate is formed by feeding the diode tree (AND or OR) directly to a (forward) inverter During the active window, the gate (FIG. 3B) passes NOR or NAND logic values. When it is idle, the gate blocks all input signals but deliver a rail or gnd value for biasing use. This type of gates burns dc current when active. There is an optional design (FIG. 3D) that the LtSBD™ tree is biased by the long channel transistors of the weak inverter driven by the Strong Output inverter. In this case, Clock only acts as Q-State care taker it shuts off the retained latch signals and restore to clear state. The nice thing is clock does not draw significant ac power. It relieves system clock resource burden. Special attention is deserved for LtSBD™ to serve signal coupling interfaces.

Fig 3D (c). This cute macro is used often for almost everywhere in other large or small macro implementations. Repeated application of the above design examples result into core macro expansions that covers a big macro design library entries that encompasses RAM, DRAM, NV Flash, FPGA and MUX implementations. SSD, and 10 units. SCMOS™ shall offer unique opportunities to lead IC and IT technology to an unprecedented new era. The Moore' law shall be revived and new boom can last another decades, it will penetrate deeper to our professional and social lives with simple devices that explore personal and Internet computing. 58] Other main benefits of the generic SCL™ circuits (including mixed CMOS and SCMOS™ SOC embedded ALM blocks) are summarized as follows:

1. Simple circuit configurations.

2. Simultaneous speed, space and power savings.

3. Mixed hard/soft code storage. 4. Embedded RAM, 10, ROM blocks and FPGA for single chip machines.

5. Easy to control RC time constant of every nets it couples.

6. Build-in power stop and quick wake-up.

[00259] These features are important to all high-speed nets especially to PLL/DLL

circuitry in mobile computing. Using SCL™ type logic and PLL can insure fast speed, space saving and power economical.

[00260] The most important concepts with the SCMOS™ IC lie in several areas.

• Active switching element, shifted from transistors to LtSBD™s and integrated transistors, which are extremely high speed in 10s of GHz.

• Class D I-V operating points of switching elements are closest to the origin, say at 0.1 V, 1 μΑ, burning prorated sub-microwatts.

• Logic operation modes changed from static only to static and dynamical.

• The DTL circuits only uses single internal node, and single power supply and small signal swing, which can be 0.6V. There were no stacking transistors, nor high RC data paths.™

• All ALMS blocks can be operated from 5-0.6V, with synchronous and asynchronous clocks.

[00261] All standard CMOS (TTL) functions are retained. Use of the SCMOS™ super macros is at user's discretions. The guidelines are any complex gates having more than 2-way TTL implementations are recommended to switch over to sbDTL™ counter parts.

[00262] Since the SCMOS™ devices and the LtSBD-transistor combined components hold superior benefits both as ideal switching elements and ultimate system building blocks, its library shall cover the whole domain of semiconductor microelectronics infrastructures; prior, present, and future applications. The SCMOS™ devices, which support both the dynamic and static operations with the new super set macros, shall also retain all simple CMOS (TTL) and NV MROM, and Flash circuits. It can overhaul all previous art works of BJT and CMOS implementations, and it can be ported to any fabrication lines from 4 IN to 15 IN manufacturing facilities with old (2D) and new (3D) transistor structures.

[00263] This super set solution is called the SCMOS™ technology. Basically, it is compatible with the processes of CMOS single Vt and Flash Multi-Vt transistors, with the exception of thermal and electrochemical treatments related to the LtSBD™ barrier metals. SCMOS™ devices may extend its applications beyond all ALMS fields to IT, computer and communication chip sets. With embedded multi-cores (i.e., 6T Dual Port Cache RAM cell with 154F2 per R/W bits, ROM with 4F2 per bit, Flash MLC, DSP blocks), and FPGA MUX blocks. The chips local Cache Unit and off chip memory and SSD. It has best speed, multimedia functionality, and capacity. Each of the SoC chips can deliver full audio, video, and data processing and storage services as a subsystem component, and the PCB .

High Density and Fast FPGA

[00264] By implementing SCMOS™ logic, Memory, and SSD macros to FPGA LUT and wiring infrastructures, the MUX functions are drastically upgraded. And SCMOS™ FPGA has powerful embedded units that are speed, space, and power efficient. The gap between logic units and its slower other system units (Analog, Memory, and Storage codes, MUX connectors are closed. A 32KB mask programmed SBD array core in chip with 2 layers of metals can be built, and it reads instruction codes in GHz performance. This NV block, standard logic gates, and multi-KB SRAM core shall be adequate to support most of the multi-media controller functions. Therefore the various system units can work together smoothly at least in the mobile small systems. The chips can be made by a low cost logic product line, which starts at 0.250μιη and down to 90 nm or even 40nm CMOS Process Node..

[00265] Although the present invention has been described in accordance with the

embodiments shown, one of ordinary skill in the art will readily recognize that there could be variations to the embodiments and those variations would be within the spirit and scope of the present invention. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.

Examples of SCMOS Implementations

[00266] In one aspect, this application discloses a low voltage threshold integrated circuit that includes a single and/or polysilicon substrate, one or more low barrier or high barrier Schottky diodes formed within the substrate, and one or more fixed threshold or variable threshold complementary transistors formed within the substrate. A respective Schottky diode shares a common terminal with a respective complementary transistor. In some implementations, the one or more Schottky diodes and one or more complementary transistors are formed and interconnected to create one or more macro circuit functional blocks.

[00267] In some implementations, the low voltage threshold integrated circuit further includes polysilicon film resistors, diffused ion-implanted pockets, capacitors and metal wiring tracks to interconnect with the one or more Schottky diodes and one or more complementary transistors to deliver specific logic, memory, storage and timing control macro functions.

[00268] In some implementations, at least one macro circuit block is from the group of RF, analog and digital circuit blocks consisting of: a memory device, a hardwired or field programmable memory device, a timing detector, a phase detector, an audio signal detector, a video signal detector, a text signal detector, a wireless signal detector, a rectifier, a decoder, a mixer, a multiplexer, a signal filter, a separator, a charge pump, a delay element, a circulator, a phase splitter, a frequency synthesizer, a phase locker, a D- type flip flop register, a latch, an inverter, a buffer, a counter, a de -multiplexer, an encoder, an adder, a phase coupler and a comparator. Further, in some implementations, at least one macro circuit block is a 4T2D-SRAM™ cell comprising four complementary transistors and two Schottky diodes.

[00269] In another aspect, this application discloses a low voltage threshold integrated circuit that includes a substrate, a fin-type field-effect-3D-transistor (FinFET) structure formed over the substrate comprising one or more fin structures, one or more low barrier or high barrier Schottky diodes formed within the 3D-FinFET structure, and one or more fixed threshold or variable threshold complementary 3D-transistors formed within the FinFET structure. In some implementations, the low voltage threshold integrated circuit further includes polysilicon film resistors, diffused ion-implanted pockets, capacitors and metal wiring tracks to interconnect with the one or more Schottky diodes and one or more complementary transistors to deliver specific logic, memory, storage and timing control macro functions. [00270] In some implementations, the one or more Schottky diodes and one or more complementary transistors are formed and interconnected to create one or more macro circuit functional blocks. Further, in some implementations, at least one macro circuit block is from the group of RF, analog and digital circuit blocks consisting of: a memory device, a timing detector, a phase detector, an audio signal detector, a video signal detector, a text signal detector, a wireless signal detector, a rectifier, a decoder, a mixer, a multiplexer, a signal filter, a separator, a charge pump, a delay element, a circulator, a phase splitter, a frequency synthesizer, a phase locker, a D-type register, a latch, an inverter, a buffer, a counter, a de-multiplexer, an encoder, an adder, a phase coupler and a comparator. Alternatively, in some implementations, at least one macro circuit block is a 4T2D-SRAM™ cell comprising four complementary transistors and two Schottky diodes.

[00271] In another aspect, this application discloses a low voltage threshold integrated circuit that includes a fully depleted silicon-on-insulator (FD-SOI) substrate (see FIG.2A), one or more low barrier or high barrier Schottky diodes formed within the substrate, and one or more fixed threshold or variable threshold complementary transistors formed within the substrate. In some implementations, the low voltage threshold integrated circuit further includes polysilicon film resistors, diffused ion- implanted pockets, capacitors and metal wiring tracks to interconnect with the one or more Schottky diodes and one or more complementary transistors to deliver specific logic, memory, storage and timing control macro functions.

[00272] In some implementations, the one or more Schottky diodes (LtSBD™s) and one or more complementary transistors are formed and interconnected to create one or more macro circuit functional blocks. Further, in some implementations, at least one macro circuit block is from the group of RF, analog and digital circuit blocks consisting of: a memory device, a timing detector, a phase detector, an audio signal detector, a video signal detector, a text signal detector, a wireless signal detector, a rectifier, a decoder, a mixer, a multiplexer, a signal filter, a separator, a charge pump, a delay element, a circulator, a phase splitter, a frequency synthesizer, a phase locker, a D-type register, a latch, an inverter, a buffer, a counter, a de-multiplexer, an encoder, an adder, a phase coupler and a comparator. Alternatively, in some implementations, at least one macro circuit block is a 4T2D-SRAM™ cell comprising four complementary transistors and two Schottky diodes.

[00273] In another aspect, this application discloses a low voltage threshold integrated circuit (see FIG.4) including a substrate, one or more low barrier or high barrier Schottky diodes formed within the substrate, and one or more fixed threshold or variable threshold complementary transistors formed within the substrate. The one or more Schottky diodes comprise a mid-band barrier metal or metal silicide.

[00274] In some implementations, the mid-band barrier metal or metal silicide to build LtSBD's comprises one or more of the group consisting of: Ti, Co, Ni, WSi2, CoSi2, NiSi2, TiSi2, and TaSi2.

[00275] In some implementations, the one or more Schottky diodes (LtSBD™s) and one or more complementary transistors are formed and interconnected to create one or more macro circuit blocks.

[00276] In some implementations, the low voltage threshold integrated circuit further includes polysilicon film resistors, diffused ion-implanted pockets, capacitors and metal wiring tracks to interconnect with the one or more Schottky diodes and one or more complementary transistors to deliver specific logic, memory, storage and timing control macro functions.

[00277] In some implementations, the one or more Schottky diodes (LtSBD™s) and one or more complementary transistors are formed and interconnected to create one or more macro circuit functional blocks. Further, in some implementations, at least one macro circuit block is from the group of RF, analog and digital circuit blocks consisting of: a memory device, a timing detector, a phase detector, an audio signal detector, a video signal detector, a test signal detector, a wireless signal detector, a rectifier, a decoder, a mixer, a multiplexer, a signal filter, a separator, a charge pump, a delay element, a circulator, a phase splitter, a frequency synthesizer, a phase locker, a D-type register, a latch, an inverter, a buffer, a counter, a de-multiplexer, an encoder, an adder, a phase coupler and a comparator. Alternatively, in some implementations, at least one macro circuit block is a 4T2D-SRAM™ cell comprising four complementary transistors and two Schottky diodes. [00278] In another aspect, this application discloses a subsystem including a substrate, and a plurality of devices placed on the substrate. The SCMOS™ process means are developed so that the plurality of integrated circuits are made with a plurality of programming resources, various physical entities of logic, memory, storage and timing control micro functions are placed and may be partially connected. In some

implementations, the devices include a plurality of fixed threshold and variable threshold complementary transistors, complementary Schottky low barrier diodes (CLtSBD™s), poly silicon film resistors, diffused or ion-implanted pockets, capacitors and metal wiring tracks are placed wherein, , by the SCMOS™ circuit means, integrated circuits are formed and completely interconnected with a plurality of programming resources, to deliver specific logic, memory, storage, and timing control macro functions.

[00279] In some implementations, the subsystem includes device isolation by oxide filled trenches, binary threshold and multi-level threshold transistors. Low and high barrier Schottky diodes in its diffusion bed or pocket. In some implementations, by the

SCMOS™ circuit means, we form a new type of re -useable hardwired logic gates to deliver more complex functions for better system advantages. We refer to these macros as SCMOS™ logic gates. Such logic gates exhibit many good features in speed, space, and power saving matrices over conventional same from CMOS. See FIG. 3B. In some implementations, another sub-class of standard cell members is made, and this sub-class of standard cell members do not burn direct current when they are activated. See FIG. 3D (a), (b). In some implementations, another sub-class of standard cell members is made for efficient signal coupling and decoupling between SCMOS circuit in high speed. See FIG. 3D (c).

[00280] In some implementations, by the SCMOS™circuit means, we form a new type of re-useable hardwired 4T2D-SRAM™ cell and core memory macros, that are

distinctively more efficient than the conventional CMOS 6T-SRAM cell. See FIG. 10 a, FIG. IOC, 10E. In some implementations, by the SCMOS™ circuit means, we form a new type of re-useable hardwired 6T Dual Port-SRAM cell and core memory macros, that are distinctively more efficient than the conventional CMOS 6T Dual Port-SRAM cell and core memory macros. In some implementations, by the SCMOS™ circuit means, we form two new types of re-useable hardwired Schottky Pass Transistor Logic (SPTL™) macros that are distinctively more efficient than the conventional CMOS gates.

[00281] In some implementations, by the SCMOS™ circuit means, we developed

LtSBD™ based mask programmable ROM. This is the most compact memory that runs at GHz speed, the bit cell size is 4F ² , and decoder pitch is 2F. It is a NVM that can store important fixed data and video information for source code resides with the processors as I-Cache, leave more room for LI SRAM. This is a unique device unit of its own. 1000X faster than CMOS Flash, cheaper and faster than CMOS SRAM or DRAM.

[00282] In some implementations, the SCMOS™ circuit means, programming resources are much more capable of delivering macro functions using sbDTL™ circuit constructs. . Our invention here is to replace all FPGA CMOS macros by the SCMOS™

replacements. The SCMOS™ version of FPGA is much more efficient in space saving, and gains orders of magnitude system merits in speed, and power savings. So new version of SFPGA™ will be cheaper and more capable. . See FIG. 7A-7D, 7F.

[00283] In some implementations, the SCMOS™ circuit means, programming resources are much more capable of delivering macro functions using sbDTL™ circuit constructs. .The SCMOS™ gates, RAM, ROM, are implemented with LtSBD™s and inverters. It has the smallest footprints, wide input Fan-In and immune to Fan-out loads. The performance simulations show some 200X advantages in performance and area power- saving for wide signal span in each stage, and MUX widest trees with powerful speed gains. See FIGS. 7G and 7H.

[00284] The CMOS MUX is based on transistor Fan-In and Fan-out. And selection

decode is based on pass transistor serial tree branches. The transistor counts are often huge and slow, if normally Fan-in is two or three way. The SCMOS™ gates can support 4 bit, 8 bit, or 16 bit each stage, complete certain embedded Memory blocks, ASIC macros, and network signals for bridging, routing, and selective data processing

[00285] In some implementations, programming means and resources may include state tables, virtual machines, setup or initialization and test procedures, data access, transport, and storage algorithms, protocols. These requirements may be provided in the embedded LtSB™D MROM. [00286] In some implementations, the hardware constructs are comprised of hardwired Schottky CMOS Logic (SCL™) gate array, CPU and processors, various NV memories, main, and simultaneously read and write dual port, Cache memory units, timing or phase detector, audio, video, and test signal detector, rectifier and decoder, mixer, multiplexer, signal filter and separator, charge pump, delay element, phase splitter, frequency synthesizer, phase locker, and D-type register, wherein these circuits are intrinsically faster but easier to control, operated with lower supply voltage, and have less sensitivity to body-effects.

[00287] In some implementations, the phase detector is configured from simple SCL™ type NAND gates, which replace conventional CMOS-TTL gates having less than 2-way logic or serial gating, wherein the charge-pump output of claim 7 directly couples to the current source of the delay element with a positive feedback in stage delays.

[00288] In some implementations, the delay element chain forms a voltage-controlled oscillator via a programmable mux and its selected long or short loop paths, wherein one can form a 12 MHz or lower frequency oscillator, which can be stabilized by an off-chip Resistor-crystal tank control at chip/PCB boundaries.

[00289] In some implementations, the delay element may form on-chip free running internal oscillator with extremely high frequency up to several GHz, wherein it was then divided to mid or lower frequency (10s- 100s MHz) by conventional D-type flip-flop means for monitoring and control.

[00290] In some implementations, the phase splitter can subdivide the low frequency delay period therefore placing the switching edge of the low frequency oscillator waveform accurately with controlled spacing, wherein two frequency synthesis means are proposed to form ultra high frequency pulses (several GHz) by combining the delayed edges with SCL™ type NOR gates.

[00291] In some implementations, the hardware constructs are comprised of software driven SCL™ gate arrays, IO transceivers, terminators, capacitors, and wherein the switching transistor is of the variable threshold type. In some implementations, the hardware constructs are comprised of software driven SC™L gate arrays, IO

transceivers, terminators, capacitors, wherein the switching transistor is of the fixed threshold type. In some implementations, the hardware constructs are comprised of software driven SCL™ gate arrays, 10 transceivers, terminators, capacitors, wherein the switching transistor is of the variable threshold type, and the SCL™ unit act as analog signal comparator. In some implementations, the analog comparator construct includes a pass transistor construct for sampling reference voltages. In some implementations, the hardware constructs are comprised of software driven SCL™ gate arrays, 10

transceivers, terminators, capacitors, wherein the switching transistor is of the variable threshold type, and the switching transistor may store multiple bits with other dedicated apparatus and software links. In some implementations, the dedicated apparatus consists of input status registers, charge pump circuitry, and stored software means in the local memory arrays.

[00292] Alternatively, in some implementations, the hardware construct are comprised of software driven SCL™ gate arrays, 10 transceivers, terminators, capacitors, wherein the switch transistor is of the variable threshold type, and the SCL™ unit may process multi- value logic operations with binary, ternary and quaternary operators. In some

implementations, the hardware constructs are comprised of software driven CMOS-TTL gate arrays, 10 transceivers, terminators, capacitors. In some implementations, the hardware constructs are comprised of hardwired conventional logic and memory units including but not limited to CMOS-TTL gate arrays, Register files, embedded RAM, ROM and Flash cores. In some implementations, the hardware constructs further comprise dedicated programming facilities of voltage and current sources, clock and oscillators, state machines, counters, to implement and control both cell wise and block wise cell operations, which is shared to alter the charge storage or Vt threshold of the selected device(s) in the logic and (Flash) memory circuitry.

[00293] In some implementations, chip sets which adopt the above architecture yield the densest logic and memory circuitry, and which also has low power, high speed, and offers great flexibility.

[00294] In some implementations, the Complementary Schottky low barrier diodes

(CLtSBD™s) are formed in poly Si thin film layers over single crystal wafers; that are situated in the overlapped layers with the transistor bulk Si crystal, wherein the LtSBD™ arrays may be stacked 3D in vertical dimensions to yield spatial savings. [00295] In some implementations, the Complementary Schottky low barrier diodes

(CLtSBD™s) are formed in poly Si thin film layers over single crystal wafers; the diodes include:

• Being formed in other mix of thin film layers such as low cost screened composite mixtures of photon voltaic films in um dimensions of transparent and reflective layers that shall generate electricity between stacked layers and regions. Therefore, certain photon voltaic effect may be developed and manipulated to generate electricity, providing or supplementing on-chip activities, or charging the batteries; Being formed in a new design of low cost apparatus, such as stacked glassy films or stainless steel panels, other than the conventional highest grade of Si chips. And SCMOS™ chips, due to its highest efficiency, may be employed to manipulate energy conversion tasks.

[00296] In some implementations, the SCMOS™ microelectronics chips may be

employed in the Bio-lab-chip assemblies with bio fluid control apparatus. Its low cost, low power nature and 3D cell motion manipulations by electro-mechanical controls provide ideal medical lab environments for bio-cell characterizations, and life science experiments.

[00297] In some implementations, the SBD process means supports the complementary Schottky low barrier diodes and CFET structures are compatible with those for making the Fin FET, and FD FET SOI structures. All of the SBDs can be placed on the transistor Drain bed as depicted in FIG. 2B.

[00298] In some implementations, the SCMOS™ circuit means are applicable to the SCMOS™ functional macros disclosed above can be scaled down and fine tuned with the new process means of the 3D transistor technology. Circuit means can apply to fine tune SCMOS™ products at the new advanced process lines.

[00299] Advantages of the SCMOS™ technology, circuits and processes will be apparent to those skilled the art in view of the descriptions included herein. Without any effort to provide an exhaustive list, some advantages and benefits are described below.

[00300] Referring to Figures 3A and 3B, in some implementations, at least one of the complementary transistors and the at least one of the Schottky diodes are part of a synchronous logic gate. [00301] Referring to Figure 3C, in some implementations, this dynamic driver can be used under the following conditions:

(a) use a dynamic Power or GND signals (with other supply floating) when activated during a synchronized time window(s).

(b) Connection 1, which is between MP4 and MN4 drains may be removed (Open Circuit). Thus the output signal is either GND or VCC state upon 1 or 0, with 1 Vtd offset. The above drivers are applicable to all bus nets, which desire light load capacitances, such as BL and BLB, Data write gate outputs.

[00302] Referring to Figures 5C - 5F, In some implementations, these are synchronous gates for the control logics and memory peripheries, CPU datapaths and other Logic blocks. All such gates use a similar combination of LtSBD's and MOSFET's with their threshold Vtp and Vtn optimized for this purpose.

[00303] Referring to Figures 3D, 3E, 3F & 31, in some implementations, these are the asynchronous SCL™ gates used in all Logic blocks, which do not rely on single or a network of clocks for proper operation. The asynchronous gates are either custom- designed or pre-built and characterized in a Standard Cell Library, all integrated in a suite of EDA tools for the front-end design of the Logic (Behavioral and/or RTL code/description), for different forms of Logic Synthesis (RTL, System Level or even C/C++, or a high-level software language), and for the physical (IC Mask Layout or ICML) and back-end design to create the set of photomask for manufacturing Integrated Circuits (ICs) or "chips".

[00304] Referring to Figures 3D, 3E, 3F & 31, in some implementations, these

Asynchronous SCL™ gates rely on pairing a set of LtSBD™s with a Source-Follower string of N or P MOSFET's (NSF or PSF). Each gate input is connected to either a P- LtSBD and NMOS in a PSF pull-down to GND or a N-LtSBD and a PMOS in a NSF pull-up to VDD. The NSF and PSF occupy a small area due to having no contact between the drain and the source of adjacent MOSFET's. Also, their source follower operation has no Miller effect. In some high-speed Logic cases, when the input signals can have a guaranteed fast transient, the LtSBD's are drawn in the ICML with sufficient lead overlap or edge capacitance with respect to the IG node further drawn with a proper series resistance effect, or with the proper placement of the input Zeros to the corresponding Pole of the IG either to GND or VDD, as well as the proper gain and effective impedance/admittance of the feedback loop (MNnF's or MPnF's), the N/PSF can be removed. This further reduces the size of SCL gates, thereby expanding the advantage of SCL™ gates over their CMOS counterparts.

[00305] Referring to Figure 3F, in some implementations, Several sets of N/P-LtSBD's with or without their corresponding P/NSF can be placed in series and parallel to build AND-OR gates to perform the same Logic operation as CMOS complex gates. Proper feedback and placement of Poles and Zeros insurae a drastic advantage over their CMOS counterpart. In addiition the complex gating technique can be very effectively to larger/wider sets of Logic inputs than CMOS can effectively offer for specified speed and power constraints.

[00306] Referring to Figures 3D, 3E, 3F & 31, in some implementations, SCMOS™

allows reintroduction of very effective Wired AND and OR Logic design techniques, which were practically removed when CMOS replaced TTL and bipolar VLSI technologies. Asynchronous SCL™ implements a new form of Wired AND and OR Logic, combining P/N-MOSFETs and P/N-LtSBD™s, and referred to as WASCL™ and WOSCL™. Like the older type, WASCL™ and WOSCL™ allow drastic reduction in the number of signal nodes or nets, which must be routed or connect the equivalent CMOS gate to implement various Logic functions. The resulting PPA improvement can be dramatic. For example, wide multiplexers, ie. 32 or more inputs to 1, built in SCMOS™ achieve a 60% to 80 % Area savings over and have a much easier and effective ICML footprint for interconnections than their CMOS counterpart.

[00307] Referring to Figures 3D, 3E, 3F & 31, in some implementations, Asynchronous SCL™ gates, WASCL™ and WOSCL™ blocks can be designed with break-before make techniques to implement another type of Logic geared towards minimizing transient power disspation as much as possible: Schottky CMOS Break Before Make Logic ("SCBBML™"). Compared to its CMOS counterpart SCBBML has smaller area. It can applied or combined with subthreshold or weak-inversion design techniques for nano-power applications like electronic watches and other applications like energy harvesting where an extremely small source of power is only available. SCBBML™ and other SCMOS™ circuits can minimize transient currents, an essential advantage for a variety of applications requiring very high frequencies and switching speeds as well as low/controlled EM noise injection in the GND and VCC lines, or AC coupling into adjacent sensitive signal lines, or EM radiation in the IC surroundings, thereby helping the EMI limits.

[00308] Figures 3H & 31 illustrate the Fan-in immunity of SCL™, both for synchronous and asynchronous gates. There is little difference between the propagation delays of 2- input to 9-input NAND or NOR SCL™ gates. In fact, the SCL™ Standard Cell Library can be designed so that all the NOR and NAND gates have almost and practically the same propagation delay, even for low-to-high and high-to-low logic transition. In addition, the variations of this delay versus fluctuations and electrical characteristics of the manufactured devices, the die junction temperature and its gradient and the supply voltage, commonly referred to as PVT variations, is much less than the CMOS counterparts. This feature brings tremendous increase in efficiency to the IC design process. It allows reduction in the number of iterations and facilitates the convergence towards the functional and timing specifications of almost all Logic blocks. The design validation and verification schedule is also reduced. Imagine the not-so-infrequent case of replacing a 2-input NAND gate by a 9-input NOR gate due to some very common design change in the middle of a tight design schedule. In the prior art, the impact of a design change on a VLSI CMOS design is usually catastrophic, requiring the redesign from RTL to circuit timing details of a significant block of Logic. In contrast, this replacement in the SCMOS™ implementation and over the same set of design tasks adds at worst only a small delay to the project schedule. Moreover, the ICML of the SCL™ gates is drawn to minimize the impact of changing the gate Fan-in. The ICML changes in the SCMOS implementation are much easier and quicker than in the CMOS counterpart. Therefore, SCMOS™ brings significant Time-to-Market Savings ("TMS") over VLSI CMOS. In some cases this TMS of SCMOS™ is even more valuable than its PPA advantage.

[00309] Figures 3H & 31 illustrate simplification of the EDA process of implementing a VLSI block or function from its behavioral model to its Logic gates and IC devices. The process consists of Logic Synthesis, either traditional RTL or more advanced System Level techniques or design flow. The CMOS implementation of a function block must be broken in 2-input NAND and NOR gates, with some exception to no more than 3- input gates. The effects on timing and areas play against each other. The EDA tools must implement sophisticated algorithm to effectively mitigate many cases and negative side effects. SCL Synthesis mainly consists in minimizing Logic Look-up Tables

irrespectively of the gate Fanin and converging towards the widest gates, and minimizing the number of routed signals. The integration of the Logic Synthesis with the ICML Place-and-Route is greatly simplified and easier to quickly achieve timing convergence, Even though, the current EDA tools developed and used for VLSI CMOS will be adequate and mostly work well for SCMOS, the simplification brought by SCL will allow simpler and more effective Logic Synthesis for this new type of VLSI

implementation.

[00310] Referring to Figures 4A, 4G, 6C, 6D, the Applicant has invented the SCMOS™ 4T2D-SRAM™ bit cell, memory core block and its periphery control circuits for SRAM chips, of any size, standalone or embedded. Each of these 4T2D-SRAM™ units, wether standalone and/or as a whole system solution is far more efficient and advantageous in Performance/speed, Power and Area savings (PPA) than the standard 6T-SRAM units. Avantages of Applicant's SCMOS™ technology are consistent regardless of using planar CMOS CFET or the 3-D FinCFETs. To make a better system solution, our arrays already have the smallest bulk areas. We can enhance further this advantage if inter- wiring planes can provide abundant wiring resources such as contacts, vias, narrow wiring tracks, and Capacitor films. So we claim that our array solutions can improve with tighter thin film metal related design rules. Therefore, the components density and bandwidth capacity are greatly increased by extending Ml rules to multiple planes (say M1-M9), all vias can be stacked over oxide areas without much metal layer borders.

[00311] Referring to Figures 41 - 40, in some implementations, embedded SRAM is the bit-cell implementation of a dual port SRAM array for the graphics and display chip sets, where re -useable SRAM are improved by circuit means using LtSBD and CFET integrations.

[00312] Figures 5 A - 5H show one implementation of a Mega core application for

the NVMPROM™. Here we have the world unique MPROM which is highest density and capacity, and runs fastest. The bit density is as good as the binary Flash, 4F ² per bit, speed is 10,000 times faster than Flash, cost is the least for any memory technology. It may be used for housing non- volatile (NV) source code, fixed data for images, and audios. You can retain and access any personal data, legal and medical files, story books etc.

[00313] Referring to Figures 7A - 7H, in some implementations, many ASIC hard macros in FPGA can be implemented by SCMOS™ devices. Since SCMOS™ is highly efficient in bulk and wiring areas, reduction of total nets, and eliminating wiring traffics. We proved that it can improve Mux space, power, and speed. They are up to orders of magnitude better than the CMOS same, along each PPA axis.

[00314] Referring to Figures 11 A - 1 IF, in some implementations, the LtSBD™ may be used as high bulk resistor if naturally lightly doped. We showed it can be used in class B/D Op amps, A/D and D/A converters, power multiplier, charge pump circuits. The 0.1 Vtd is near perfect to pick up any digital switching signals. And the bulk area is the smallest ever known. The converter will have the highest bandwidth ever made in any microelectronic apparatus. The network can be small or large as the loading calls for. The rectification efficiency is near perfect, and much more better than PN junction diodes, or even exceed the old SBD which had Vtd at 0.7 Volt

[00315] Figures 12A - 12D show implementations of a PLL circuit running at 2.4 GHz (typical) and higher frequencies, using a synchronous signal chopper from 30 MHz or other frequency crystal Ring Oscillator. The biggest advantage is we only use inverters and single phase clocks. So both the power and clock resource reduced drastically via SCMOS™ techniques.

[00316] Referring to Figure 13, in some implementations, DRAM has more timing

control circuits than any other memory product chips. IO bus nets are also multiplexed and highly capacitive. Therefore, IO signal swing, simplify the PLL and clocking facility will result in PPA reductions as well. We can use LtSBD™ switching elements to reduce transistor nets, we are using 1.25V power supply, and high Fanln and FanOut sbDTL™ control circuits.

[00317] While particular embodiments are described above, it will be understood it is not intended to limit the disclosure to these particular embodiments. On the contrary, the disclosure includes alternatives, modifications and equivalents that are within the spirit and scope of the appended claims. Numerous specific details are set forth in order to provide a thorough understanding of the subject matter presented herein. But it will be apparent to one of ordinary skill in the art that the subject matter may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the embodiments.

[00318] The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used in the description of the disclosure and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms "includes," "including," "comprises," and/or "comprising," when used in this

specification, specify the presence of stated features, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, operations, elements, components, and/or groups thereof.

[00319] As used herein, the term "if may be construed to mean "when" or "upon" or "in response to determining" or "in accordance with a determination" or "in response to detecting," that a stated condition precedent is true, depending on the context. Similarly, the phrase "if it is determined [that a stated condition precedent is true]" or "if [a stated condition precedent is true]" or "when [a stated condition precedent is true]" may be construed to mean "upon determining" or "in response to determining" or "in accordance with a determination" or "upon detecting" or "in response to detecting" that the stated condition precedent is true, depending on the context.

[00320] The foregoing description, for purpose of explanation, has been described with reference to specific embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical applications, to thereby enable others skilled in the art to best utilize the disclosure and various embodiments with various modifications as are suited to the particular use contemplated.