The invention relates to a supply voltage circuit having an input for connecting an input alternating voltage and an output for tapping off an output power having a predetermined value, comprising a zero crossing detector, connected to the input, for delivering zero crossing pulses at the zero crossings of the input alternating voltage and a timing circuit which is controlled by the zero crossing pulses and which, after a time period following the zero crossing pulses and corresponding to the predetermined value of the output power, supplies control pulses to the control circuit of a triac circuit interconnected between the input and the output of the supply voltage circuit. Such a supply voltage circuit is known from US Patent Specification 4,528,482.

In this case, the zero crossing detector controls a timing circuit which comprises a monostable multivibrator having variable timing and a monostable multivibrator having a fixed timing. The output pulse of the last-mentioned multivibrator then controls a triac which supplies an output voltage to a load in accordance with the principle of phase gating of the input voltage, it being possible to control the value of the output voltage by means of adjusting the timing of the first-mentioned monostable multi¬ vibrator. This known circuit has the disadvantage that, especially in the case of low values of the output power, the regulation is unstable, and this is manifested, for example, when a fluorescent tube or an electric motor is supplied. The fluorescent tube is going to flicker at low voltage, while the motor will not run smoothly with such a voltage but is going to vibrate. The instabi¬ lity may even result in a half cycle of the input voltage not being affected by the regulation. This will be unacceptable for neon tubes since they switch off if a half cycle is absent.

The object of the invention is to provide a supply voltage circuit of the type mentioned in the preamble in which the above- mentioned disadvantages are avoided.

According to the invention, this object is achieved in that a set and reset circuit which resets and sets the timing

circuit prior to the zero points of the input alternating voltage is connected between the zero crossing detector and the timing circuit.

This always ensures that, at every zero crossing of the input alternating voltage, the signal supplied to the control circuit of the triac circuit is always zero, with the result that the triac is reliably switched off at the zero crossings.

The triac will therefore always be switched off if the voltage across it is zero. This prolongs the duration of life of the triac.

The result is additionally achieved that a phase gating is carried out in every half cycle of the input alternating voltage. This achieves a very stable regulation down to very low output powers. In this connection it has been found that, if the controllable supply voltage circuit according to the invention is used for motors, the motors run vibration-free and smoothly even at very low voltages and, therefore, low rotational speeds.

In addition, it has been found that the nature of the load of the supply voltage circuit has no effect on the regula- tion. An inductive or capacitive load does not present any problems at all.

In addition, if the supply voltage circuit is used for fluorescent tubes, no flickering occurs at low voltage, while the intensity of a neon tube supplied by the circuit can be stably regulated down to very low values, which was hitherto impossible.

According to an embodiment of the invention, the set and reset circuit is arranged to deliver output pulses, of which the leading edges correspond to the leading edges of the zero crossing pulses and the trailing edges occur prior to the zero crossings of the input alternating voltage, in response to the zero crossing pulses, the leading edges of the output pulses resetting the timing circuit and the trailing edges thereof setting it.

In a further elaboration of the invention, the set and reset circuit incorporates a differentiator whose output is connected to the input of a threshold circuit.

Preferably, the threshold circuit is formed by a NAND gate whose inputs are connected together.

In another embodiment of the invention, the zero crossing detector comprises a series circuit of a resistor and a parallel circuit of two transistors of mutually opposite conduction type and a voltage source connected in parallel with the series cir- cuit, the connecting point between the transistors and the voltage source being connected to the first input terminal of the zero crossing detector, while the other terminal of the voltage source is connected to earth, the bases of the transistors being coupled to the second input terminal of the zero crossing detector in a manner such that, at the zero crossings of the input voltage, both transistors are in the non-conducting state and, at positive and negative values of the input voltage, one of the transistors is always in the conducting state, the output terminals of the zero crossing detector being coupled to the terminals of the resistor. According to the invention, the last-mentioned embodiment is further elaborated in a manner such that the emitter and collector of the first and second transistor respectively are connected to each other and the first input terminal of the zero crossing detector, while the collector and emitter of the first and second transistor respectively are connected to each other and the resistor, while the base of the first transistor is connected to the second input terminal of the zero crossing detector via a base resistor.

In yet a further elaboration, the base of the second transistor is connected to the collector of a third transistor and the base of the third transistor is connected to the first input terminal and the emitter thereof is connected, on the one hand, to the base of the first transistor and, on the other hand, to the first input terminal of the zero crossing detector via an emitter resistor.

Preferably, the connecting point between, on the one hand, the first and second transistors and, on the other hand, the resistor is connected to the two inputs of a NAND gate, while the output thereof is connected to the unearthed output terminal of the zero crossing detector.

According to yet another embodiment of the invention, the base circuit of the first transistor incorporates a mains filter.

The timing circuit according to a simple embodiment of the invention comprises a series circuit of a capacitor and a resistor, the free terminal of which is connected to earth, while the connecting point of the capacitor and the resistor is connec- ted to the input of a voltage comparator, whose other input is connected to a reference voltage and whose output is coupled to the control circuit of the triac circuit.

Preferably, the voltage comparator is formed by a NAND gate, one input of which is connected to the connecting point of the capacitor and the resistor, while the other input is connec¬ ted to the first input terminal of the zero crossing detector via a resistor and to earth via a capacitor.

To drive the triac correctly, the output of the timing circuit is coupled to the gate electrode of the triac via a NAND gate, the inputs of the said gate being mutually connected.

The invention will be explained in more detail below with reference to the drawings. In the drawings:

Figure 1 shows a block diagram of an embodiment of the invention; Figure 2 shows a preferred embodiment of the supply voltage circuit according to the invention;

Figures 3a-h show the pulse shapes of the signals at diverse points of the circuit according to Figure 2;

Figure 4 shows a preferred embodiment of the zero crossing detector according to the invention;

Figure shows a graph in which diverse parameters of the controllable supply voltage circuit are plotted for two fluores¬ cent tubes as a function of the light intensity thereof; and

Figure 6 shows the application of the invention to a three-phase motor.

From Figure 1 it is evident that the supply voltage circuit comprises a zero crossing detector Q to the input of which an input alternating voltage Ui is fed, a set and reset circuit R connected to the output of the zero crossing detector, timing circuit S controlled thereby and a triac circuit T, the control circuit of which is controlled by the timing circuit, while the input alternating voltage Ui connected to the triac circuit is switched through to the output of the triac circuit in

accordance with the phase gating principle in order to tap off a controllable output power Uo.

From the input alternating voltage, the zero crossing detector forms zero crossing pulses whose leading edges occur prior to the zero crossings and whose trailing edges occur after the zero crossings of the input alternating voltage. The set and reset circuit resets and sets the timing circuit prior to the point of time of the zero crossings of the input alternating voltage. After a time period following the zero crossing pulses and which corresponds to the desired value of the output power, the timing circuit supplies control pulses to the control circuit of the triac circuit. This configuration achieves the result that, at the zero crossings of the input alternating voltage, no voltage or current is fed to the gate electrode of the triac. At each zero crossing, the triac will therefore always be reliably switched off, with the result that every half cycle is affected during the regulation, resulting in a stable regulation. To regulate the output power, the time period defined by the timing circuit is adjustable. In addition, the set and reset circuit is designed to deliver output pulses in response to the zero crossing pulses. The leading edges of said output pulses correspond to the leading edges of the zero crossing pulses and the trailing edges of the said pulses occur prior to the instants in time of the zero crossings of the input alternating voltage. The leading edges of the output pulses can therefore be used to reset the timing circuit, while the trailing edges thereof are capable of setting the timing circuit.

A preferred embodiment of the supply voltage circuit according to the invention is shown in Figure 2.

In the embodiment according to Figure 2, the zero crossing detector, which is indicated in Figure 1 by the reference symbol Q, comprises the transistors Ql, Q2 and Q3 and the NAND gate U1A. The set and reset circuit R comprises the series circuit of a capacitor C4 and a resistor R connected to earth, the connecting point of which being connected to a threshold circuit which is formed, in Figure 2, by the NAND gate U1B whose inputs are connec¬ ted to each other and to the connecting point of the said capaci-

- b — tor C4 and the resistor R5. The output, formed by the output of the NAND gate U1B, of the set and reset circuit is connected to a timing circuit which comprises, in the embodiment according to Figure 2, a series circuit of a capacitor C5 and an adjustable resistor PI connected to earth, the connecting point being con¬ nected to one input of a voltage comparator, while the other input of the said comparator is connected to a reference voltage. The voltage comparator is preferably formed by the NAND gate U1C shown in Figure 2. One input of said gate is connected to the capacitor C5 and the adjustable resistor PI, while the other input of said gate is connected to the connecting point of the series circuit of the resistor R7 and the capacitor C6, which series circuit is connected, on the one hand, to the positive potential of the line 2/N and, on the other hand, to earth. The capacitor C6 is used only for the starting phase when switching on a fluorescent tube. For other purposes, for example supplying a motor, the capacitor can be omitted, the connecting point of the resistor R7 and the input of the gate U1C being connected directly to the said potent¬ ial. The capacitor C6 disables the gate U1C in the said phase, with the result that, via the gate UID, the triac is kept in the conducting state for a time determined by the resistor R7 and the capacitor C6 in order to have the fluorescent tube started.

To drive the gate electrode of the triac Q4 correctly, use is made of the NAND gate UID, the inputs of which, which are connected to each other, are connected to the output of the gate U1C. The input alternating voltage is fed to the input terminals 1/L1 and 2/N respectively, which input voltage is switched through to the output Uol and Uo2 respectively of the supply voltage circuit by the triac in accordance with the phase gating princip- le.

The operation of the supply voltage circuit according to Figure 2 will be explained below with reference to the pulses shown in Figures 3a-h.

Figure 3c shows the zero crossing pulses which are delive- red by the zero crossing detector at the point B of the circuit. Said pulses are fed to the series circuit of the capacitor C4 and the resistor R5.

During the rising edge of the zero crossing pulses at the point B of the circuit, the signal at the point C will change directly into a logic 1. At that instant the capacitor C4 is discharged, as a result of which the impedance is virtually zero ohm. A voltage division now occurs between the impedance of the capacitor C4 and the much higher resistance value of the resistor R5, resulting in the direct changing of the signal at the point C into a logic 1. Said signal will change into a logic zero accor¬ ding to an exponential power as a function of the RC time constant of the said capacitor. The signal at the point C is shown in Figure 3d.

At the instant of the rising edge of the pulse at the point C of the circuit, the output signal of the gate U1B at the point D of the circuit will change into a logic zero when the switching level of the NAND gate U1B is reached, which level is indicated in Figure 3d as a horizontal broken line. At the instant when the switching level of the gate U1B is passed in the downward direction at the point C of the circuit, the signal at the point D will change from a logic zero into a logic 1. The pulse at the point D of the circuit is shown in Figure 3e.

The pulse, shown in Figure 3e, which occurs at the point D of the circuit is fed to the series circuit of the capacitor C5 and the adjustable resistor or potentiometer PI. When the rising edge of the pulse at the point D of the circuit occurs, the signal at the connecting point E of the said capacitor and potentiometer will immediately change from a logic zero into a logic 1. At said instant in time, the capacitor C5 is discharged, as a result of which the impedance thereof is virtually zero ohm. A voltage division now occurs between the impedance of the capacitor C5 and the set resistance value of the resistor PI. The logic 1 which occurs at the point E of the circuit will change into a logic zero in accordance with an exponential power depending on the RC time constant of the series circuit of the resistor PI and the capaci¬ tor C5. The signal at the point D of the circuit is shown in Figure 3f-

As has already been explained, after the switching-on of the circuit and the start phase, one input of the gate U1C is connected to a positive voltage via the resistor R7. The signal

_ g _

at the point E of the circuit is supplied to the other input of the gate UIC. During the rising edge of the signal at the point

E, a change from a logic 1 to a logic zero will occur at the output F of the gate UIC. The shape of the signal at the point F of the circuit is shown in Figure 3g- At the instant when the signal at the point E of the circuit passes the switching level of the gate UIC in the downward direction, a change from a logic zero to a logic 1 will take place at the output of the said gate.

At the point G of the circuit, the NAND gate UID produces a signal which is inverted with respect to the signal at the point

F. This inverted signal is shown in Figure 3h. The pulses shown in Figure 3h are fed to the gate electrode of the triac via the resistor Rδ. It is clear that the width of the negative pulses shown in Figure 3h depends on the RC time constant of the capacitor C5 and the potentiometer PI. The triggering cycle of the triac can therefore be controlled by adjusting the potentiometer PI.

In addition, it is evident from Figure 3e and Figure 3 that, during the falling edge of the pulse shown in Figure 3e, the timing circuit C5. PI and UIC is always reset to zero and during the rising edge is set again and, to be specific, always prior to the occurrence of the zero crossing of the input signal shown diagrammatically in Figure 3a. The pulses occurring at the output of the abovementioned timing circuit ensure, again after an inverting action, that no control voltage occurs at the triac Q4 during the zero crossing of the input signal shown in Figure 3a, with the result that, at every zero crossing of the input signal, the triac is always switched off. As a result of this, a very stable regulation is achieved, even with low output voltages across the points Uol and Uo2.

Figure 4 shows a zero crossing detector according to the invention which has a simple configuration and comprises only a few components. The input voltage for the zero crossing detector is fed to the input terminals 1 and 2, while a very narrow or short pulse which accurately indicates the zero crossing of the input voltage is tapped off at the output terminals 3 and 4. The most important components are the parallel-connected transistors Ql and Q2 which are of the PNP and NPN conduction type respective-

ly. The emitter and collector, which are connected to each other, of the transistors Ql and Q2 respectively are connected to the input terminal 2, while the collector and emitter respectively of the said transistors are connected to each other and to a connect- ing terminal of the resistor R4 whose other connecting terminal is earthed. Connected in parallel with the series circuit comprising the parallel circuit of the transistors Ql and Q2 and the resistor R4 is a voltage source S which feeds the supply to the transistors Ql and Q2. The transistors Ql and Q2 must be controlled by the input terminal 1 in a manner such that, in the positive cycle of the input voltage, the transistor Ql must be in the off-state, while the transistor Q2 is, on the contrary, conducting. In the negative cycle of the input voltage precisely the opposite occurs. At the instant of the zero crossing of the input voltage, both transis¬ tors Ql and Q2 must be in the off-state. In the design in Figure 4, the control mentioned is obtained by connecting the base of the transistor Ql via a resistor R2, also termed a measuring resistor, to the input terminal 1. In this case, the transistor Q2 is controlled by means of a transistor Q3, the collector of the last- mentioned transistor being connected to the base of the transis¬ tor Q2. The base of the transistor Q3 is connected directly to the input terminal 2. The emitter of the transistor Q3 is connected, on the one hand, directly to the base of the transistor Ql and, on the other hand, is connected to the input terminal 2 via a resis¬ tor R3« The output terminals 3 and 4 are connected via a NAND gate U1A across the resistor R4, the inputs of the said gate being connected to each other.

The measuring resistor R2 decreases the voltage of the input terminal 1 in a manner such that the transistor Ql can be triggered.

There are three states which may occur in the circuit:

The potential of the input terminal 1 is higher than that of the input terminal 2. - The potential of the input terminal 2 is higher than that of the input terminal 1.

- The potentials of the input terminals 1 and 2 are equal to each other.

_ _1£) _

If the potential of the input terminal 1 is higher than that of the input terminal 2, the base voltage of the transistor Ql is higher than the voltage between the emitter and earth. As a result, the transistor Ql is in the off-state. In this state, the transistor Q3 is, on the contrary, conducting, as a result of which the transistor Q2 is also driven into the conducting state. As a result of this, a logic 1 is produced across the resistor R4. If the potential of the input terminal 2 is higher than that of the input terminal 1, the transistor Ql conducts, but the transistors Q3 and Q2 do not. In this case, too, a logic 1 occurs on the resistor R4.

However, if the potentials of the input terminals 1 and 2 are equal to each other, a zero crossing of the input voltage occurs. At the instant when the absolute value of the input voltage becomes less than the offset voltage of the transistors, the transistors Ql and Q3, and therefore also Q2, enter the off- state. The consequence of this is that a logic zero appears across the resistor R4. Only when a logic zero occurs across the resistor R4, does a logic 1 appear on the outputs 3 _t 4 of the zero crossing detector.

Known zero crossing detectors comprise an analog compara¬ tor, a reference voltage being connected to one input thereof. The input voltage of the detector is fed to the other input of the comparator via a transformer and diodes. The output voltage of the comparator is a wide pulse, with the result that the zero crossing is not determined accura¬ tely. The width of the pulse could possibly be reduced by keeping the reference voltage low, but the width of the pulse will never be less than a value which is determined by the offset voltage of the diodes, which diodes have, in general, an offset voltage of approximately 1.4 volt. Said offset voltage becomes even higher if the load of the diodes is high. In addition, a transformer is necessary for controlling the diodes.

Since the offset voltages of the transistors are only a fraction of 1 volt and are less load-dependent than those of the diodes, quite a sharp pulse with a width of approximately 10 microseconds is produced on the output of the zero crossing detector according to the invention at the zero crossing of the

_ _

input voltage. In addition, the input signal to be supplied can be coupled directly to the input of the zero crossing detector, i.e. without transformer.

Preferably, the transistors Ql and Q2 are driven in a manner such that the voltage across the resistor R4 is flattened at the peaks. If desired, the pulse can be sharpened further in a manner not shown by using transistor amplifiers at the output of the detector.

The zero crossing detector described above is used in the circuit according to Figure 2.

In the input circuit of the zero crossing detector, use is made of a mains filter which comprises the self-inductance LI and the capacitor C3« The voltage source of Figure 4 is formed, in the circuit according to Figure 2, by the series circuit of the capacitor Cl and the resistor Rl and a diode Dl, while a series circuit of a diode D2 and a parallel circuit of a zener diode D3 and a capacitor C2 is connected across the diode Dl. One side of the capacitor C2 is connected to earth.

As a result of the admittance of the capacitor Cl, a large alternating voltage is produced across it of approximately 205 volts rms if the input of the zero crossing detector is connected directly to the 220-volt mains.

If the input terminal 1/L1 is positive with respect to the input terminal 2/N, the voltage source or supply makes no use of it. In order to avoid short circuiting in this half of the cycle, the resistor Rl is incorporated in the circuit. If, how¬ ever, the input terminal 2 is positive with respect to the input terminal 1, there occurs across the zener diode D3 of, for example, 12 volts, a voltage of said value. The capacitor C2, which is connected in parallel with the zener diode, is charged up and is used in the other half of the cycle as a buffer for the supply. The supply voltage of the transistors is present between the input terminal 2/N and earth. The input terminal 2, for example the neutral N of the mains, is the positive terminal of the +12-volt supply. The diodes cater for the splitting-up of the two halves of the cycle.

The abovementioned mains filter is used to filter mains interference. As a result of using said filter, the zero crossing

detector cannot react to severe interference peaks in the mains voltage since said peaks are filtered out.

The operation of the zero crossing detector shown in Figure 2 is evident from the voltage forms shown in Figures 3a- c. Figure 3 shows diagrammatically the zero crossings of the input voltage on the terminals 1/L1 and 2/N. These figures also indicate the base-emitter voltages of the transistors Ql and Q2 as a horizontal broken line. As a consequence of the zero cross¬ ings of the input signal shown diagrammatically in Figure 3a, the signal shown in Figure 3b is produced at the point A of the circuit. Figure 3b also shows a switching level of the gate U1A as a horizontal broken line. At the output of the gate U1A, the pulses shown in Figure 3b are therefore produced.

The abovementioned NAND gates are preferably of the COSMOS type.

Figure 5 shows a graph which applies to two Osram 40- watt RS tubes which are supplied from the mains by means of a supply voltage circuit according to the invention. Plotted along the horizontal axis is the light intensity of the tubes and along the vertical axis the voltage across the tubes E _β , the current through the tubes Ig, the power consumed by the tubes (apparent power. Vs; actual power Vw) and the cosine .

Figure 6 shows a three-phase motor which is energized by means of three controllable supply voltage circuits according to the invention. The adjustable resistors, constructed as potenti¬ ometers, of the three supply voltage circuits can be mechanically coupled.