BACKGROUND OF THE INVENTION

Cross-Reference to Related Applications:

[0001] This invention claims the benefit of U.S. provisional application number 61/108,784, filed on October 27, 2008. State of the Prior Art:

[0002] Switch-mode power supplies are used to convert electrical power of a given voltage to a different desired voltage. Given the pervasive use of power supplies for a broad range of electronic devices, it is advantageous to minimize their cost and complexity, particularly, but not exclusively, for price competitive consumer electronic products. [0003] In general, voltage outputs of switch-mode power supplies are controlled by periodically turning switches that are connected to the source of power on and off periodically, and, for a given input voltage, the duty cycle (relating the on time to the period) is directly related to the output voltage. Therefore, switch mode power supplies use one or more active devices as switches along with some kind of on-off control to turn the switch or switches on and off with a desired duty cycle to produce a desired output voltage. Such duty cycle controllers or control circuits, which generate the on-off signals to control the switch or switches are called pulse width modulation (PWM) controls or controllers. Ideally, these switches are digital in the sense that they switch almost instantaneously between full on and full off and vice versa. There are a host of canonical circuit topologies known to persons skilled in the art and available publicly to achieve various power supply characteristics. Good PWM control circuits can be quite complex due to the number of functions and details they entail, including, for example, triangle or other waveform generation, comparison, loop stability, cycle-by-cycle current limiting, slope compensation, lock-out, and other considerations. However, integrated circuit PWM controllers are readily available commercially that take care of these functions and complexities.

[0004] A less complicated PWM control technique called hysteretic control uses the output ripple (small periodic oscillations in the output voltage) to create the PWM drive to switch to control the duty cycle, thus output voltage. This hysteretic technique simplifies the PWM function by eliminating the triangle or other waveform generator and some other complexities, but it introduces other problems. For example, the output voltage necessarily has voltage ripple, which is a requirement of the feedback technique, and the switching frequency is greatly dependent on the load.

[0005] The foregoing examples of related art and limitations are intended to be illustrative, but not exclusive or exhaustive of the subject matter. Other aspects and limitations of the related art will become apparent to those skilled in the art upon a reading of the specification and a study of the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate some, but not the only or exclusive, example embodiments and/or features. It is intended that the embodiments and figures disclosed herein are to be considered illustrative rather than limiting. [0007] In the drawings:

[0008] Figure 1 is a block diagram of an example switch-mode buck converter with switch- node feedback;

[0009] Figure 2 is a schematic circuit diagram of an example switch-mode buck converter with switch-mode feedback; [0010] Figure 3 is a block diagram similar to Figure 1, but with an added capacitance to mitigate undamped ringing;

[0011] Figure 4 is a schematic circuit diagram similar to Figure 2, but with the added capacitance to mitigate undamped ringing and not including a capacitance component used in the Figure 2 example for creating a triangular waveform to the comparator;

[0012] Figure 5 is a schematic diagram similar to Figure 4, but with a Schmidt trigger circuit instead of the comparator circuit in Figure 4; and

[0013] Figure 6 is a schematic diagram similar to Figure 2, but with an added current sense circuit and compensating input voltage to the comparator.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

[0014] The most common switch mode power supplies, converters, or regulators that use pulse width modulation (PWM) to control duty cycle of one or more active switches to control voltage output are switched inductor converters, including buck converters, boost converters, and buck-boost converters (also commonly called inverters). Buck converters reduce the input voltage in direct proportion to the duty cycle (the ratio of a switch conductive or "on" time to total switching period), whereas the output voltage of a boost converter is always greater than the input voltage. A buck-boost output voltage is inverted, but it can be greater than, equal to, or less than the magnitude of its input voltage. In all conventional buck, boost, and buck -boost converters, the input, the output, and the ground all come together at one point or node, but one of three (input, output, or ground) passes through an inductor on the way to the node where they all come together, and the other two pass through switches, at least one of which must be an active switch and the other switch can be a diode. The active switch is controlled (e.g., turned on and off) by pulse width modulation (PWM), which sets the duty cycle, and a feedback control loop is used to regulate the output voltage by modulating the pulse width to vary the duty cycle to compensate for variations in input voltage. In the examples described herein, the feedback is obtained from the node that connects the active switch to the inductor, is called the switch node. [0015] A block diagram of an example buck converter circuit 10 utilizing switch-node feedback for pulse width modulation (PWM) to control duty cycle, thus output voltage, is shown in Figure 1. This buck converter circuit 10, as well as the other circuits shown and described herein, are example, but not the only possible, implementations that demonstrate features and principles of switch-node feedback for switch-mode power supplies, converters, and regulators. Therefore, this description will proceed with reference to the example circuits and implementations shown in the Figures 1 - 6, but with the understanding that the inventions recited in the claims below can also be implemented in myriad other switch-mode power supply, converter, and regulator circuits and topologies, once the principles are understood from the examples, descriptions, and explanations herein, and that some, but not all, of such other implementations, variations, and enhancements are also described or mentioned below. Also, it is easiest and most natural to discuss the operation of the example circuits and implementations with the assumption that the load current is high enough so that the example converters are operating in continuous conduction mode, i.e., that the inductor current does not go to zero between switching cycles. However, the principles and applications of switch-node feedback discussed and explained herein are also applicable to discontinuous conduction mode operation, i.e., where the inductor current does go to zero during part of the switching cycle, and discontinuous conduction mode does not pose a limitation to this method or technique.

[0016] Referring now primarily to the example buck converter 10 in Figure 1, the buck converter circuit elements include the input Vj _n , the output V _out , the ground G, the energy transfer inductor Ll , the active switch Sl, and the diode Dl. An output capacitor Cl is usually included in a buck converter (shown in the example buck converter 10 in Figure 1 across the output in parallel to the load Ri _oad ) to smooth out the current changes from the inductor Ll into a stable voltage at V _out and to minimize voltage overshoot, in which output voltage overshoots the regulated value when a full load is suddenly removed from the output. Cl also minimizes voltage ripple and ringing at the output. Input capacitors (not shown) and other components can also be included for various design needs and parameters, as is known to persons skilled in the art, thus need not be described here.

[0017] Essentially, the buck converter operates by closing the active switch Sl to connect the input voltage Vj _n to the inductor Ll to store energy in the inductor Ll as current flows to the load Rioad, and then, when the active switch Sl is opened, the energy stored in the inductor Ll discharges into the load Ri _oad , where it performs work or creates heat. While the active switch Sl is closed, there is a voltage (V _1n - V _out ) across Ll, the current rises linearly, a magnetic field builds in Ll (storing energy), and the diode Dl is reverse biased (turned off), thus prevents current flow from the input, through Dl to ground G so that the current flows through the load Ri _oad - However, when the active switch Sl is opened, the applied voltage V _1n is removed, the magnetic field of Ll collapses, reversing the voltage and releasing the energy to continue the current flow, which falls linearly as the energy depletes, and the now forward biased (thus turned on) diode Dl provides a current path (closed circuit) for the Ll induced current to flow through the load Ri _oad - Of course, the more time the active switch is turned on during each cycle, the more energy will be stored in the inductor Ll during each cycle, and the higher the output voltage V _out will be. Therefore, as mentioned above, the higher the duty cycle (ratio of time the switch is one to the total time of a cycle period), the higher the output voltage V _out will be. Likewise, the lower the duty cycle, the lower the output voltage V _out will be. Also, if the input voltage V _1n varies for a given duty cycle, the energy transferred into the inductor Ll will vary accordingly, so the energy discharged by the inductor Ll to the load Ri _oad will also vary, causing a comparable variations in the output voltage V _out . Therefore, in order to maintain a constant output voltage V _out for a given load Ri _oad when the input voltage V _1n decreases, the duty cycle (ratio of time the active switch Sl is on in a cycle period) can be increased to maintain the same level of energy transferred into the inductor Ll in each cycle in spite of the lower input voltage Vj _n . Likewise, in order to maintain a constant output voltage V _out for a given load Ri _oad when the input voltage V _1n increases, the duty cycle can be decreased. Also, a variation in the load Ri _oad will change the voltage drop across the load Ri _oad and affect the current flow, thus energy transfer into and out of the inductor Ll, causing variation in the output voltage V _out . Consequently, the duty cycle may have to be varied to maintain a constant output voltage V _out as variations in the load Ri _oad occur.

[0018] In the example buck converter 10 shown in Figure 1, the active switch Sl is turned on and off by a pulse width modulated switch control signal 14 from an inverting comparator COMP, which provides the duty cycle or timing with which the active switch S 1 is turned on and off. In order to maintain a constant desired output voltage V _out in spite of variations in input voltage V _1n and other variations, a feedback indicative of the output voltage V _out is applied to the comparator COMP to cause it to adjust the pulse width modulation (PWM) of the switch control signal 14 to create a duty cycle adjustment as needed to correct for any changes in the output voltage V _out from the desired output voltage V _out . In this example, the output voltage feedback is obtained indirectly, from the switch node 12, instead of directly from the output voltage node 18, which has several advantages. For example, the on and off state continues at a fairly fixed frequency that depends little on the output load Ri _oad or on the load current, and the circuit can still be relatively simple.

[0019] As mentioned above, the node 12, which connects the active switch Sl to the energy transfer inductor Ll is called the switch node. The pulse width modulation (PWM) control of the active switch Sl to control the duty cycle, thus the output voltage V _out , is provided in this example buck converter 10 by an inverting comparator COMP, as indicated diagrammatically by the output 14 to the active switch Sl. As also indicated by the connection 16 of the inverting input (-) of the comparator COMP to the switch node 12 via the resistor Rl, the feedback for the comparator COMP to regulate the output voltage V _out is obtained from the switch node 12. When the inverting comparator COMP compares the voltage on the inverting input (-) to a reference voltage V _re f connected to the non-inverting (+) input of the comparator COMP, and it outputs an on signal to the switch Sl when the inverting input (-) voltage is lower than V _ref and outputs an off signal when the inverting input (-) voltage is lower than V _ief , thereby completing a control loop. A capacitance, represented diagrammatically by the capacitor C2 in Figure 1 , between the inverting input (-) of the comparator COMP and a low impedance point, such as the ground G and/or the load Ri _oad , charges and discharges to form a time-varying voltage substantially similar to a sawtooth waveform, and it slows the rate at which the feedback voltage changes on the inverting input (-) of the comparator COMP in response to the voltage changes at the switch-node 12 as applied to the inverting input (-) through the feedback resistor Rl . This arrangement allows the switching frequency to be set by appropriate choice of components Rl and C2. Hysteresis in the comparator COMP ensures bistable operation such that the voltage across C2 is constantly increasing and decreasing between two levels. The values of the feedback resistance Rl, the capacitance C2, and the hysteresis, together, control the frequency of the bistable oscillations for a given input and output voltage. Assuming continuous conduction mode operation, the voltage at the switch node 12 toggles between V _1n and ground G at that switching frequency, regardless of variations in current through the load Ri _oad - Therefore, the comparator COMP outputs on and off drive signals to the switch Sl at a fixed frequency that depends little on the output load Ri _oad and is fairly immune to variations in load current. [0020] The duty cycle of the drive signal 14 from the comparator COMP will be that required to create an average voltage equal to the reference voltage V, _ef across Cl, i.e., between the switch node 12 and ground G. The average voltage across the capacitor C2 is the same as the average voltage at the switch node 12, because the average current in the capacitor C2 has to be zero, and ideally, assuming the comparator COMP does not require any current so that the only current that flows through the feedback resistor Rl charges and discharges the capacitor C2, the average voltage across the feedback resistor Rl is also zero. Further, ideally, the average voltage across the inductor Ll has to be zero, so the output voltage V _out is ideally equal to the average voltage at the switch node 14. Consequently, by these equivalencies, the output voltage V _out , like the voltage at the switch node 12, will also be equal to the reference voltage V _ie f.

[0021] In practice, of course, inductors and comparators are not ideal, so the output voltage V _0Ut will not be exactly equal to the voltage across the capacitor C2. For example, leakage current in the comparator COMP will cause a slight voltage drop across the feedback resistor Rl, thus biasing the equivalence. Also, resistance in the inductor Ll will create droop in the output voltage V _out , which does not affect the voltage at the switch node 12, thus will not be detected or cause duty cycle correction or compensation by the pulse width modulation of the COMP. Other non-ideal losses or leakages might also bias the equivalences described above. However, there are ways to mitigate and/or compensate for such affects due to non-idealities, which are known to persons skilled in the art to help achieve acceptable operation of this kind of power supply or converter for many applications and perfoπnance specifications. For example, but not for limitation, an inductor with a specified series resistance that will keep the resulting droop within tolerable specifications for a particular application can be selected and used for the energy transfer inductor Ll . Also, for example, but not for limitation, a compensatory signal can be provided to the comparator COMP based on measured output current so that the inherent droop in the output voltage V _out from resistance in the induction Ll can be cancelled by a corresponding rise in the average voltage at the switch node 12. These and other mitigations and compensations can be used, if necessary, to take advantage of the benefits of switch node feedback principles and/or example implementation described herein.

[0022] As mentioned above, the example buck converter 10 with switch-node feedback shown in Figure 1 and described above is a block diagram, which can be implemented in a variety of ways. The circuit diagram in Figure 2 shows one fairly simple example of a switch-mode buck converter 20 with a switch-node feedback PWM control implementation, where the transistor Ql forms the active switch (Sl in Figure 1), and the transistors Q2 and Q3 in a differential configuration form the comparator (COMP in Figure 1). The inverting input 22 of the comparator is at the base of Q2, and the non-inverting input 24 is at the base of Q3. Therefore, the base of Q2 (the inverting input 22) is connected to the switch-node 12 (i.e., the node where the collector of the active switch Ql connects to the energy transfer inductor Ll), and the base of Q3 (the non-inverting input 24) is connected to the cathode of a zener diode D2, which functions as a reference voltage V _{1 ef} . The value of this V _{1 ef} can be set at any desired level to produce a desired output voltage V _out level, which may be equal to V _ief as explained below. A circuit can also be configured to provide a V _out that is different than the V ₁ ef , for example with resistors, voltage dividers, or other multipliers, as shown in the Figure 5 example below.

[0023] Like the Figure 1 example 10, the capacitor C2 is provided across the inverting input 22, and the output voltage V ₀₁₁ , is ideally equal to the average voltage at the switch-node 12, which is equal to the average voltage across the capacitor C2, which, with the pulse width modulation (PWM) provided by the comparator, is maintained the same as the reference voltage V _{1 ef} , as explained above. Therefore, as also explained above for the example 10 of Figure 1, the feedback for modulating the pulse width of the on-off control signal for the switch Ql to provide a duty cycle that maintains the output voltage V _out at a desired level is obtained at the switch-node 12, and the comparator COMP works to maintain the average voltage of C2, which is equal to the average voltage at the switch-node 12, at the same level as the reference voltage V _ief .

[0024] Essentially, when the voltage across the capacitor C2 drops below the low threshold set by the voltage on the base of Q3, the COMP switches on, and current flows through Q3 to drive the base of the switch Ql to turn Ql on. When the switch Ql is turned on, the switch- node 12 voltage goes high, substantially equal to the input voltage V _1n , and current flows from the input, through the switch Ql and through the energy transfer inductor Ll to the load Ri _oad - The voltage across the capacitor C2 follows the switch-node 12 voltage and increases approximately linearly. Eventually, when the voltage across the capacitor C2 reaches the high threshold set by the voltage at the base of Q3, the COMP turns off, i.e., Q2 turns on and Q3 turns off, so current ceases following through Q3 to drive the base of the switch Ql, and flows through Q2 instead. With no current flowing through Q3 to drive the base of the switch Ql, the switch Ql turns off, and the switch-node 12 voltage drops to a diode drop below ground G as the current induced by the inductor flows through the diode Dl and through the load Ri _oad - With that voltage drop, there is a negative voltage across Rl, which gives rise to a current that makes the voltage on C2 decrease. When the voltage of C2 falls again to the threshold voltage set by the voltage on the base of Q3, then Q3 turns on as a result of V _icf on the base of Q3 then being higher than the voltage at the emitter of Q3, and Q2 turns off. The turned on Q3 again turns on the switch Ql , and the cycle repeats. [0025] The resistor R2 is provided to drain the charge stored in the base-emitter junction of the switch Ql when Q3 turns off, so that Ql turns off quickly. The resistor R3 sets the operating current of the COMP, which will go through either Q2 or Q3, depending on which one is turned on.

[0026] Hysteresis, which defines how far the voltage on C2 ramps up and down chasing the switching threshold, is created by positive feedback from a capacitive coupling between the Q2 output and the zener diode D2, which provides the reference voltage V _ref on the base 24 of Q3. In the example buck converter 20 circuit shown in Figure 2, the capacitive coupling is provided by the capacitor C3 connected between the collector of Q2 and the non-inverting input 24 on the reference node, i.e., the node connecting the V _ref of the zener diode D2 to the base of Q3. When Q2 is turned on and current flows through R4, a voltage is developed at R4. That voltage is capacitively coupled by C3 to the reference node 26 at the non-inverting input 24 on the base of Q3, where it works against the inherent dynamic resistance of the zener diode Dl to create a tiny square wave at the switching frequency riding on the reference voltage V _ief provided by the zener diode Dl as Q2, thus the voltage across R4 applied to the reference node 26, turns on and off. This positive feedback from Q2 to the reference node 26 and base of Q3 creates the hysteresis for the comparator voltage thresholds that result in bistable operation of the comparator COMP and switching Ql on and off at a fixed frequency with little, if any, dependence on the load Ri _oad or on the load current, because the cycling of voltage at C2, thus cycling of Q2, is caused by voltage changes at the switch-node 12 and not by current flowing to or through the load. Therefore, the voltage at C2 ramps up and down the amount and frequency of the tiny square wave riding the V _{1 ef} on the base of Q3, chasing the ever-toggling threshold of the comparator COMP. [0027] As mentioned above for the Figure 1 example 10, because the voltage across the capacitor C2 is constrained to lie between the high and low hysteretic thresholds of the comparator, closed loop control of the average voltage across the capacitor C2 is inherently stable. At the same time, the output voltage V _out is controlled indirectly, by feedback from the switch node 12, instead of directly from the output voltage V _out - [0028] Although the average output voltage V _ou t is theoretically equal to V _{1 ef} , as explained above, it can vary instantaneously from V _ief . Capacitor Cl and inductor Ll form an LC low- pass filter with damping factor being dependent on the load Ri _oad - In some cases, the dynamic impedance of the load may be very high, for example, when the load has a large inductive component or drives a circuit that draws a constant current, which can allow excessive and/or undesired ringing at the output. Such undesired effects can be mitigated by the addition of capacitance coupling from the output to the summing junction (the inverting input of the comparator) as shown, for example, by the capacitor C4 in Figure 3, which, except for the addition of the capacitor C4, is the same block diagram of the example buck converter 10 as shown in Figure 1. With this addition of capacitance coupling C4, ringing at the output will feed back into the PWM control, causing opposing adjustments to the switch drive. In this variation, the capacitance across the inverting input (-) of the comparator COMP, which charges and discharges to form the time- varying voltage, is provided by the combination of C2 and the newly added C4.

[0029] In some case, the capacitor C2 can be eliminated, as illustrated, for example, in Figure 4, which is the same buck converter circuit as the example 20 in Figure 2, except for the addition of C4 and elimination of C2. In this example in Figure 4. the capacitance across the inverting input (at the base of Q2) of the comparator COMP, which charges and discharges to form the time-varying voltage, is provided by C4.

[0030] The non-idealities of the example buck converters with switch-node feedback shown in Figures 2 - 4 can be mitigated or provided with compensations as explained above for the example 10 in Figure 1. [0031] The hysteretic comparator for use in switch-mode power supplies using switch-node feedback can also be provided in other ways, for example, with a Schmidt trigger, as illustrated in an alternate embodiment in Figure 5. The example buck converter 30 circuit shown in Figure 5 is similar to the example buck converter circuit shown in Figure 4, but with a Schmidt trigger formed by transistors Q2 and Q3 instead of the comparator COMP in the Figure 4 example. The feedback in this example buck converter 30 is still obtained from the switch-node 12, as described above, but the reference voltage for output voltage V _out regulation is the emitter-base voltage of Q3 plus the hysteresis voltage developed across R4. Also, as in the Figure 4 example, the capacitance across the inverting input of the Schmidt trigger comparator in Figure 5 is provided by the capacitor C4 between the inverting input and the load Ri _oad - In this embodiment, the comparator with hysteresis is formed by Q2, Q3, R2, R3, and R4. When Q3 is on, the voltage at the emitter of Q2 is low, and hence the current through R2 is low. The low current through R2 causes the voltage drop across R4 to be low, and therefore the threshold at the base of Q3 is also low. When the voltage at summing junction 32 drops below the low threshold, Q3 turns of, which in turn causes the voltage on the base of Q2 to be large. As a consequence, the voltage at the emitter of Q2 also becomes large, which results in a high current passing through R2. The high current of R2 flows through R4 developing the "high" voltage across R4, which, in turn, sets the threshold of Q3 to its "high" value. Drive is provided to the switching transistor Ql whenever the current through R2 is in the "high" state. In this way, the switch-node 12 causes the voltage at summing junction 32 to "chase" the ever-changing threshold at the base of Q3. The Resistor divider formed by Rl and R6 then set the average voltage of the switch-node 12 to be a multiple of the average voltage on the base of Q3, thereby regulating the output V _out . The voltage at the summing junction 32 formed by Rl, R6, R7, and C4 approximates a triangle wave, similar to that described in the example 10 in Figure 1. The Schmidt trigger (Q2 and Q3) turns on and off at two different threshold levels, the difference of which is defined by the hysteretic voltage developed across R4.

[0032] As the voltage at the summing junction 32, which is derived as a predetermined fraction of the voltage of the switch-node, decreases below the lower threshold, the Schmidt trigger turns on, and the current flow through Q2 drives the switch transistor Ql to turn on. Turning on switch Ql drives the output of Ql, thus the switch-node 12, to V _1n , and causes the voltage at the summing junction 32 to increase, which is caused by capacitor C4 charging through resistor Rl . The resistors R6 and R7 facilitate setting the output voltage V _out at a desired level, which may be different than the reference voltage or hysteresis thresholds. [0033] As the voltage at the summing junction 32 increases beyond the upper threshold, the Schmidt trigger turns off, stopping the flow of current through Q2, and thereby removing the drive from the switch transistor Ql. As a result, switch Ql turns off (speeded by drain of energy through R5), and the voltage at the switch-node 12 goes to a diode drop below ground G. This voltage drop at the switch-node 12, in turn, causes the voltage at the summing junction (the charge in capacitor C4) to decrease. The cycle repeats itself, as explained for previous examples, with the frequency defined by the hysteresis voltage, the Thevenin charging resistance, the value of the capacitor C4, and the supply voltage V _1n . Also, as in the previous examples, the frequency has little, if any, dependence on the load Ri _oad or the load current.

[0034] A metal oxide semiconductor field effect transistor (MOSFET) or other kinds of transistors (not shown) can be used for the switch Ql, if desired, instead of the bipolar junction transistors (BJT) shown in the examples, including either the differential pair or other comparator versions or the Schmidt trigger versions described above. In general, modifications of the example circuits to accommodate various silicon switches would be obvious to persons skilled in the art, once they understand the principles of this invention, and such obvious variants are considered to be equivalents within the scope and intent of the invention as defined by the claims below.

[0035] A buffer (not shown) can also be placed between the drive signal and the gate of a MOSFET switching device in order to allow the input capacitance of the MOSFET to be charged more quickly than the collector resistor of the previously described examples allow. The increased switching speed reduces switching losses and improves overall converter efficiency.

[0036] As mentioned above, non-idealities, mostly resulting from losses in the inductor Ll, can result in degradation in the output voltage V _out regulation against output load, and some, but not necessarily all, relatively simple techniques for reducing these effects and improving output regulation have been discussed above. A non-ideal inductor possesses a non-zero series resistance that introduces a voltage drop across the inductor, and such voltage drop biases the equivalence between output voltage and average voltage at the switch-node upon which this method and apparatus relies for output regulation. As a result, the output voltage will droop according to the product of the inductor series resistance and the load current. [0037] One approach to counteract such droop in voltage output due to inductor series resistance includes the output current sense circuit for injecting a compensating signal to the comparator or Schmidt trigger summing junction, as shown, for example, in Figure 6. The example buck converter with switch-node feedback shown in Figure 6 is substantially the same as shown in Figure 4, but it has a current sense circuit added, which comprises, for example, resistors R6 through Rl 1 and transistors Q4 through Q6. In this example, a voltage is derived across the resistor Rl 1 , which is proportional to the output current. This voltage derived across Rl 1 is the output of the current sense circuit. A feedback resistor Rl 2 couples the output of the current sense circuit to the comparator summing junction 34. [0038] When there is little or no output current, the voltage drop across the resistor Rl 1 is small, and the current through resistor Rl 2 is defined by the difference between the output voltage V _1n and the voltage at the summing junction 34. As the current increases, the voltage drop across resistor Rl 1 increases, lowering the current through Rl 2. he lower current through R12 causes a higher duty cycle at the switch-node 12, thereby increasing the average voltage at the switch-node 12, which, in turn, counteracts the inherent voltage drop in the inductor Ll.

[0039] The example circuit in Figure 6 can also be adjusted to compensate for the non-ideal zener diode D2, which provides the reference voltage in the circuit. In practice, the zener diode D2 does not perform ideally, because the shunt current through the zener diode D2 changes with input supply voltage V ₁₁₁ . This variation in current results in a variation in the reference voltage V, _ef at the bse of Q3. As a result, the output voltage V _out increases with increasing input voltage V _1n . The resistors Rl 1 and Rl 2 can be adjusted so as to cancel this input voltage V _1n dependence. At the same time, a solution exists so as to allow resistors RI l and Rl 2 to simultaneously compensate for load current droop as explained above. Consequently, the example circuit in Figure 6 can achieve good output regulation across varying input voltage and load current. The current sensing ciruit of Figure 6 comprises Q4, Q5, Q6, R6, R7, R8, R9, RlO. The transistors Q4 and Q5 form a differential amplifier measuring the voltage across R6. The output of the differential amplifier drives R9 and RlO. The voltage drops across R9 and RlO will be equal as long as the voltages on the emitters of Q4 and Q5 are equal. When load current flows through R6, the balance is disturbed and Q6 turns on. Current through the emitter of Q6 creates a drop across R8 that tends to restore balance on the emitters of Q4 and Q5. The current required to restore balance is directly proportional to the load current. In this way, the current that flows in the collector of Q6 is proportional to the load current. [0040] While a number of example aspects and implementations have been discussed above, those of skill in the art will recognize certain modifications, permutations, additions, and subcombinations thereof. It is therefore intended that the following appended claims and claims thereafter introduced are interpreted to include all such modifications, permutations, additions, and subcombinations as are within their true spirit and scope. [0041] The words "comprise," "comprises," "comprising," "composed," "composes," "composing," "include," "including," and "includes" when used in this specification, including the claims, are intended to specify the presence of stated features, integers, components, or steps, but they do not preclude the presence or addition of one or more other features, integers, components, steps, or groups thereof. Also the words, "maximize" and "minimize" as used herein include increasing toward or approaching a maximum and reducing toward or approaching a minimum, respectively, even if not all the way to an absolute possible maximum or to an absolute possible minimum.