Title:
SYNCHRONOUS FIFO
Document Type and Number:
WIPO Patent Application WO/2023/103337
Kind Code:
A1
Abstract:
Disclosed is a synchronous FIFO comprising a data storage circuit, a first logic circuit, a second logic circuit and an indicator circuit. The data storage circuit comprises N first registers, N first multiplexers and N first deciders, N being a positive integer; the first registers are alternately connected to the first multiplexers. The synchronous FIFO builds the storage required by the FIFO on the basis of registers, and primarily comprises registers, multiplexers and decision devices and omits RAM, so that there is no need for occupying RAM or for RAM read-write enabling or address control, avoiding the waste of RAM resources. In designs with lower storage depth requirements, few resources are occupied, chip area is greatly reduced, costs are reduced, and wiring layout is more convenient.
Inventors:
WANG HONGLIANG (CN)
ZHANG DESHAN (CN)
MOU QI (CN)
ZHANG DESHAN (CN)
MOU QI (CN)
Application Number:
PCT/CN2022/100478
Publication Date:
June 15, 2023
Filing Date:
June 22, 2022
Export Citation:
Assignee:
INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO LTD (CN)
International Classes:
G06F5/06; G06F13/16
Foreign References:
| CN113900975A | 2022-01-07 | |||
| CN102053815A | 2011-05-11 | |||
| CN106776357A | 2017-05-31 | |||
| CN205176827U | 2016-04-20 | |||
| US20050091465A1 | 2005-04-28 |
Attorney, Agent or Firm:
BEIJING WANHUIDA LAW FIRM (CN)
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