BACKGROUND

[0001] Embodiments of the present disclosure relate to system, system-on-chip (SoC), and method for wireless communication.

[0002] Wireless communication systems are widely deployed to provide various telecommunication services such as telephony, video, data, messaging, and broadcasts. In wireless communication, there may be communications between a user device and a base station. During the data transmission, errors may occur. Accordingly, error detection and correction may be critical to ensure good quality in wireless communication systems. For that purpose, various approaches are introduced.

SUMMARY

[0003] Some embodiments of the present disclosure provide a system that implements hybrid-automatic repeat request (HARQ). The system may include an external memory and a system-on-chip (SoC) that may include an internal memory and at least one processor. In certain aspects, each of the external memory and the internal memory may be divided into a plurality of memory blocks. The at least one processor may be configured to store soft bits, corresponding to one or more erroneous code blocks (CBs), in the plurality of memory blocks and retrieve the soft bits according to a TB queue header for soft combination of the one or more erroneous CBs. The one or more erroneous CBs may be identified based on decoding results, through a decoding circuit of the SoC, on one or more CBs of a transport block (TB). In certain other aspects, first soft bits of the soft bits, corresponding to a first erroneous CB of the TB, may be stored in first linked memory blocks of the plurality of memory blocks based on the TB queue header, and second soft bits of the soft bits, corresponding to a second erroneous CB of the TB, may be stored in second linked memory blocks of the plurality of memory blocks based on the TB queue header. The TB queue header may be configured to associate the first linked memory blocks with the second linked memory blocks. In certain aspects, the internal memory may include at least one subset of the first linked memory blocks or the second linked memory blocks.

[0004] Some embodiments of the present disclosure provide an SoC that implements HARQ. The SoC may include an internal memory divided into a plurality of memory blocks and at least one processor. The at least one processor may be configured to store soft bits, corresponding to one or more erroneous CBs, in the plurality of memory blocks. The one or more erroneous CBs may be identified based on decoding results, through a decoding circuit of the SoC, on one or more CBs of a TB. In certain aspects, the soft bits may include first soft bits and second soft bits. The first soft bits may be stored in one or more first memory blocks, and the second soft bits may be stored in one or more second memory blocks. In certain other aspects, the plurality of memory blocks may include the one or more first memory blocks associated with a TB queue header and the one or more second memory blocks associated with the TB queue header. The TB queue header may be configured to associate the one or more first memory blocks with the one or more second memory blocks. The at least one processor may be further configured to retrieve the soft bits according to the TB queue header for soft combination of the one or more erroneous CBs.

[0005] Some embodiments of the present disclosure provide a method of implementing (HARQ). The method may include storing soft bits, corresponding to one or more erroneous CBs, in memory. The one or more erroneous CBs may be identified based on decoding results, through a decoding circuit of an SoC, on one or more CBs of a TB. In certain aspects, the memory may include an internal memory of the SoC and a memory external to the SoC that are divided into a plurality of memory blocks. The storing of the soft bits may include storing first soft bits of the soft bits, corresponding to a first erroneous CB of the TB, in first linked memory blocks of the plurality of memory blocks based on a TB queue header; and storing second soft bits of the soft bits, corresponding to a second erroneous CB of the TB, in second linked memory blocks of the plurality of memory blocks based on the TB queue header. The TB queue header may be configured to associate the first linked memory blocks with the second linked memory blocks. The internal memory may include at least one subset of the first linked memory blocks or the second linked memory blocks. The method may further include retrieving the soft bits of the one or more erroneous CBs according to the TB queue header for soft combination of the one or more erroneous CBs.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure. [0007] FIG. 1 illustrates an exemplary wireless network, according to some embodiments of the present disclosure.

[0008] FIG. 2 illustrates a block diagram of an exemplary node, according to some embodiments of the present disclosure.

[0009] FIG. 3 illustrates a block diagram of an exemplary system including a baseband chip, a radio frequency (RF) chip, and a host chip, according to some embodiments of the present disclosure.

[0010] FIG. 4 illustrates a block diagram of an exemplary baseband chip, according to some embodiments of the present disclosure.

[0011] FIG. 5 illustrates an exemplary continuous decoding strategy in response to a first erroneous CB, according to some embodiments of the present disclosure.

[0012] FIG. 6 illustrates a diagram of an exemplary linked-list memory data structure, according to some embodiments of the present disclosure.

[0013] FIG. 7 illustrates a diagram of transport block (TB) queue header management schemes, according to some embodiments of the present disclosure.

[0014] FIG. 8 illustrates a flow chart of an exemplary method of implementing HARQ, according to some embodiments of the present disclosure.

[0015] FIG. 9 illustrates another flow chart of an exemplary method of implementing HARQ, according to some embodiments of the present disclosure.

[0016] Embodiments of the present disclosure will be described with reference to the accompanying drawings.

DETAILED DESCRIPTION

[0017] Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

[0018] It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “some embodiments,” “certain embodiments,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures, or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

[0019] Various aspects of wireless communication systems will now be described with reference to various apparatus, systems, and methods. These apparatus, systems, and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, units, components, circuits, steps, operations, processes, algorithms, etc. (collectively referred to as “elements”). These elements may be implemented using electronic hardware, firmware, computer software, or any combination thereof. Whether such elements are implemented as hardware, firmware, or software depends upon the particular application and design constraints imposed on the overall system.

[0020] The techniques described herein may be used for various wireless communication networks, such as code division multiple access (CDMA) system, time division multiple access (TDMA) system, frequency division multiple access (FDMA) system, orthogonal frequency division multiple access (OFDMA) system, single-carrier frequency division multiple access (SC- FDMA) system, and other networks. The terms “network” and “system” are often used interchangeably. A CDMA network may implement a radio access technology (RAT), such as Universal Terrestrial Radio Access (UTRA), evolved UTRA (E-UTRA), CDMA 2000, etc. A TDMA network may implement a RAT, such as Global System for Mobile communication (GSM). An OFDMA network may implement a RAT, such as Long Term Evolution (LTE) or New Radio (NR). The techniques described herein may be used for the wireless networks and RATs mentioned above, as well as other wireless networks and RATs. [0021] A transport block (TB) in a wireless communication system (e.g., 5G NR) may include a payload that is transmitted in a shared data channel between the base station and the user equipment (UE). At the PHY layer of the base station, an error-detecting (ED) code, such as cyclic redundancy check (CRC), may be appended to the TB to enable error detection at the UE. The CRC is an error-detecting code in which redundant bits are added to the data for transmission to facilitate UE-side detection of errors in the coded TB. In certain implementations, the CRC can be used by the hybrid-automatic repeat request (HARQ) processes at the UE as a trigger for requesting retransmissions.

[0022] Reliability of data transmission is a fundamental issue in wireless communications. Transmission problems, such as fading in wireless channels, can result in a loss of signal power and cause poor performance in a communication system. In view of this, HARQ schemes are introduced to improve the transmission reliability. Some automatic repeat request (ARQ) schemes are combined with high-rate forward error correction (FEC) schemes in the HARQ schemes, which are widely applied to wireless data communication systems.

[0023] As described above, the CRC may be appended to the TB to be transmitted. Following the attachment of the CRC, the TB at the base station may be segmented into multiple code blocks (CBs) to improve encoding and decoding performance. Each CB may be encoded with an FEC code, such as Turbo code or a low-density parity-check (LDPC) code, and rate matched separately. The resulting bits may be concatenated to form the sequence of bits representing the coded TB to be sent to the UE. At the UE, each coded CB may be decoded and verified based on the error detection code, separately.

[0024] During the data transmission, various errors may occur. For example, data packets may be negatively influenced by time-variant channels, multipath fading, and/or other factors. These issues cannot be predicted and compensated in advance, thus resulting in erroneously received packets. As it is not possible to decode the erroneously received packets, the ARQ schemes of other approaches discard the packets which fail the code check and accordingly request retransmission. Despite so, the erroneous packets may still contain valuable information to benefit the decoding. In view of this, the HARQ schemes come with soft combining. In the HARQ soft combining, in response to the decoding failure at a packet, soft bits of the erroneous packet may be stored and combined with the retransmission to obtain a single, combined packet that is more reliable than its previous transmission.

[0025] In a wireless data communication system employing certain forward error correction (FEC) schemes, a decoding performance can be improved by applying soft bits with a soft-decision decoder. The soft-decision decoder is configured for a decoding method in which inputs to the soft-decision decoder may take on a whole range of values between 0 and 1, rather than a binary' code in a hard-decision decoder. The extra information of the range indicates the reliability of each input data point and is used to give better estimates of the original data. In some sense, the soft bits represent reliability information based on likelihood decoding rules. One commonly used metric for the soft bits is the log-likelihood ratio (LLR). In the present disclosure, soft bits and LLR bits may be used interchangeably to represent the same subject. While the LLR bits describe the reliability information more from a functional perspective, the soft bits emphasize a physical perspective of the reliability information.

[0026] In the retransmission, the set of coded bits transmitted may be selected differently. In one scheme as additional repetition coding, the retransmission may consist of the same set of coded bits as the original transmission. The additional repetition coding does not give any additional coding gain. In another instance, an incremental redundancy (IR) may be applied to send a different version of the packets with different error detection and correction bits so as to increase the signal~to~noise ratio (SNR) and the coding gain.

[0027] In some approaches, at the first occurrence of an erroneous CB, the decoding may be terminated immediately, waiting for the retransmission with respect to the next decoding. For the HARQ combining, in these approaches, the soft bits of the entire TB are stored in an external memory (i.e., a system memory or a main memory). The soft bits of the entire TB herein refer to the soft bits of the erroneous CB in addition to those of other CBs that pass the code check. In these approaches, until a retransmitted TB is received, the decoding will not be restarted.

[0028] This system of the other approaches, however, comes with several shortcomings. For example, if only one or a few of the CBs are in error, storing the soft bits of the entire TB may result in low efficiency as compared to storing only the erroneous CBs. Besides, knowingly, large jitters, multiple bus accesses, and intensive read/write operations are associated with the external memory, the problems of which result in long latency, performance loss, and more power consumption. With the higher and higher throughput in wireless communication systems today, the data bus traffic required to transfer the soft bits to the external memory increases dramatically. As a result, the power as required by these operations with respect to the external memory may not be supported by the modem chip of a mobile device powered by a battery.

[0029] In order to solve the problems in the approaches as described above, some embodiments of the present disclosure provide a system, a chip, and a method, in which at any erroneous CBs, only the soft bits of the erroneous CBs are stored instead of storing the soft bits of the entire TB. Accordingly, fewer resources, less power consumption, and more efficiency can be expected.

[0030] In accordance with some embodiments of the present disclosure, an internal memory may be implemented in the same baseband chip, or any suitable SoC, that performs the HARQ combination as a local memory or an on-chip memory. In certain embodiments, the internal memory may be in a modem (baseband) chip. The soft bits of only the erroneous CBs may be stored to the internal memory, rather than (or, in addition to) the external memory. In such a manner, an efficient way can be provided to use the internal memory under a typical target Block Error Rate (BLER). Further, the present design can effectively reduce the traffic congestion due to excesses to the external memory, thereby saving power and reducing the latency under typical working conditions for high throughput wireless traffic without much increase in the hardware cost.

[0031] In some embodiments of the present disclosure, the internal memory may be divided into a plurality of memory blocks. Further, memory management schemes may be implemented in the embodiments, in which a portion of the plurality of memory blocks, for storing the soft bits of the erroneous CBs of one TB, may form a linked-list data structure. In this way, the memory usage efficiency of the internal memory can be increased. Meanwhile, in order to reduce memory holes due to different memory size requirements for each CB, in certain embodiments, sizes of the divided memory blocks may be the same.

[0032] At a storing stage of the soft bits (i.e., an offloading stage), some embodiments of the present disclosure may maintain a queue for recoding information about the erroneous CB(s) of one TB to be decoded in a current transmission time interval (TTI). The information associated with the erroneous CB(s) in one TB may be saved as TB offload queue header in response to an end of the TB decoding in the TTI. At the retransmission, for the HARQ combining, the previous soft bits associated with the TB are required. For that purpose, the previously saved TB offload queue header may be retrieved and used as TB onload queue header at a stage of fetching the soft bits (i.e., an onloading stage). In such a way, a HARQ process can easily follow a linked-list data structure of TB onload queue header (in some sense, TB offload queue header) in sequence to obtain the previously-stored soft bits and accordingly perform the HARQ combining. In the present disclosure, the HARQ combining and the soft combination may be used interchangeably. [0033] Reference will now be made in detail to exemplary embodiments of the present disclosure in the following, which may be illustrated in the accompanying drawings. It is apparent that the described embodiments are some but not all of the embodiments of the present disclosure, and the drawings are used for illustration but not for limitation.

[0034] FIG. 1 illustrates an exemplary wireless network 100, in which certain aspects of the present disclosure may be implemented. As shown in FIG. 1, wireless network 100 may include a network of nodes, such as user equipment (UE) 102, access node 104, and core network element 106. UE 102 may be any terminal device, such as a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, or any other device capable of receiving, processing, and transmitting information, such as any member of a vehicle to everything (V2X) network, a cluster network, a smart grid node, or an Internet-of-Things (loT) node. It can be understood that UE 102 is illustrated as a mobile phone simply by way of illustration and not by way of limitation. [0035] Access node 104 may be a device that communicates with UE 102, such as a wireless access point, a base station, a Node B, an enhanced Node B (eNodeB or eNB), a next- generation NodeB (gNodeB or gNB), a cluster master node, or the like. Access node 104 may have a wired connection to UE 102, a wireless connection to UE 102, or any combination thereof. Access node 104 may be connected to UE 102 by multiple connections, and UE 102 may be connected to other access nodes in addition to access node 104. Access node 104 may also be connected to another user equipment. It can be understood that access node 104 is illustrated by a radio tower by way of illustration and not by way of limitation.

[0036] Core network element 106 may serve access node 104 and UE 102 to provide core network services. Examples of core network element 106 may include a home subscriber server (HSS), a mobility management entity (MME), a serving gateway (SGW), or a packet data network gateway (PGW). These are examples of core network elements of an evolved packet core (EPC) system, which is a core network for the LTE system. Other core network elements may be used in LTE and in other communication systems. In some embodiments, core network element 106 may include an access and mobility management function (AMF) device, a session management function (SMF) device, or a user plane function (UPF) device, of a core network for the NR system. It can be understood that core network element 106 is shown as a set of rack-mounted servers by way of illustration and not by way of limitation.

[0037] Core network element 106 may connect with a large network, such as the Internet 108, or another Internet Protocol (IP) network, to communicate packet data over any distance. In this way, data from UE 102 may be communicated to another user equipment connected to other access points, including, for example, computer 110 connected to Internet 108, for example, using a wired connection or a wireless connection, or to a tablet 112 wirelessly connected to Internet 108 via a router 114. Thus, computer 110 and tablet 112 provide additional examples of possible user equipments, and router 114 provides an example of another possible access node.

[0038] A generic example of a rack-mounted server is provided as an illustration of core network element 106. However, there may be multiple elements in the core network including database servers, such as database 116, and security and authentication servers, such as authentication server 118. Database 116 may, for example, manage data related to user subscription to network services. A home location register (HLR) is an example of a standardized database of subscriber information for a cellular network. Likewise, authentication server 118 may handle authentication of users, sessions, and so on. In the NR system, an authentication server function (AUSF) device may be the specific entity to perform user equipment authentication. In some embodiments, a single server rack may handle multiple such functions, such that the connections between core network element 106, authentication server 118, and database 116, may be local connections within a single rack.

[0039] Each element in FIG. 1 may be considered a node of wireless network 100. More detail regarding the possible implementation of a node is provided by way of example in the description of node 200 in FIG. 2. Node 200 may be configured as UE 102, access node 104, or core network element 106 in FIG. 1. Similarly, node 200 may also be configured as computer 110, router 114, tablet 112, database 116, or authentication server 118 in FIG. 1. As shown in FIG. 2, node 200 may include processor 202, memory 204, and transceiver 206. These components are shown as connected to one another by a bus, but other connection types are also permitted. When node 200 is UE 102, additional components may also be included, such as a user interface (UI), sensors, and the like. Similarly, node 200 may be implemented as a blade in a server system when node 200 is configured as core network element 106. Other implementations are also possible.

[0040] Transceiver 206 may include any suitable device for sending and/or receiving data. Node 200 may include one or more transceivers, although only one transceiver 206 is shown for simplicity of illustration. An antenna 208 is shown as a possible communication mechanism for node 200. Multiple antennas and/or arrays of antennas may be utilized. Additionally, examples of node 200 may communicate using wired techniques rather than (or in addition to) wireless techniques. For example, access node 104 may communicate wirelessly to UE 102 and may communicate by a wired connection (for example, by optical or coaxial cable) to core network element 106. Other communication hardware, such as a network interface card (NIC), may be included as well.

[0041] As shown in FIG. 2, node 200 may include processor 202. Although only one processor is shown, it can be understood that multiple processors can be included. Processor 202 may include microprocessors, microcontrollers (MCUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functions described throughout the present disclosure. Processor 202 may be a hardware device having one or more processing cores. Processor 202 may execute software. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Software can include computer instructions written in an interpreted language, a compiled language, or machine code. Other techniques for instructing hardware are also permitted under the broad category of software. [0042] As shown in FIG. 2, node 200 may also include memory 204. Although only one memory is shown, it can be understood that multiple memories can be included. Memory 204 can broadly include both memory and storage. For example, memory 204 may include random-access memory (RAM), read-only memory (ROM), static RAM (SRAM), dynamic RAM (DRAM), ferro- electric RAM (FRAM), electrically erasable programmable ROM (EEPROM), CD-ROM or other optical disk storage, hard disk drive (HDD), such as magnetic disk storage or other magnetic storage devices, Flash drive, solid-state drive (SSD), or any other medium that can be used to carry or store desired program code in the form of instructions that can be accessed and executed by processor 202. Broadly, memory 204 may be embodied by any computer-readable medium, such as a non-transitory computer-readable medium.

[0043] Processor 202, memory 204, and transceiver 206 may be implemented in various forms in node 200 for performing wireless communication functions. In some embodiments, processor 202, memory 204, and transceiver 206 of node 200 may be implemented (e.g., integrated) on one or more system-on-chips (SoCs). In one example, processor 202 and memory 204 may be integrated on an application processor (AP) SoC (sometimes known as a “host,” referred to herein as a “host chip”) that handles application processing in an operating system (OS) environment, including generating raw data to be transmitted. In another example, processor 202 and memory 204 may be integrated on a baseband processor (BP) SoC (sometimes known as a “modem,” referred to herein as a “baseband chip”) that converts the raw data, e.g., from the host chip, to signals that can be used to modulate the carrier frequency for transmission, and vice versa, which can run a real-time operating system (RTOS). In still another example, processor 202 and transceiver 206 (and memory 204 in some cases) may be integrated on an RF SoC (sometimes known as a “transceiver,” referred to herein as an “RF chip”) that transmits and receives RF signals with antenna 208. It is understood that in some examples, some or all of the host chip, baseband chip, and RF chip may be integrated as a single SoC. For example, a baseband chip and an RF chip may be integrated into a single SoC that manages all the radio functions for cellular communication.

[0044] Referring back to FIG. 1, in some embodiments, any suitable node of wireless network 100 (e.g., UE 102 or access node 104) may perform the HARQ operations and/or configure the UE 102 to perform the HARQ operations described below in connection with FIGs. 3-9.

[0045] FIG. 3 illustrates a block diagram of an exemplary system, according to some embodiments of the present disclosure. System 300 may include baseband chip 302, RF chip 304, and host chip 306, according to some embodiments of the present disclosure. System 300 may be an example of any suitable node of wireless network 100 in FIG. 1, such as UE 102 or access node 104. As shown in FIG. 3, system 300 may include baseband chip 302, RF chip 304, host chip 306, and one or more antennas 310. In accordance with some embodiments of the present disclosure, baseband chip 302 may be implemented by processor and internal memory. Internal memory may refer to an on-chip memory, such as registers, buffers, or caches at baseband chip 302. System 300 may further include an external memory 308 (e.g., a system memory or a main memory external to baseband chip 302, RF chip 304, and host chip 306) that can be shared by each chip 302, 304, or 306 through the system/main bus. Although baseband chip 302 is illustrated as a standalone SoC in FIG. 3, it can be understood that in one example, baseband chip 302 and RF chip 304 may be integrated as one SoC; in another example, baseband chip 302 and host chip 306 may be integrated as one SoC; in still another example, baseband chip 302, RF chip 304, and host chip 306 may be integrated as one SoC, as described above. [0046] FIG. 4 illustrates a block diagram of an exemplary baseband chip, according to some embodiments of the present disclosure. As described above, at the PHY layer of the base station, raw data as generated may be sent for error code attachment, encoding, modulation, and mapping. At the base station, the raw data may be accessed through a source, for example, using the direct memory access (DMA). In certain instances, the source may be implemented using electronic hardware, firmware, computer software, the like, or any combination thereof and may process MAC information (or Radio Link Control, RLC, information) and send information bits to an error code attaching circuit and an encoding circuit, respectively . The error code attaching circuit may append the error-detecting code, such as CRC, to the TB to enable the error detection at the UE. The encoding circuit may encode the data by, e.g., source coding and/or channel coding. The coded data may be modulated through the modulating circuit using any suitable modulation techniques, such as multi-phase pre-shared key (MPSK) modulation or quadrature amplitude modulation (QAM). Meanwhile, the base station may perform additional functions, such as symbol or layer mapping, to convert the data into a signal that can be used to modulate the carrier frequency for transmission. The modulated signal may be sent to an RF chip of the base station. The RF chip of the base station may convert the modulated signal in digital form into analog form, i.e., RF signals and perform any suitable front-end RF functions, such as filtering, up-conversion, or sample-rate conversion. A transmitter of the RF chip and an antenna, e.g., an antenna array, at the base station may transmit the RF signals to a data channel to arrive at the UE.

[0047] Referring back to FIG. 3, antenna 310 at the UE may receive the RF signals and pass the RF signals to a receiver (RX) of RF chip 304. RF chip 304 at the UE may perform any suitable front-end RF functions, such as filtering, down-conversion, or sample-rate conversion, and convert the RF signals into low-frequency digital signals (baseband signals) that can be processed by baseband chip 302, 400. In the downlink, as illustrated in FIG. 4, baseband chip 400 may demodulate the baseband signals through demodulating circuit 402 and decode the demodulated signals through decoding circuit 404 to extract raw data that can be processed by host chip 306. The raw data provided by baseband chip 400 may be sent to host chip 306 directly or stored in external memory 308.

[0048] Moreover, the baseband chip 400 according to some embodiments of the present disclosure may perform additional functions, such as de-mapping, channel estimation, descrambling, etc. In certain instances, baseband chip 400 may include one or more components to realize the HARQ operations, such as managing/storing the soft bits, soft combining, and error detection. As a result, compared to the other approaches, the present disclosure can decrease latency, reduce power consumption, and achieve good decoding performance/reliability.

[0049] In some embodiments, baseband chip 400 may further include error-detecting circuit 406 for code check/error detecting of the decoded CBs in each TB. Error-detecting circuit 406 may be configured to check the error detecting (ED) code, such as CRC, appended to the decoded CBs and determine whether the CBs are successfully decoded and pass the code check. If error-detecting circuit 406 determines that all the CBs of one TB pass the code check, the decoded CBs may be transmitted to TB concatenating circuit 408. TB concatenating circuit 408 may concatenate the segmented CBs to form one TB, which may be sent to host chip 306 directly or stored in external memory 308.

[0050] In some scenarios, however, due to the transmission errors, the decoding errors, and/or other errors, one or more CBs may fail the code check at error-detecting circuit 406. In these cases, the soft bits of the erroneous CBs are required to be saved so that the subsequent HARQ combining can be performed. As described above, in some embodiments of the present disclosure, the soft bits of the erroneous CBs may be stored in the internal memory by a linked-list data structure. As a result, compared to the other approaches by storing the entire TB to the external memory, the present disclosure provides better decoding performance/reliability and less power consumption.

[0051] In view of the above, the baseband chip 400 may further include internal memory 410. Internal memory 410 is an on-chip memory of the baseband chip 400, such as buffers or caches. In certain instances, the internal memory 410 may include fast low-latency static RAM (SRAM). The size of internal memory 410 may be determined by a peak throughput of the system and a target BLER under which the system is working stably. In an example, 4G or 5G Enhanced Mobile Broadband (EMBB) systems may support carrier aggregation of 5 component carriers (CCs) and maximum 16 HARQ processes on each CC with 10%TB BLER and 2 erroneous CB per TB. Under those conditions, a memory size of the internal memory for storing the soft bits can be estimated to be around 100KB.

[0052] FIG. 5 illustrates an exemplary continuous decoding strategy in response to the occurrence of a first erroneous CB, according to some embodiments of the present disclosure. In this strategy, instead of immediately terminating the decoding used by the other approaches, the decoding of the remaining CBs of the TB may be continued. In other words, even after the CB of one TB fails the code check, the decoding continues till the end of the TB in the current TTI. As a result, a long latency waiting for the retransmission can be avoided.

[0053] Support for this strategy is that, even with a high TB BLER, the chance for the occurrence of one erroneous CB within one TB is relatively smaller. This is because, as one TB may include up to 152 CBs, individual CB failure contributes to the TB error. For example, assuming that the error bits in one TB occur independently, the probability of one erroneous CB in one TB can be calculated by formula (1) as follows:

[0054]

[0055] In one example with 10% TB BLER and 50 CBs per TB, the probability of one erroneous CB, based on the above formula, can be as low as 0.2%. That is, even under a high TB error rate, the CB error rate is still much smaller compared to the TB error rate. In practical situations, the CB errors may occur in bursts and result in a higher CB error rate of up to 1%. Compared to 10% TB error rate, 1% CB error rate is still relatively lower. Based on the estimation, some embodiments of the present disclosure may implement the continuous decoding strategy in the present system to reduce the latency.

[0056] As illustrated in FIG. 5 as an example, transport block TB0 that includes code blocks CB0, CB1, CB2, and CB3 may be transmitted through transmitter TX to receiver RX of baseband chip 400 for the decoding and code check. It can be understood that the numbers of CBs in each TB may vary with different technology, CB code format, and CB size. The number of four CBs in FIG. 5 is merely shown for illustrative purposes. As described above, coded CB0, CB1, CB2, and CB3 may be decoded through decoding circuit 404 and code verified through error- detecting circuit 406, as shown in FIG. 4. In the continuous decoding strategy, even after the first erroneous CB (e.g., CB0 in FIG. 5), the decoding of remaining CBs (e.g., CB1, CB2, and CB3) may be continued till the decoding of the TB is completed. In some embodiments, as described above, the soft bits of only the erroneous BC(s) (e.g., CB0 in FIG. 5) may be stored in internal memory 410 for the HARQ combining later.

[0057] Referring back to FIG. 4, in some embodiments, baseband chip 400 may further include HARQ combining circuit 412. In the case of a decoding failure at one CB, the soft bits of the erroneous CB are required to be saved and later combined with the retransmission to obtain a single, combined packet to be decoded again. Some embodiments of the present disclosure may include internal memory 410 configured to store the soft bits of the erroneous CB. With reference to FIGs. 4 and 5, in response to an erroneous CB (e.g., CB0 in FIG. 5), feedback signal FB may be sent to notify the sender of the erroneous CB and request the sender to retransmit the TB. The HARQ systems may use acknowledgment (ACK) and/or negative acknowledgment (NACK) signal feedback to determine whether the retransmission of a data packet is required or not. The early stored soft bits of the erroneous CB (e.g., CB0 in FIG. 5) may be retrieved and combined with the soft bits of a retransmitted CB of for example, a different version through HARQ combining circuit 412. In certain embodiments, in response to the onloading being completed, the memory blocks (either in internal memory 410 or in external memory 308) that store the soft bits can be released.

[0058] The combined CB may be sent to decoding circuit 404 again for the decoding and to error-detecting circuit 406 again for the code check. If all the CBs pass the code check, these successful bits may be concatenated through TB concatenating circuit 408 to form one TB for transmission/storage. On the other hand, if the combined soft bits of the same CB still fail at error- detecting circuit 406, the combined soft bits may be stored again, and storage information regarding the memory' blocks corresponding to the combined soft bits may be attached to/ saved in TB offload queue header.

[0059] It can be understood that, although the baseband chip 400 is divided into various circuits according to their operations and/or functions for a better description, FIG. 4 is used only for illustration but not for limitation. The component(s) of baseband chip 400 as illustrated in FIG. 4 and described above are given as an example. In other instances, certain circuits in baseband chip 400 may be implemented to other portions of the system. Multiple circuits in baseband chip 400 may be integrated as one circuit, or one circuit therein may be divided into two. In some embodiments, multiple component carriers (CCs) may be applied, and each CC may use multiple HARQ processes. The multiple HARQ processes of the multiple CCs may run concurrently so that a transmission failure of a single packet does not terminate the overall transmission. For that purpose, certain circuits in FIG. 4 may be duplicated. Further, for ease of illustration, certain modules/circuits at the baseband chip, e.g., in regard to the encoding and modulating operations shown in FIG. 3, are omitted from FIG. 4.

[0060] The CB size may vary significantly from one CC to another CC and from one HARQ process to another HARQ process of the same CC. Further, the TB size and coding rate selected by the transmitter also vary. During the HARQ operations, some CBs may be decoded and verified successfully, and their previously occupied memory locations may be accordingly released. A next CB, however, may require a different memory size and cannot fit in the free memory locations. As a result, holes in the memory may be easily generated and become inevitable. What makes it worse is that, with more and more memory holes, the system may corrupt and cannot function normally.

[0061] In view of the issue of increasing memory holes, some embodiments of the present disclosure provide a linked-list data structure for effectively and efficiently managing the allocated memory for storing the soft bits. In certain instances, this management scheme may be applied to both internal memory 410 and external memory 308, while, in other instances, it may be only applied to internal memory 410.

[0062] FIG. 6 illustrates an exemplary linked-list memory data structure, according to some embodiments of the present disclosure. As illustrated in FIG. 6, both internal memory 410 and external memory 308 may be divided into a plurality of memory blocks 602, 604, respectively. In certain embodiments, the sizes of the plurality of memory blocks 602, 604 may be the same, e.g., 2KB. At an offloading stage, a queue for recording information about storing the erroneous CBs for each TB in the current transmission time interval (TTI) may be maintained. TB offload queue header 606 may be configured to save the information, such as the memory block locations storing the soft bits, the size of the stored soft bits, the size of the memory blocks, etc. Further, the information may be linked or associated, based on the memory blocks of one TB, through TB offload queue header 606, such that finding one stored memory block can help locate another, if any. The terms “linked” or “associated” used herein may refer to a relationship established between the memory blocks or a connecting relationship of the memory blocks, e.g., in a chain form and/or a tree form.

[0063] Considering that multiple component carriers (CCs) of various techniques may be implemented in some embodiments of the present disclosure, TB offload queue header 606 may further include information indicative of an index of the CC and the technology associated with the TB. In this way, in the subsequent HARQ combining, a correct TB offload queue header can be identified and located for retrieving the required soft bits.

[0064] TB offload queue header 606 may include one or more CB descriptor headers 6061, 6062, the number of which may be dependent on the number of the erroneous CB(s). Each of one or more CB descriptor headers 6061, 6062 may be configured for describing information about one of the erroneous CB, e.g., an index of the CB, a total storage size of the soft bits of the CB, an address of a first memory block, whether the memory block(s) is in the internal memory or in the external memory, a compression mode, a pointer to a next erroneous CB (if any), the like, or any combinations thereof. As illustrated in FIG. 6, TB offload queue header 606 in CC0 for 5G NR may include CB descriptor headers 6061, 6062, and CB descriptor header 6061 for CBO in error (CB_id=0) may include a pointer to next CB descriptor header 6062 for CB 25 in error (CB_id=25). In this example, the CBs between CBO and CB25 may be successfully decoded and pass the code check. Therefore, their corresponding memory blocks for buffering the soft bits may be released and reused by another CB. As a result, their related information is not shown in FIG. 6. As illustrated in FIG. 4, in a case of a CB that passes the code check, an indicator signal 414 may be generated and sent out (e.g., through error-detecting circuit 406 and the RX chip of the UE) to enable internal memory 410 to release one or more memory blocks corresponding to the success CB. In a case of a CB that fails the code check, another indicator signal 414 may be generated and sent out to enable internal memory 410 to save TB offload queue header corresponding to the erroneous CB. In one instance, the indicator signal 414 may include one or more digits indicative of a result of the decoding and the code check.

[0065] In some embodiments, each of CB descriptor headers 6061, 6062 may include one or more pointers, and each pointer may indicate a location of one of the memory blocks associated with the erroneous CB. Further, one pointer may point to/locate another. In this manner, one or more memory blocks 602, 604 of one erroneous CB can form a linked-list data structure as shown in FIG. 6 through TB offload queue header 606 (that includes CB descriptor headers 6061, 6062). The location herein may refer to the memory address of a memory block or any other manners that can help identify the memory block.

[0066] Some embodiments of the present disclosure may allow a subset of the one or more memory blocks 602 for one erroneous CB being arranged in internal memory 410, while others are arranged in external memory 308. In other embodiments, all the memory blocks of one erroneous CB may be arranged in the same memory, either all in internal memory 410 (such as CBO in FIG. 6) or all in external memory 308 (such as CB25 in FIG. 6). As shown in FIG. 6, each of CB descriptor headers 6061, 6062 may include one or more memory descriptor headers 6063 configured to describe corresponding memory blocks, e.g., an individual memory block size.

[0067] Some embodiments of the present disclosure may maintain free internal-memory queue header 6081 for managing available/free memory blocks in internal memory 410 and may maintain free external-memory queue header 6082 for managing available/free memory blocks in external memory 308. Free memory queue headers 6081, 6082 may include one or more free memory pointers, and each memory pointer may point to an information descriptor indicative of a location and related information of one free memory block in the internal memory or in the external memory. One of the free memory pointers may point to/locate another. By this manner, the information about the free memory blocks corresponding to a respective free memory queue header may be formed in a linked-list data structure, as illustrated in FIG. 6. The linked-list data structure herein may refer to the information descriptor of each of the free memory blocks being formed in a chain form or in a tree form, such that finding one free memory block can help locate another, if any. In view of this, in certain instances, free internal-memory queue header 6081 and free external- memory queue header 6082 may be combined into one, forming a tree structure, each branch for a respective free memory block management.

[0068] Once one CB is decoded successfully and passes the code check, a corresponding memory block can be released, and an additional pointer may be added to a corresponding free memory queue header for this free memory block to be reused by another CB. In this way, the holes in the memory can be reduced and accordingly, the memory usage and efficiency can be increased. In one 5G NR example, under the TB having one CB of maximum 8448 bits, an average coding rate of 2/3, and bit-width of soft bits being 4, it may require, at most, 4 memory blocks for storing the soft bits of the maximum CB and result in the memory utilization ratio up to 77%.

[0069] Some embodiments of the present disclosure may preset (e.g., through a control firmware) a memory storage threshold for the internal memory, e.g., 80%. In response that usage of the internal memory at run time is equal to or above the threshold (i.e., an overflow status of the internal memory), instead of obtaining a free memory block still from the internal memory, free external-memory queue header 6082 may be accessed to obtain a free memory block from the external memory for storing the soft bits of an erroneous CB. Otherwise, to increase the usage of the internal memory, the memory blocks from the internal memory may be first obtained for storing the soft bits.

[0070] As described above, at an offloading stage, a queue for recording information about storing the erroneous CBs for each TB in the current transmission time interval (TTI) may be maintained. If an erroneous CB occurs, the information associated with the erroneous CB may be saved as TB offload queue header 606 in response to the decoding of the entire TB being completed. At the retransmission of the TB, the soft bits associated with the TB are required for the HARQ combining. For that purpose, at an onloading stage, previously saved TB offload queue header may be readily used as TB onload queue header. In this manner, HARQ combining circuit 412 may follow the linked-list data structure of TB offload queue header 606 in sequence to obtain the previously-stored soft bits of the erroneous CBs in one TB and accordingly perform the HARQ combining.

[0071] FIG. 7 illustrates a diagram of TB queue header management schemes, according to some embodiments of the present disclosure. In response that one TB is done with decoding for the current TTI, and an error associated with the TB is detected, TB offload queue header 702 for the descriptions of the one or more erroneous CBs may be saved. In some embodiments, the system may support carrier aggregation of multiple CCs for different technology. Therefore, TB offload queue headers 702 may include information to indicate the index of the CC and the technology thereof. As shown in FIG. 7, several TB offload queue headers 702 associated with different techniques may be saved in slot N.

[0072] As described above, in response to the erroneous CB(s), the feedback signal FB (shown in FIGs. 4 and 5) may be sent to notify the sender of the erroneous CB(s) and request the sender for a retransmitted TB. For performing the HARQ combining, to reduce the unnecessary memory copy from/to the internal memory, some embodiments may retrieve previously saved TB offload queue header 702 (e.g., through a control firmware) and use it as TB onload queue header 704 for providing memory information about the stored soft bits. In FIG. 7, three TB offload queue headers 702 for NR technology and the soft bits based on their corresponding erroneous CBs in slot N are directly copied to slot N+M to illustrate that TB offload queue headers 702 are readily used as TB onload queue headers 704. In some sense, TB offload queue header 702 and TB onload queue header may be identical. Therefore, the identical soft bits can be retrieved according to TB onload queue headers 704 (in some sense, TB offload queue headers 702). As the LTE sender may schedule the HARQ retransmission independently from the NR sender, the retransmission time slot may be different between the NR and LTE technology. Therefore, only for illustration in FIG. 7, TB offload queue header in LTE technology is retrieved and used as TB onload queue header in a different slot, e.g., in slot N+K.

[0073] In this manner, HARQ combining circuit 412 may locate the first erroneous CB according to TB onload queue header 704 (in some sense, TB offload queue header 702) and follow the linked-list data structure of TB onload queue header 704 in sequence to obtain the previously- stored soft bits for each erroneous CBs corresponding to one TB. The retrieved soft bits may be combined with the retransmitted soft bits of the TB. As illustrated in FIGs. 6 and 7, for simplicity of illustration, all the soft bits of one CB are stored in the same memory, either in the internal memory or in the external memory. The present disclosure, however, does not place limitations hereto. A portion of the soft bits of one erroneous CB may be stored in the internal memory, while another portion thereof may be stored in the external memory. By the memory management schemes described above based on the linked-list data structure, the memory block(s), either in the internal memory or in the external memory, for storing the soft bits can be identified for retrieving the soft bits.

[0074] In some embodiments, the present disclosure may provide a caching mechanism. As the external memory is associated with a large jitter, the caching mechanism may provide a manner to match a decoder hardware accelerator speed to compensate for the latency of the external memory. In certain aspects, at on offloading stage, before moving data to the external memory, the data may be first cached in the internal memory.

[0075] Referring to FIG. 7, at an offloading stage in slot N, the soft bits of CB0 706 may be cached to internal memory 410 in the first place. While checking a watermark of internal memory 410 for a usage thereof, if the current usage is equal to or above the preset threshold of the memory usage (i.e., an overflow status of the internal memory), some embodiments may trigger an offloading of the last-stored CB0 706 to external memory 308 from internal memory 410. Further, the memory block(s) in internal memory 410 associated with CB0 706 may be released (shown in FIG. 7 in broken lines), and information of the free memory block(s) may be added to free internal -memory queue header 6081.

[0076] On the other hand, at an onloading stage, the soft bits stored in the external memory may be copied to internal memory before the HARQ combining. As illustrated in FIG. 7, one or more free memory blocks may be obtained through free internal-memory queue header 6081 for buffering the data from the external memory before the HARQ combining. It can be understood that although only free internal-memory queue header 6081 is shown in FIG. 7, free external- memory queue header 6082 may also be implemented.

[0077] Some embodiments also provide a method of implementing the HARQ operations. FIG. 8 illustrates a flow chart of an exemplary method of implementing HARQ, according to some embodiments of the present disclosure. As illustrated in FIG. 8, the method may include:

[0078] At 802: storing soft bits, corresponding to one or more erroneous CB, in memory according to a TB queue header.

[0079] As described above, the one or more erroneous CBs may be identified based on the decoding of the one or more CBs of a TB. As illustrated in FIG. 4, the CBs may be decoded through decoding circuit 404 and code-checked through error-detecting circuit 406. Based on the above operations, it can be determined whether the CBs are successfully decoded to identify the erroneous CB(s). As illustrated in FIG. 5, some embodiments may continue decoding of the CBs even after a first erroneous CB in one TB. The memory may include internal memory 410 at an SoC and external memory 308 outside the SoC and may be divided into a plurality of memory blocks as shown in FIG. 6.

[0080] FIG. 9 illustrates another flow chart of an exemplary method of implementing HARQ according to some embodiments of the present disclosure. In some embodiments, as shown in FIG. 9, the storing operations at 802 may include:

[0081] At 902: storing first soft bits, corresponding to a first erroneous CB of the TB, in first linked memory blocks of the plurality of memory blocks based on a TB queue header; and [0082] At 904: storing second soft bits, corresponding to a second erroneous CB of the TB, in second linked memory blocks of the plurality of memory blocks based on the TB queue header. [0083] As shown in FIG. 6, some embodiments of the present disclosure may include TB offload queue header 606, and through which the memory blocks for storing the erroneous CB may be linked or associated. In this manner, the memory blocks for storing the soft bits associated with one TB may form a linked-list data structure, such as all the soft bits can be retrieved through TB offload queue header 606. In certain instances, internal memory 410 may include at least one subset of the first linked memory blocks or the second linked memory blocks.

[0084] In some embodiments, the method may further include:

[0085] At 804: retrieving the soft bits of the one or more erroneous CBs according to the

TB queue header for soft combination of the one or more erroneous CBs.

[0086] As shown in FIG. 7, some embodiments of the present disclosure may use TB offload queue header 702 as TB onload queue header 704. In this manner, the stored soft bits in the linked-list data structure can be retrieved according to TB onload queue header 704 (in some sense, TB offload queue header 702) to be combined with the retransmitted soft bits in the HARQ combination.

[0087] As described above, the combined CB may be sent to decoding circuit 404 again for the decoding and to error-detecting circuit 406 again for the code check. If all the CBs pass the code check, these successful bits may be concatenated through TB concatenating circuit 408 to form one TB for transmission/storage. On the other hand, if the combined soft bits of the same CB still foil at error-detecting circuit 406, the combined soft bits may be stored again, and storage information regarding the memory blocks corresponding to the combined soft bits may be attached to/ saved in TB offload queue header. In some embodiments, the combined soft bits may be stored in linked memory blocks different from the linked memory blocks that stored the soft bits before the soft combination. In such a way, with another retransmitted TB, the combined soft bits may be retrieved and another soft combination may be performed to combine the retrieved combined soft bits with newly -received soft bits based on the second retransmitted TB so as to increase the coding gain.

[0088] Some embodiments of the present disclosure provide a system that implements HARQ. The system may include an external memory and an SoC that may include an internal memory and at least one processor. In certain aspects, each of the external memory and the internal memory may be divided into a plurality of memory blocks. The at least one processor may be configured to store soft bits, corresponding to one or more erroneous CBs, in the plurality of memory blocks and retrieve the soft bits according to a TB queue header for soft combination of the one or more erroneous CBs. The one or more erroneous CBs may be identified based on decoding results, through a decoding circuit of the SoC, on one or more CBs of a TB. In certain other aspects, first soft bits of the soft bits, corresponding to a first erroneous CB of the TB, may be stored in first linked memory blocks of the plurality of memory blocks based on the TB queue header, and second soft bits of the soft bits, corresponding to a second erroneous CB of the TB, may be stored in second linked memory blocks of the plurality of memory blocks based on the TB queue header. The TB queue header may be configured to associate the first linked memory blocks with the second linked memory blocks. In certain aspects, the internal memory may include at least one subset of the first linked memory blocks or the second linked memory blocks.

[0089] In some embodiments, the TB queue header may include a first CB descriptor header and a second CB descriptor header. The first CB descriptor header may include one or more first pointers configured to link each memory block in the first linked memory blocks and a second pointer configured to point to the second CB descriptor header. The second CB descriptor header may include one or more second pointers configured to link each memory block in the second linked memory blocks.

[0090] In some embodiments, the internal memory may include a memory storage threshold. In response to a usage of the internal memory being equal to or greater than the memory storage threshold, the at least one processor may allocate one memory block from the external memory and store a portion of the soft bits to the memory block of the external memory.

[0091] In some embodiments, in response to an indicator signal indicating a code-check failure of one CB of the TB, the at least one processor may identify the CB as an erroneous CB and save the TB queue header corresponding to the erroneous CB.

[0092] In some embodiments, in response to the erroneous CB, a decoding circuit of the SoC may continue decoding remaining CBs of the TB, following the erroneous CB, till an end of the TB.

[0093] In some embodiments, in response to receiving a retransmitted TB, the at least one processor may obtain the TB queue header and retrieve the soft bits of the one or more erroneous CBs according to the TB queue header, and perform the soft combination, through a combining circuit of the SoC, of the soft bits with soft bits of CBs, corresponding to the one or more erroneous CBs, of the retransmitted TB to form combined soft bits for decoding.

[0094] In some embodiments, in response to an indicator signal indicating a code-check failure of the combined soft bits, the at least one processor may store the combined soft bits in third linked memory blocks of the plurality of memory blocks based on the TB queue header for another soft combination.

[0095] In some embodiments, sizes of the plurality of memory blocks may be the same.

[0096] In some embodiments, a size of each of the plurality of memory blocks is determined according to CB sizes supported by the system.

[0097] In some embodiments, the internal memory may include all of the second linked memory blocks; or the external memory may include all of the second linked memory blocks.

[0098] In some embodiments, the internal memory may include a memory storage threshold. In response to a usage of the internal memory being equal to or greater than the memory storage threshold, the at least one processor may allocate each of the second linked memory blocks from the external memory and store the second soft bits to the second linked memory blocks of the external memory.

[0099] In some embodiments, the at least one processor may be further configured to maintain a free internal -memory queue header. The free internal-memory queue header may include one or more free internal -memory pointers. Each of the one or more free internal-memory pointers may indicate a location of a free memory block in the internal memory. A first free internal-memory pointer of the one or more free internal-memory pointers may be configured to point to a second free internal-memory pointer of the one or more free internal-memory pointers.

[0100] In some embodiments, the at least one processor may be configured to access the free internal-memory queue header to obtain one free internal-memory pointer of the one or more free internal-memory pointers and store a portion of the soft bits in a free memory block of the intemal memory indicated by the free internal-memory pointer.

[0101] In some embodiments, the at least one processor may be further configured to maintain a free external-memory queue header that comprises one or more free external -memory pointers. Each of the one or more free external-memory pointers may indicate a location of a free memory block in the external memory. A first free external-memory pointer of the one or more free external memory pointers may be configured to point to a second free external -memory pointer of the one or more free external -memory pointers.

[0102] In some embodiments, the at least one processor may be configured to buffer soft bits of one CB in a subset of the plurality of memory blocks. In response to receiving an indicator signal indicating a code-check pass of the CB corresponding to the buffered soft bits, the at least one processor may release the subset of the plurality of memory blocks corresponding to the CB and add a free-memory pointer to a free memory queue header to indicate a location of the subset of the plurality of memory blocks and an available status of the subset of the plurality of memory blocks.

[0103] In some embodiments, in response to determining that each CB of the TB is successfully decoded, the at least one processor may release the TB queue header corresponding to the TB.

[0104] Some embodiments of the present disclosure provide an SoC that implements HARQ. The SoC may include an internal memory divided into a plurality of memory blocks and at least one processor. The at least one processor may be configured to store soft bits, corresponding to one or more erroneous CBs, in the plurality of memory blocks. The one or more erroneous CBs may be identified based on decoding results, through a decoding circuit of the SoC, on one or more CBs of a TB. In certain aspects, the soft bits may include first soft bits and second soft bits. The first soft bits may be stored in one or more first memory blocks, and the second soft bits may be stored in one or more second memory blocks. In certain other aspects, the plurality of memory blocks may include the one or more first memory blocks associated with a TB queue header and the one or more second memory blocks associated with the TB queue header. The TB queue header may be configured to associate the one or more first memory blocks with the one or more second memory blocks. The at least one processor may be further configured to retrieve the soft bits according to the TB queue header for soft combination of the one or more erroneous CBs.

[0105] In some embodiments, the TB queue header may include a first CB descriptor header and a second CB descriptor header. The first CB descriptor header may be configured to associate each memory block in the one or more first memory blocks and to point to the second CB descriptor header. The second CB descriptor header may be configured to associate each memory block in the one or more second memory blocks.

[0106] In some embodiments, the internal memory may include a memory storage threshold. In response to a usage of the internal memory being equal to or greater than the memory storage threshold, the at least one processor may allocate one memory block from a memory external to the SoC, store a portion of the soft bits to the allocated memory block, and, according to one CB corresponding to the portion of the soft bits, associate the allocated memory block to the TB queue header.

[0107] Some embodiments of the present disclosure provide a method of implementing HARQ. The method may include storing soft bits, corresponding to one or more erroneous CBs, in memory. The one or more erroneous CBs may be identified based on decoding results, through a decoding circuit of a system-on-chip (SoC), on one or more CBs of a TB. In certain aspects, the memory may include an internal memory of the SoC and a memory external to the SoC that are divided into a plurality of memory blocks. The storing of the soft bits may include storing first soft bits of the soft bits, corresponding to a first erroneous CB of the TB, in first linked memory blocks of the plurality of memory blocks based on a TB queue header; and storing second soft bits of the soft bits, corresponding to a second erroneous CB of the TB, in second linked memory blocks of the plurality of memory blocks based on the TB queue header. The TB queue header may be configured to associate the first linked memory blocks with the second linked memory blocks. The internal memory may include at least one subset of the first linked memory blocks or the second linked memory blocks. The method may further include retrieving the soft bits of the one or more erroneous CBs according to the TB queue header for soft combination of the one or more erroneous CBs.

[0108] In some embodiments, the TB queue header may include a first CB descriptor header and a second CB descriptor header. The first CB descriptor header may include one or more first pointers configured to link each memory block in the first linked memory blocks and a second pointer configured to point to the second CB descriptor header. The second CB descriptor header may include one or more second pointers configured to link each memory block in the second linked memory blocks.

[0109] The present disclosure improves power consumption and avoids performance loss due to the multiple accesses to and the traffic congestion of the external memory. Considering that the CB error rate is relatively lower than the TB error rate under a typical operation condition, some embodiments of the present disclosure do not terminate the decoding at a first erroneous CB. Instead, the decoding continues till the end of the TB to avoid the waiting time accumulated to the latency. Due to the low CB rate, a size increase of the internal memory is not significant. Moreover, fewer resources, less power consumption, and more efficiency can be expected with the present disclosure.

[0110] The foregoing description of the specific embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

[0111] Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

[0112] The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

[0113] Various functional blocks, modules, and steps are disclosed above. The particular arrangements provided are illustrative and without limitation. Accordingly, the functional blocks, modules, and steps may be re-ordered or combined in different ways than in the examples provided above. Likewise, certain embodiments include only a subset of the functional blocks, modules, and steps, and any such subset is permitted.

[0114] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments but should be defined only in accordance with the following claims and their equivalents.