USING CYCLIC LOOP IMAGES

RELATED APPLICATIONS

[0001] This disclosure claims the benefit of U.S. Provisional Pat. App. No. 63/038,040, titled “PAM4 CYCLIC EYE IMAGE REPRESENTATION FOR WAVEFORM DATA,” filed June 11, 2020, U.S. Provisional Pat. App. No. 63/039,360, titled “READ/WRITE BURST SEPARATION AND MEASUREMENT USING NOVEL CYCLIC EYE PLOT AND MACHINE LEARNING,” filed June 15, 2020, U.S. Provisional Pat. App. No. 63/041,041, titled “CYCLIC EYE IMAGE REPRESENTATION FOR WAVEFORM DATA,” filed June 18, 2020, and U.S. Provisional Pat. App. No. 63/177,930, titled “CYCLIC EYE WITH MACHINE LEARNING FOR MEASURING OR TUNING AN OPTICAL TRANSMITTER,” filed April 21, 2021, each of which hereby incorporated herein by reference in their entirety.

[0002] This disclosure is related to the following patent applications: U.S. Pat. App. 17/345,342, filed June 11, 2021, with the title, “SYSTEM AND METHOD FOR SEPARATION AND CLASSIFICATION OF SIGNALS USING CYCLIC LOOP IMAGES,” (Atty-Dkt 12222-US1), U.S. Pat. App. 17/345,283, filed June 11, 2021, with the title, “A CYCLIC LOOP IMAGE REPRESENTATION FOR WAVEFORM DATA,” (Atty-Dkt 12223-US1), and U.S. Pat. App. 17/345,312, filed June 11, 2021, with the title, ’’SYSTEM AND METHOD FOR MULTI LEVEL SIGNAL CYCLIC LOOP IMAGE REPRESENTATIONS FOR MEASUREMENTS AND MACHINE LEARNING,” (Atty-Dkt No. 12224-US2).

TECHNICAL FIELD

[0003] This disclosure relates to identifying data in two-way buses, more particularly to identifying and classifying the data direction. BACKGROUND

[0004] In some situations, identifying acquired bursts of data on two-way buses and classifying in which direction the data signal is traveling is useful. If test and measurement instruments like oscilloscopes had unlimited channels, it would provide the ability to acquire the needed command bus lines to separate read and write bursts on such bi-directional buses. However, it becomes a challenge when only one or two probes are available.

[0005] An example of such a signal is in DDR5 memory, the standard for double-data rate memory version 5 memory. This represents the next major change in computing memory increasing speed and density but keeping a similarly dimensioned DIMM (dual in-line memory module). The system channel characteristics differ significantly between read and write operations as seen at the probe point. The read signals must be processed and measured separately from the write signals, so they must be separated.

[0006] Users often use eye diagrams, so-called because the opening between two waveforms looks like an eye, to analyze signals. But, the increasing speeds of memory on the same printed circuit board (PCB) material results in waveform diagrams have “closed” eyes for write data bursts that arrive at the memory. The DDR5 DRAM supports data rates from 3200 MT/s to 6400

MT/s. This increase in the data rate is achieved without changing the signaling scheme of data pins, i.e. DQ bus is still single-ended -same as DDR3/4. However, due to the many impedance mismatched points that exists in the DDR5 channel, inter-symbol interference (ISI) due to reflections is expected to increase. At data rates of 4800 MT/s and higher, the data eye at the

DRAM probe point, e.g. a solder ball, is expected to be closed. A 4-tap DFE is implemented in the DDR5 DRAM receiver to help equalize the DQ signals and mitigate this problem.

[0007] While the DIMM PCB on which the memory mounts and the size of the board has remained the same, the memories are doubling in size. In addition, oscilloscopes typically only have four channels, limiting the number of parallel data, clock, and command address lines acquirable for analysis and testing.

[0008] Typically, the DQS clock strobe signal and the DQ data signal are the most interesting for analysis. Two probes are required. A preamble occurs on the DQS signal before each data burst and this can be used for locating the beginning of bursts of read or write data. In the past, for previous DDR DRAM protocols like DDR3/DDR4, there was a phase difference between read and write bursts, meaning DQS and DQ on the write bursts were center aligned and on the read bursts were edge aligned. Also, the command bus had separate WE (Write Enable), RAS (Row Access Select), CAS (Column Address Select) signals available which were used to identify read or write bursts. However, DDR5 replaces the WE/CAS/RAS signals with a compact 14 pin Command Address (CA) bus and decoding is required to figure out read/write commands. This typically means getting access to all 14 CA pins, which is not practical. Also, there is no more distinct phase difference between DQS and DQ signals like in DDR4/DDR3. In DDR5, DQS and DQ on the write path could have a fixed offset of up to 3 UI (unit intervals) that i programmed during the bootup process.

[0009] Therefore, what is needed is a method to use only data lines in order to identify whether burst signals are read or write. Embodiments of the disclosed apparatus and methods address shortcomings in the prior art.

BRIEF DESCRIPTION OF THE DRAWINGS [0010] Fig. 1 shows a representation of a cyclic loop image.

[0011] Fig. 2 shows an example of a DDR5 memory data burst signal.

[0012] Fig. 3 shows an example of a DDR5 memory data burst signal with reflections from a mismatched load. [0013] Fig. 4 shows an example of a DDR5 memory data burst signal with reflections from a mismatched load and with trace intersymbol interference (ISI) loss.

[0014] Fig. 5 shows a trace between a test probe and a mismatched load for a write operation. [0015] Fig. 6 shows a trace between a test probe and a mismatched load for a read operation. [0016] Fig. 7 shows a graph of trace loss modeled by an exponential equation compared to two actual measured traces.

[0017] Fig. 8 shows an embodiment of a system for creation and analysis of cyclic loop images. [0018] Fig. 9 shows an example of an oscilloscope screen of the waveforms used for creating a cyclic loop diagram.

[0019] Fig. 10 shows examples of cyclic loop images.

[0020] Fig. 11 shows an example of a DQ random data signal with no reflections and no ISI and the resulting cyclic loop image.

[0021] Fig. 12 shows an example of a measurement from a standard YT trace display.

[0022] Fig. 13 shows an example of measuring reflection delay.

[0023] Fig. 14 shows examples of measuring coefficients.

[0024] Fig. 15 shows an example of measuring reflection coefficients using the cyclic loop diagram.

DETAILED DESCRIPTION

[0025] Embodiments of the disclosure address the problem of identifying acquired bursts of data on two-way buses and classifying which direction the data travels. For the case of DDR5 memory, oscilloscopes generally do not have channels and/or the device under test (DUT) does not have sufficient space for connecting enough probes to acquire the needed command bus lines to differentiate between read and write data bursts. However, the system channel characteristics differ significantly between read and write operations as seen at the probe point. Read signals must be processed and measured separately from write signals. The embodiments here address the need to perform this separation using only one or two probes. One aspect of the embodiments lies in the use of a unique cyclic loop image that is more sparse than a traditional eye diagram. The cyclic loop images focus more on the edges of the signals, which contain most of the information that characterizes the system response.

[0026] The embodiments utilize an apparatus and method to create a cyclic loop image as an XY plot of the incoming signal. The cyclic loop images of the embodiments facilitate numerous measurements, and provide a simplified image suitable for using, for example, as an input to existing pre-trained neural networks or other machine learning systems for classification of read versus write in particular data bursts. Embodiments may also have applications to other binary encoded signals such as non-return-to-zero (NRZ) or multilevel signals such as pulse-amplitude- modulated signals (e.g., PAM4). The embodiments also address using the cyclic loop image coupled with machine learning in order to perform read and write separation for memory systems. Fig. 1 shows an example of a cyclic loop diagram 10.

[0027] The embodiments use a simple but robust algorithm to create an XY plot of the input signal. The vertical Y axis consists of the signal itself. For DDR5 applications, this signal would typically be either the DQ data burst signal, or the DQS data strobe clock signal. The horizontal X axis consists of a sweep signal created by processing the DQ, or the DQS, signal. This processing creates a unique linear or a somewhat linear ramp sweep signal only at edge transitions in the data pattern. No ramps occur in intervals in which the signal level does not change, e.g. long intervals of highs or long intervals of lows. This takes a unique approach that differs from a classical Lissajous figure. Embodiments automatically position these ramps such that the XY signal path is a closed loop line containing all rising edges above the upper side of the loop and all falling edges on the lower side of the loop.

[0028] Since edges in the system contain most of the information defining the system transfer function, this simple image results in a cyclic display that captures all cycles of the waveform in one image and yet it eliminates a lot of the extra unnecessary data points that a typical eye diagram would contain. The resulting plot may, depending on the waveform characteristics, have appearance similarities to magnetic hysteresis BH plots. However, there are significant differences in the aspects of the horizontal ramp creation and how they are generated and how it applies to PRBS (pseudo-random binary sequence) data pattern.

[0029] A major advantage lies in the simplicity of the implementation and its robustness. The overall approach represents several methods for creating the X axis ramp like signal. A specific embodiment discussed below regarding Fig. 8 addresses a simple process in complexity and processing speed. This approach may produce some distortion in the edge shape. For purposes of machine learning system recognition, this method will increase compute speed, while at the same time still allow the machine learning algorithm to classify it. For example, the machine learning system can classify read versus write operations in a memory system by looking only at the DQS or the DQ signal.

[0030] One should note that while the discussion below addresses classification of memory signals, embodiments are not limited to that application. No such limitation should be inferred. Embodiments may be used for other bi-directional systems where system characteristics may be different depending on the direction of signal propagation. In addition, the signals may consist of read or write data burst signals, or any binary encoded signals with two levels like non-return-to- zero (NRZ) signals, or pulse-amplitude modulated signals with more than two levels, such as PAM4.

[0031] The cyclic loop image is simplified plot that specifically shows, signal attributes such as the system response, non-linearity for rising compared to falling edges, SNR, amplitude, reflections delay, reflection coefficient, etc. The XY image created has a method of reducing the unnecessary parts of a waveform display and showing only the important attributes needed for classifying the difference between the write operation system response and the read operation response. The reduced image size and the simplified closed loop path representing the system act as ideal inputs for a pre-existing, pre-trained image processing neural network or other machine learning network or system. In addition, multiple measurements as described above can be made using the cyclic loop image.

[0032] Once the DQS and DQ bursts have been classified and separated into separate waveforms, these waveforms are amplitude as a function of time, and may be further processed with operations such as creating virtual test point filters to move the view of the actual probe point. This removes the steps from reflections of memory loads that are not matched to the transmission line. It does not actually remove the reflection, but it removes the delay from the reflections, resulting in no steps in the rising and falling edges, but the amplitude is usually increased by the reflection. In the case of DDR5, as well as other possible applications, a DFE equalizer is applied to the separated write bursts. Finally, the processed waveforms may be processed by DDR compliance application or by jitter analysis application software for further analysis.

[0033] Therefore, what is needed and addressed by the embodiments is a method to use only DQS and/or DQ data lines to identify whether burst signals are read or write. The embodiments also utilize a unique way to create a cyclic loop image, instead of the traditional eye diagram, to facilitate numerous measurements. The cyclic loop provides a simplified image suitable for input to existing pre trained neural networks for classification of read versus write signal bursts. [0034] Figs. 2-4 show examples of DQS burst signals. Fig. 2 shows an example of an ideal DQS burst signal 12 in DDR5 memory systems. Fig. 3 shows an example of a DDR5 memory DQS burst signal 14 that includes reflections from a mismatch load. Fig. 4 shows an example of a DDR5 DQS signal 16 with reflections from a mis-matched load, and with trace inter symbol interference (ISI) loss.

[0035] The system transfer function allows for distinguishing between read and write data bursts, as it typically differs between the two. The system hardware has different characteristics for read versus write operations. The loads at the ends of the transmission line may differ. The voltage amplitude at the memory transmitter may be different than that at the SOC (system on a chip) transmitter. The delay times of reflections may be different.

[0036] In addition, for many situations the probe physically connects to an interposer board mounted very close to the memory chip and far from the SOC. Fig. 5 shows a trace 20 on a device under test between probe 22 from test and measurement instrument 26 and mismatched memory load 24. Trace 20 is short with the signal observed at the probe 22 point having a large reflection. This results in a high reflection coefficient, and small delay. This results in pulse amplitude at the probe point that is larger than the incident pulse amplitude from the SOC 28. However, the long trace 30 from SOC to the probe 22 point will have loss that will cause a loss of signal amplitude from the SOC. Therefore, the trace ISI loss tends to lower the pulse amplitude at the probe point, and the memory reflection coefficient tends to increase the amplitude at that point. This occurs because the impedance of the memory load is greater than the transmission line impedance. This is the situation for typical DDR5 system probed with an interposer 32 for a write operation.

[0037] Fig. 6 shows a read operation. For this case, the memory 24 has become the transmitter. The probe 22, typically connected through the interposer 32, is only separated from the memory 24 by a short trace 34 with low loss. This makes the incident pulse at the probe 22 similar in amplitude to what the memory transmitted. The signal then travels down the long trace 36 to the SOC 28 with a large impedance mismatch which reflects some signal back to the probe 22. The long trace 36 has high loss reducing amplitude of the reflected signal. This reflected signal comes back to the probe 22 and usually increases the amplitude seen at the probe because the SOC 28 load impedance is larger than the transmission line characteristic impedance. For this case the delay time is much longer and the SOC load may be different than the memory load when it was the receiver.

[0038] The delay time of the reflection and the reflection coefficient value can be computed by doing a couple of cursor measurements on the waveform acquired by the probe 22 and test and measurement instrument 26, such as an oscilloscope. Then, if the SOC load is known, the trace impedance can be computed given the reflection coefficient and the SOC load value. Or if the trace impedance, i.e. the characteristic impedance, is known, then the SOC impedance can be computed i.e. Using standard transmission line theory equation:

Z = — l-rZ 0 (1) ’ where Z is the SOC memory load and Z0 is the long trace transmission line impedance. G is the reflection coefficient.

[0039] Overall, for the DDR5 model example, the primary system characteristics influencing the pulse shape are: 1) the loss of the long trace which can be represented by a single parameter, a, 2) the delay of the reflections, t, 3) the reflection coefficient, G, and 4) the output voltage gain constant of the transmitter, K. It appears, based on looking at several examples in the industry, that this model works reasonably well for defining a system equation that can simulate the types of waveforms observed in these systems. These parameters can be configured into a frequency domain equation shown below in equation (6). This model approximates the response of the system shown in Figs. 5 and 6.

[0040] The first step to create a modeled transfer function, H, to model the long trace length between SOC and probe point as shown in (2). n = 0 ...N — 1 (3) where N is the length of the frequency domain vector in samples from DC to fs, the sample rate. The value of n is the index to various samples in the frequency domain.

[0041] The value of a is a constant that determines loss characteristic of different PCB trace lengths. The exponential term only defines the magnitude response. To assign an appropriate phase response, the minimum phase response can be obtained from (4). h = rceps(ifft(H )) (4) where rceps is a Matlab function that returns minimum phase impulse response of Y.

H = ffm (5) where H is now the modeled minimum phase frequency response of the PCB trace from SOC to the probe point. where fs is the sample rate in Hz and n is the frequency index, and N is the number of samples from DC to fs. G is the reflection coefficient, and t is the reflection delay. The part of equation (2) with the exponent -an/N creates the magnitude roll off that closely matches typical PCB traces as shown in Fig. 7. Therefore, a is the variable that determines which loss curve is created as shown in the plots in Fig. 7, X(n) represents the signal at the input to the model.

[0042] The previous discussion has described the system modeling and measurement issues required for DDR5 memory read versus write separation. This lays the foundation for understanding why embodiments of the disclosure are needed.

[0043] A first procedure commonly used when setting up machine learning applications is data reduction. For example, the more parameters and data inputs there are into the machine learning algorithm the more difficult it is to arrive at a unique correct solution. In addition, more input data requires more training time and more runtime processing. Therefore, a first step is to look at all the input parameters and data and determine which parameters and which data, have very little effect on the outcome. These items shall be eliminated as inputs to the system.

[0044] The discussion above presented a set of four of the most basic elements needed to understand the shape commonly seen in DDR waveforms. Those four parameters were a, which represents the long trace ISI in the model, and t, which represents the reflection delay time, and G, which represents the reflection coefficient, and K, which represents an amplitude difference constant between the SOC transmission for write operations, and the memory transmission amplitude from memory for a read operation. These three parameters, excluding K, may affect ISI, inter symbol interference. The value of a represents ISI due to trace loss and the reflection coefficient and delay represents ISI due to reflections caused by load mismatch impedance. [0045] Fig. 8 shows an embodiment of a system used to classify data burst signals. The system pulse response can be viewed and derived in multiple different ways. For example, the waveform plot of amplitude as a function of time is one way. However, there are disadvantages of giving that view to a machine learning system in the sense of different bit rates, and different data patterns and how to incorporate it. Likewise, the signal can be viewed in the frequency domain and in the cepstrum domain. However, if one attempted to use these views for input to a machine learning systems, there is the problem of having the signal pattern interfere with the view of trying to see the system response. Deconvolution is needed. There are many issues and details that make implementing these views difficult to setup and deal with.

[0046] For example, complex clock recovery techniques may be required, and complex gating and interpolation may be required as part of a deconvolution process. There are other issues such as the short reflection delay of the interposer results in resolution issues with cepstrum and spectrum views. Large ISI make it more difficult to extract key features.

[0047] The embodiments here resolve the issues involved in these other methods and generate a cyclic loop image that captures all of the edge transitions into a single closed looped XY plot that simply cycles over the same path across the entire length of the input data record. The input data may be a clock signal during a burst interval such as in a DDR5 memory system. The input signal may be a random data pattern such as in DQ burst interval in a DDR5 memory system. While not shown here, the input signal or signals may undergo interpolation or decimation to increase or decrease the number of samples to fill in the resulting image, or to reduce the amount of data used in the artificial intelligence/machine learning system. Reducing the amount of data, often referred to as dimensionality reduction, allows the machine learning system to function more efficiently and accurately. The system may also subtract a mean of the incoming signal from the incoming signal to remove a DC offset from the incoming signal.

[0048] As mentioned above, the input signal may be any kind of waveform that has high and low levels with edge transitions with positions determined by a system clock. The X-axis signal is considered to be a linear sweep ramp signal, or a ramp like signal, derived from the input signal. This may be thought of in terms of a standard oscilloscope horizontal sweep ramp. This ramp is synchronized with the input signal directly because it relies on the input signal in generation. [0049] The related patent applications mentioned above detail different approaches to the generation of cyclic loop images and their associated data. For an example of a specific embodiment of cyclic loop image creation, the horizontal sweep ramps are generated by first running the input signal through a circuit that creates a square pulse representation of the input signal, referred to here as a clipper circuit 42, 43. In one embodiment, this circuit multiplies the signal by a large value, e.g. 500, and then if the signal is greater than zero it is assigned to an ideal high value constant that will be same as the input voltage nominal high level. If the signal is less than or equal to zero it is assigned to the low-level constant value. In the embodiment of Fig. 8, the input signal DQ goes through a clipping circuit 43 and the DQS signal goes through a clipper circuit 42.

[0050] After the clipping circuit, the signal goes through a short-term integrator 40 and 45. In this embodiment the integrators take the form of boxcar filters. The width of the boxcar filter shall be equal in width to one UI of the input signal. Since there are an integer number of coefficients, it may be the number of coefficients at the given sample rate that is equal to the UI interval, or a fraction of a sample interval less than the UI width. This creates a positive-going ramp-like signal during the time period of positive edges of the input signal, and it creates a negative-going ramp-like signal for time periods during a falling edge of the input signal. For long intervals of multiple UI where there are no edges, there is no ramp, a unique feature of this approach. This results in only positive and negative edge positions appearing in the closed loop path of the cyclic loop image. [0051] All data for multiple UI intervals with no edges is in the image but only at two positions on screen such that only the edges showing the characteristics of the system model are fully visible in a very simple looped path in the image. If the ISI is high then there will be a wider variation of paths followed around the loop. This will cause the center of the cyclic loop to close more. For a clock signal that changes for every UI the entire waveform data set repeatedly traces around the same closed loop path on the XY cyclic loop display. This is also a novel aspect o because all edges are traced along the looping path. This results in the cyclic loop image that does not have a lot of overlays of positive and negative edges that obscures much of the signal detail as in traditional eye diagrams.

[0052] The burst detector 44 detects bursts of read and write data. Each burst of data must be detected so that it can be processed and classified as a read or write operation. For DDR5, the burst detection can be accomplished by looking at the DQS clock signal. It stays at zero until a burst starts. There is a preamble of several UI intervals that will have a low for more than one UI in a row. This preamble occurs on the DQS signal. This is the basis for detecting the start of a burst. After that, the DQS signal in the burst alternates between high and low each UI. The DQ signal will contain random highs and lows at each UI interval.

[0053] The burst gates 46 and 48 control the data used to produce the cyclic loop image based upon the signal from the burst detector. In the embodiment of Fig. 8, the burst gates comprise a multiplier between the input signal and a 1 or 0 input from the burst detector. The main system controller 76 will sequence the entire system so that only one burst at a time is processed and classified.

[0054] The system may create one or two plots, such as 50 and 52, one plot 52 with the acquired DQS on the vertical axis and the sweep ramp output of the clipper and boxcar filter on the horizontal, X axis, applied to the DQS signal. The second plot 50 would have the DQ signal on the Y axis and the sweep ramp created from the cyclic loop algorithm applied to the DQ signal. These two plots may be represented as two relatively low-resolution cyclic loop images which can be used as input to the deep learning neural network to train for classification. These two plots may also be rendered on the display screen for the user to analyze and use to measure various characteristics of the input waveforms, DQ, and DQS. In some embodiments, the system may store the cyclic loop image data in a memory (not shown), and not necessarily render the cyclic loop images on a display.

[0055] The system may take multiple measurements using the measurement unit 54, the measurements made from observing the cyclic loop images or the data used to form the cyclic loop images. These measurements may optionally be used as parameter input for part of the machine learning. The values of some of the measurements may be used to identify whether the system model consists of a read or a write. The measurement unit 54 may comprise one or more hardware circuits, software measurement routines, or any combination of hardware and software implementations.

[0056] Measurement examples include reflection delay, reflection coefficient, ISI, signal-to- noise ratio (SNR), and non-linearity. The system can obtain the angle between two radial lines from the center of the loop to the correct points on the closed loop for reflection delay. This angle is converted into the time delay of the reflection. Since the rising and falling edges appear in the XY display, the ratio of incident and reflected signals can be measured and the reflection coefficient can be computed. This is most accurate and easy to do when the trace ISI is low. When trace ISI is high it becomes more difficult to tell where to measure from and it becomes less accurate. A relative value of ISI can be obtained by looking at the overall outer diameter of the loop, and the inner diameter of the loop. Some of this will be due to noise. But in a noiseless system, no ISI translates into a single thin line looped path. In contrast, high ISI closes down the loop and widens the loop path thickness.

[0057] In addition, from these other measurements, the system can compute the signal to noise ratio. The non-linearity of the transmitter has a different edge shape or slope for falling edges versus rising edges the non-linearity of this will show up readily in the symmetry of the cyclic loop. A measurement can represent this linearity as a single numeric value that can act as input to the machine learning.

[0058] Another aspect of the embodiments includes a combination of the measurements into the display image. The various measurements above can act as input parameters for the machine learning. One method for inputting them into the existing trained neural nets that process images is to incorporate them as bar graphs or other formats of digital encoded data into the image. This way the extracted parameters along with the actual waveform image work together to help with the classification process.

[0059] The machine learning system 56 receives as input the cyclic loop images. The main purpose of system or network 56 is to look at the cyclic loop images along with any digitally encoded extracted parameters that were placed into the images, then classify the waveform represented in the image to be either a write burst or a read burst. There may be a training phase 57 where multiple examples of read and write cyclic loop images are presented to the network to train it how to classify. After the training period, the input images are analyzed by the trained network and classified as either read or write.

[0060] The machine learning system 56 may have the following inputs. The cyclic loop XY plot images show cyclic closed-loop path overlaying all edges into the path. The extracted measurement parameters, if any, are provided inserted in the cyclic loop image, in some other form of a separate image, or as a vector of numbers, or other forms may be devised. When inserted in the image it may be of the form of simple bar graph, or multiple bar graphs, or pi- chart shaped objects, etc. A user input menu 72 would allow the user to look at the cyclic loop images for the acquired bursts and tell the machine which is read, and which is write, for example, as part of training process 57. Once the machine knows which is which it can classify them from that point on in a runtime process 58.

[0061] This would be useful for systems which do not have very much difference between read and write, or for which the key model assumptions described above are not the same. For example, there may be no interposer, and the probe may be positioned closer to mid bus where delay for read reflections may be same for write reflections, etc. The system also has a user input menu 74 that allows entry of the various system parameters such as memory load, trace impedance, interposer use and location, etc.

[0062] The machine learning system 56 outputs classified data burst signals as either reads or writes. The blocks 66 or 62 creates multiburst waveforms. In one embodiment, this may involve concatenating each detected burst into a single waveform containing only read bursts or write bursts. After the multi-burst waveforms are created, de-embedding filters 64 and 68 may be computed for each waveform. Since the system transfer functions for read versus write are different, there will be a different filter for each waveform. These filters will also move the probe test point at the interposer to a virtual probe test point at the memory or SOC. Optimally, for the DQ signal a DFE equalizer 70 may be applied. The machine learning system 56 may also provide results of the measurements 60. [0063] The system controller 76 may consist of a general-purpose processor which controls and sequences the entire system, or a processor on the test and measurement device, or distributed between them. The system controller may also be distributed across several processors, cloud computing, etc. The processors may be configured to execute code that causes the processors to provide all the processing functions, for measurements and the neural network or other types of machine learning that may be employed. Obviously, any part of this system may be implemented on other types of processors such as ASICs, GPUs, FPGAs, etc.

[0064] Fig. 9 shows examples on an oscilloscope screen of the waveforms used for making the cyclic loop image. In this view the somewhat sinusoidal looking waveform is a DQS clock signal 80. The output of the clipper is shown as a square wave 82. The ramp signal is the output of the boxcar filter at 84.

[0065] Fig. 10 shows examples of cyclic loop images. At left is a high ISI DQS write signal. In the middle is a DQS read signal where reflections are visible. At the right is an overlay of both DQS read and write. Fig. 11 shows an example of DQ random pulse levels 90 and the associated ramp sweep signal 92 with ramps that only occur during the edge transitions of the DQ signal, and the cyclic loop image 94 constructed from the DQ signal 90 and the ramp sweep signal 92. [0066] The reflection delay between probe and memory load, may be measured from a standard YT trace display as shown in Fig. 12. The trace delay is then computed from (7) as:

Delay = T / 2 (7)

[0067] Fig. 13 shows how to measure the trace delay using the cyclic loop image, where delay is represented as Q in degrees. For both cases the waveform is shown with no trace ISI loss in order to simplify the view to show the points at which to measure a phase angle, Q, in order to compute the reflection delay time. [0068] The delay time may be computed from the (8). One full path thru the loop is 360 degrees which is one cycle. One cycle is two UI or two bits for an NRZ type signal. dela ^J y = - 360 -b where Q is in degrees and delay has units of seconds. The data rate of the signal is the bitrate for an NRZ type signal.

[0069] A reflection coefficient for the short trace between probe and memory can be measured on a standard YT type of waveform display as shown in Fig. 14. The reflection coefficient is then computed as:

G = ( v2 - vl ) / vl

[0070] Once the reflection coefficient is known the impedance of the load, Z, or the characteristic impedance Z0 can be computed if one of them is known.

Z = Zo· ( 1 + G ) / ( 1 - G)

[0071] The reflection coefficient may be measured using the cyclic loop image as shown below in Fig. 15.

[0072] In this manner, the system can create and use new cyclic loop images, and optionally include measurement encoded bar graphs in the images. These images are then used in a deep learning environment to determine and classify the nature of the signals by separating them and classifying them for analysis and other uses.

[0073] Aspects of the disclosure may operate on a particularly created hardware, on firmware, digital signal processors, or on a specially programmed general purpose computer including a processor operating according to programmed instructions. The terms controller or processor as used herein are intended to include microprocessors, microcomputers, Application Specific Integrated Circuits (ASICs), and dedicated hardware controllers. One or more aspects of the disclosure may be embodied in computer-usable data and computer-executable instructions, such as in one or more program modules, executed by one or more computers (including monitoring modules), or other devices. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types when executed by a processor in a computer or other device. The computer executable instructions may be stored on a non-transitory computer readable medium such as a hard disk, optical disk, removable storage media, solid state memory, Random Access Memory (RAM), etc. As will be appreciated by one of skill in the art, the functionality of the program modules may be combined or distributed as desired in various aspects. In addition, the functionality may be embodied in whole or in part in firmware or hardware equivalents such as integrated circuits, FPGA, and the like. Particular data structures may be used to more effectively implement one or more aspects of the disclosure, and such data structures are contemplated within the scope of computer executable instructions and computer-usable data described herein.

[0074] The disclosed aspects may be implemented, in some cases, in hardware, firmware, software, or any combination thereof. The disclosed aspects may also be implemented as instructions carried by or stored on one or more or non-transitory computer-readable media, which may be read and executed by one or more processors. Such instructions may be referred to as a computer program product. Computer-readable media, as discussed herein, means any media that can be accessed by a computing device. By way of example, and not limitation, computer-readable media may comprise computer storage media and communication media. [0075] Computer storage media means any medium that can be used to store computer-readable information. By way of example, and not limitation, computer storage media may include RAM, ROM, Electrically Erasable Programmable Read-Only Memory (EEPROM), flash memory or other memory technology, Compact Disc Read Only Memory (CD-ROM), Digital Video Disc (DVD), or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, and any other volatile or nonvolatile, removable or non removable media implemented in any technology. Computer storage media excludes signals per se and transitory forms of signal transmission.

[0076] Communication media means any media that can be used for the communication of computer-readable information. By way of example, and not limitation, communication media may include coaxial cables, fiber-optic cables, air, or any other media suitable for the communication of electrical, optical, Radio Frequency (RF), infrared, acoustic or other types of signals.

[0077] Additionally, this written description makes reference to particular features. It is to be understood that the disclosure in this specification includes all possible combinations of those particular features. For example, where a particular feature is disclosed in the context of a particular aspect, that feature can also be used, to the extent possible, in the context of other aspects.

[0078] Also, when reference is made in this application to a method having two or more defined steps or operations, the defined steps or operations can be carried out in any order or simultaneously, unless the context excludes those possibilities.

EXAMPLES

[0079] Illustrative examples of the disclosed technologies are provided below. An embodiment of the technologies may include one or more, and any combination of, the examples described below. [0080] Example 1 is a system to classify signals, comprising: an input to receive incoming waveform data; a memory; and one or more processors configured to execute code to cause the one or more processors to: generate a ramp sweep signal from the incoming waveform data; locate a data burst in the incoming waveform data using a burst detector; receive a signal from the burst detector to cause the memory to store cyclic loop image data in the form of the incoming waveform data as y-axis data and the ramp sweep signal as x-axis data; and employ a machine learning system to receive the cyclic loop image data and classify the data burst.

[0081] Example 2 is the system of Example 1, further comprising a test and measurement instrument to acquire the incoming waveform data from a device under test.

[0082] Example 3 is the system of either Examples 1 or 2, wherein the code to cause the one or more processors to generate the ramp sweep signal from the incoming waveform data further comprises code to cause the one or more processors to: use a clipper to generate a square pulse signal from the incoming waveform data; and use an integrator to generate ramp signals based upon the square pulse signal and transmit the ramp signals to the burst gate.

[0083] Example 4 is the system of Example 3, wherein the integrator comprises a boxcar filter. [0084] Example 5 is the system of any of the Examples 1-4, further comprising a measurement unit to take a measurement using the cyclic loop image data.

[0085] Example 6 is the system of Example 5, wherein the measurement includes one or more of reflection delay, reflection coefficient, intersymbol interference, signal-to-noise ratio, and non linearity.

[0086] Example 7 is the system of Example 5, wherein the measurement unit sends the measurement to the machine learning system. [0087] Example 8 is the system of any of Examples 1-7, further comprising a concatenator to create a multi-burst waveform from the classified data burst from the machine learning system. [0088] Example 9 is the system of Example 8, further comprising a filter to apply to the multi burst waveform.

[0089] Example 10 is the system of any of Examples 1-9, further comprising a system controller to coordinate operations of the system.

[0090] Example 11 is a method of classifying signals, comprising: generating a ramp sweep signal from incoming waveform data; locating a data burst in the incoming waveform data; storing cyclic loop image data for the data burst in the form of the incoming waveform data as Y- axis data and the ramp sweep signal as X-axis data; and using a machine learning system to receive the cyclic loop image and classify the data burst.

[0091] Example 12 is the method of Example 11, further comprising receiving system parameters from a user.

[0092] Example 13 is the method of either of Examples 11 or 12, wherein generating the ramp sweep signal comprises: generating a square pulse signal from the incoming waveform data; and integrating the square pulse signal to produce the ramp sweep signal.

[0093] Example 14 is the method of Example 13, wherein integrating the square pulse signal is performed by a boxcar filter.

[0094] Example 15 is the method of any of the Examples 11-14, further comprising taking a measurement using the cyclic loop image data.

[0095] Example 16 is the method of Example 15, wherein the taking the measurement includes measuring one or more of reflection delay, reflection coefficient, intersymbol interference, signal -to-noise ratio, and non-linearity. [0096] Example 17 is the method of Example 15, further comprising sending the measurement to the machine learning system, wherein the machine learning system classifies the data burst using the cyclic loop image data and the measurement.

[0097] Example 18 is the method of any of the Examples 11-17, further comprising creating a multiburst waveform from classified data bursts from the machine learning system.

[0098] Example 19 is the method of any of the Examples 11-18, further comprising training the machine learning system, the training comprising: providing a set of cyclic loop images; receiving user inputs that classify each cyclic loop image; testing the machine learning system by having the machine learning system provide a classification and verifying the classification against the user input; and repeating the testing until the machine learning system correctly classifies the cyclic loop images.

[0099] Example 20 is a system to classify data signals, comprising: a ramp generator to generate a ramp sweep signal from incoming waveform data; a burst detector to locate a data burst in the incoming waveform data; a burst gate to receive a signal from the burst detector and cause a memory to store cyclic loop image data in the form of the incoming waveform data as y-axis data and the ramp sweep signal as x-axis data; and a machine learning system to receive the cyclic loop image and classify the data burst.

[0100] Example 21 is the system of Example 20, wherein the incoming waveform data is acquired from a memory device under test, and wherein the machine learning system classifies the data burst as resulting from one of a write operation or a read operation for the memory device under test.

[0101] All features disclosed in the specification, including the claims, abstract, and drawings, and all the steps in any method or process disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive. Each feature disclosed in the specification, including the claims, abstract, and drawings, can be replaced by alternative features serving the same, equivalent, or similar purpose, unless expressly stated otherwise.

[0102] Although specific embodiments have been illustrated and described for purposes of illustration, it will be understood that various modifications may be made without departing from the spirit and scope of the disclosure. Accordingly, the invention should not be limited except as by the appended claims.