Title:
SYSTEM AND METHOD FOR TIMING SYNCHRONIZATION
Document Type and Number:
WIPO Patent Application WO/2024/072686
Kind Code:
A3
Abstract:
The system and method generates a pulse or a signal that is transmitted between a central processing unit or processor and an Ethernet integrated circuit card to program a trigger generator in the IC. The pulse is effectively a 1PPS signal that is provided to the IC, which may be in the form a field programmable gate array to enable timing synchronization. The trigger in the IC may also generates an interrupt to the processor so a driver in the CPU is instructed to set the next trigger. For the trigger to be accurately controlled, the control routine is implemented in the driver existing in kernel space rather than user space. A routine or protocol periodically polls the interrupt to determine when the trigger must be reset.
Inventors:
SHERMAN MATTHEW (US)
SINHA MRITUNJAY (US)
YANG LAWRENCE (US)
SINHA MRITUNJAY (US)
YANG LAWRENCE (US)
Application Number:
PCT/US2023/033354
Publication Date:
May 16, 2024
Filing Date:
September 21, 2023
Export Citation:
Assignee:
BAE SYS INF & ELECT SYS INTEG (US)
International Classes:
H04J3/06; H04J1/16; G06F1/04
Attorney, Agent or Firm:
ASMUS, Scott, J. (US)
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