Technical Field

[0001] The present invention relates to clock synchronisation. Specifically, the present invention relates to clock synchronisation as it applies to Ultra-Wide Band (UWB) localization.

Background of Invention

[0002] Localization techniques have been used to identify the location of a device in situations where satellite navigation is inaccessible or inefficient for reasons such as signal blockage, multipath transmissions, time consumption and the like. Techniques such as Received Signal Strength Indication (RSSI), fingerprinting, Time of Flight (ToF), Angle of Arrival (AoA) and Time Difference of Arrival (TDOA) have been used in location identification.

[0003] Localization in the UWB can be challenging. Two types of localization techniques in UWB are Two Way Ranging (TWR) and Time Difference of Arrival (TDOA). TWR has an increase in error proportional to the distance between nodes and is thus not favourable in circumstances where the distance between nodes may be large. UWB nodes performing TDOA are based on wireless channel dependent synchronisation events. Localisation methods such as those discussed above are affected by the accuracy of clocks used, and in addition, suffer from higher power consumption.

[0004] It would therefore be desirable to provide a UWB localisation technique which ameliorates or at least alleviates one or more of the above problems or provides a useful alternative. [0005] A reference herein to a patent document or other matters which is given as prior art is not to be taken as an admission that that document or matter was known or that the information it contains was part of the common general knowledge as at the priority date of any of the claims. Summary of Invention

[0006] According to an aspect of the present invention, there is provided a system for synchronization between a plurality of nodes connected using differential pair carrying data signals, the system including a master node and one or more slave nodes, the master node and the one or more slave nodes performing time-difference of arrival in ultra-wide band and a control module configured to generate a clock signal for the master node, wherein the generated clock signal is multiplexed with the data signals as an output signal and to de-multiplex the output signal from the data signals received from the master node to obtain the clock signal for the one or more slave nodes for synchronising the master node and the one or more slave nodes to perform time- difference of arrival.

[0007] Advantageously, the present invention may provide a way to synchronise between nodes very accurately within, for example, a vehicle, a vessel, locomotive compartment, airplane, small buildings and the like. In the case of a vehicle, where, for example, a pair of differential wires (known as a “differential pair”) being used for communication (i.e. twisted pair or a CAN bus) is provided to each node within the vehicle, a clock signal is provided on the differential pair. The clock signal sent over a differential pair being used for communication synchronises the nodes (typically in the UWB) to allow the nodes to then perform TDOA.

[0008] In a further possible advantage, superimposing a clock signal over a differential pair which are being used for differential signalling as an output signal (such as a common mode disturbance i.e. CAN, Ethernet) avoids distorting the data on the bus or the injected clock signal. The present invention may also allow reduction in the amount of copper conductors used between nodes thereby reducing overall cost and weight.

[0009] It will be appreciated that in some embodiments of the present invention, the master node and the control module can be combined into a single module, while in some other embodiments, the steps of generating and multiplexing the clock signal may be performed from within the master node, while the step of de-multiplexing the output signal may be performed from within the one or more slave nodes. [0010] Preferably, the control module may initially be configured to assign one of the plurality of nodes as the master node and the remaining of the plurality of nodes as the one or more slave nodes.

[0011] The control module associated with or within the master node may assign roles, such as slave nodes and assign “positions” of the slave nodes.

[0012] In a preferred embodiment, a master node is assigned only at initialisation while the remaining plurality of nodes can be assigned as slave nodes at any point in time. In some embodiments, the one or more slave nodes may be assigned positions by the master node. [0013] Preferably, the control module is configured to generate the clock signal using a signal generation module. In a preferred embodiment, the control module may be in the master node, while in other embodiments, the control module may be a module that is physically separate from, but communicatively connected to, the master node. In an embodiment of the invention, the signal generation module may reside within the control module.

[0014] Preferably, the control module may be configured to associate the signal generation module with the master node. Advantageously, by such association, there is no limitation as to the physical location of the control module, the signal generation module and the master node with respect to each other. [0015] Preferably, the control module may be configured to de-multiplex the output signal using a signal extraction module. In an embodiment of the invention, the signal extraction module may reside within the control module.

[0016] Preferably, the control module may be configured to associate the signal extraction module with the one or more slave nodes. Advantageously, by such an association, there is no limitation on the physical location of the control module, the signal extraction module and the slave node(s) with respect to each other.

[0017] Preferably, each of the master node and the one or more slave nodes has a data transceiver to send and receive the data signals carried by the differential pair. [0018] Preferably, the output signal includes a common mode signal. However, it will be appreciated that any signal which is injected as common mode, that is able to be rejected by a CAN transceiver is able to be modulated and demodulated, and the demodulation circuit may be modified accordingly. Advantageously, multiplexing the clock signal with the data signals as a common mode signal would have less noise than other arrangements.

[0019] Preferably, the master node and the one or more slave nodes are spatially separated.

[0020] Preferably, the signal generation module is configured to generate a synchronisation signal to be multiplexed along with the generated clock signal and the data signals for synchronising the master node and the one or more slave nodes.

Brief Description of Drawings

[0021] Figure 1A is a system diagram illustrating a vehicle utilising the system for synchronisation between the plurality of nodes connected via differential pair as a “daisy-chain” or a continuous string of nodes according to a preferred embodiment of the present invention;

[0022] Figure 1 B is a system diagram illustrating an alternative embodiment of a vehicle utilising the system for synchronisation between the plurality of nodes connected via differential pair in an alternate topography;

[0023] Figure 2A is a schematic diagram illustrating the system for synchronisation between a plurality of nodes connected using differential pair carrying data signals according to a preferred embodiment of the present invention;

[0024] Figure 2B is a schematic diagram illustrating the system for synchronisation between a plurality of nodes connected using differential pair carrying data signals according to an alternative embodiment of the present invention;

[0025] Figure 3A is a detailed schematic of the master nodes and one or more slave nodes according to a preferred embodiment of the present invention; [0026] Figure 3B is a detailed schematic of an alternative embodiment of the master node and one or more slave nodes according to an alternative embodiment of the present invention;

[0027] Figure 4A is a schematic diagram of the control module according to a preferred embodiment of the present invention;

[0028] Figure 4B is a schematic diagram of the control module according to an alternative embodiment of the present invention;

[0029] Figure 5A is a schematic diagram of the signal extraction module according to a preferred embodiment of the present invention; [0030] Figure 5B is a schematic diagram of the signal extraction module according to an alternative embodiment of the present invention; and

[0031] Figure 6 is a chart illustrating a clock signal which has a violation superimposed on it, the properties of which are utilised in an embodiment of the present invention. Detailed Description

[0032] The present invention may be utilised by systems such as a vehicle having interconnected nodes by way of a differential pair (e.g. CAN, Ethernet or the like), and it will be convenient to describe the invention in relation to that exemplary, but non limiting, application. It will be appreciated that the present invention is not limited to that application and may for example, be applied in ships, locomotive compartments, airplanes, small buildings and the like.

[0033] Figure 1A is a system diagram illustrating a vehicle 100A embodying the system according to a preferred embodiment of the present invention.

[0034] The vehicle 100A includes a master node 110 and one or more slave nodes 120A to 120F all of which are connected as a “daisy-chain” or a continuous string of nodes using a differential pair 140 such as a CAN bus that carries data signals. In a preferred embodiment, the master node 110 also acts as a control module to generate a clock signal and multiplex the clock signal.

[0035] In operation, the system residing on the vehicle 100A provides synchronisation between a plurality of nodes which in this case includes a master node 110 and one or more slave nodes 120A to 120F which are connected using differential pair 140 which carries data signals. The master node 110 and one or more slave nodes 120A to 120F perform Time Difference of Arrival (TDOA) in the Ultra-Wideband (UWB). The master node 110 is configured to generate a clock signal for the master node 1 10 wherein the generated clock signal is multiplexed with data signals carried by the differential pair 140 as an output signal (e.g. a common mode signal). The system residing on vehicle 100A is configured to de-multiplex the output signal from the data signals received from the master node 110 to obtain the clock signal for the one or more slave nodes 120A to 120F to synchronize the master node 110 and the one or more slave nodes 120A to 120F to subsequently perform TDOA between the plurality of nodes. It will be appreciated that the master node 110 also acts as a control module to generate the clock signal for the master node 110 and to multiplex the clock signal with the data signals as an output signal (e.g. a common mode signal). It will further be appreciated that the one or mode slave nodes 120A to 120F are configured to perform de-multiplexing of the data signals from the output signal to obtain the clock signal. It will also be appreciated that common mode signal is an exemplary type of output signal, and that the skilled addressee would understand that other types of signals are also possible without departing from the scope of the invention.

[0036] Advantageously, this may be a way to synchronise between nodes very accurately within the vehicle 100A, 100B where the differential pair may, for example, be a twisted pair which is provided to each node within the vehicle and a clock is provided on the twisted pair or differential pair or CAN bus for that purpose.

[0037] It will be appreciated that other suitable arrangements of connecting the master node and the one or more slave nodes are possible. For example, as shown in Figure 1 B, there is provided a system diagram illustrating a vehicle 100B embodying the system according to an alternative embodiment of the present invention (utilising a different network topology - for example a star network, or a non-continuous string of nodes) as would be appreciated by a skilled addressee.

[0038] The vehicle 100B includes a control module 130B, a master node 110 and one or more slave nodes 120A to 120D connected using a differential pair 140 as a star network. The control module 130B may be a separate entity outside of the master node 110 and the master node 110 and the control module 130B may be separately connected to each of the slave nodes 120A to 120D using a differential pair 140 such as a CAN bus that carries data signals. The control module 130B can assign positions to the one or more slave nodes 120A to 120D.

[0039] In operation, the system residing on the vehicle 100B provides synchronisation between a plurality of nodes which in this case includes a master node 110 and one or more slave nodes 120A to 120D which are connected using differential pair 140 carrying data signals. The master node 110 and one or more slave nodes 120A to 120D perform Time Difference of Arrival (TDOA) in the Ultra-Wideband (UWB). The control module 130B is configured to generate a clock signal for the master node 110 wherein the generated clock signal is multiplexed with the data signals as an output signal (e.g. a common mode signal). The control module 130B is further configured to de-multiplex the output signal from the data signals received from the master node 110 to obtain the clock signal for the one or more slave nodes 120A to 120D to synchronize the master node 110 and the one or more slave nodes 120A to 120D to then perform TDOA. It will be appreciated that the one or mode slave nodes 120A to 120D may be configured to perform the de-multiplexing of the data signals from the output signal to obtain the clock signal based on commands received from the control module 130B. It will also be appreciated that common mode signal is an exemplary type of output signal, and that the skilled addressee would understand that other types of signals are also possible without departing from the scope of the invention.

[0040] Figure 2A is a schematic diagram 200A illustrating the association between the master node 110 and slave nodes 120A, 120B interconnected via differential pair 140. A control module 130A is located within the master node 110 in a preferred embodiment of the present invention. A signal extraction module 220A is located within each slave node 120A, 120B. However, it will be appreciated that this arrangement would apply equally to the other slave nodes 120C through 120F and the like.

[0041] In operation, the control module 130A generates a clock signal for the master node 110 and multiplexes the generated clock signal onto the differential pair 140 as an output signal. The signal extraction module 220A within the slave node 120A then receives the output signal from the differential pair 140 and de-multiplexes the clock signal from the output signal received from the differential pair 140. Similarly, the slave node 120B receives the output signal from the differential pair 140 and de-multiplexes the clock signal from the output signal received from the differential pair 140. The clock signal generated at the master node 110 and received at the slave node(s) 120A (and other slave nodes 120B to 120F) via the differential pair 140 causes the master node 110 and the slave nodes 120A to 120F to be synchronised such that TDOA can then be performed.

[0042] It will be appreciated that other suitable associations between the master node and the one or more slave nodes may be possible. For example, as shown in Figure 2B, there is provided a schematic diagram 200B according to an alternative embodiment illustrating the association between the control module 130B, a signal generation module 210 (such as “modulator” or the like), a signal extraction module 220B (such as “demodulator” or the like), the master node 110 and a slave node 120A. The signal generation module 210 and the control module 130 are located outside of the master node 110 in an alternative embodiment of the present invention. The signal generation module 210 and the signal extraction module 220B are communicatively connected to the control module 130 via the differential pair 140. It will be appreciated that other modes of connection may be possible between the control module 130, the signal generation module 210 and the signal extraction module 220B without departing from the scope of the invention. In this embodiment, the signal extraction module 220B is located outside of the slave node 120A. However, it will be appreciated that this arrangement would apply equally to the other slave nodes 120B through 120F and the like. It will further be appreciated that the signal generation module 210 and the control module 130 can be one and the same module. In some embodiments, the signal extraction module 220B may be within the one or more slave nodes 120A to 120D. [0043] In operation, the control module 130B receives from the signal generation module 210 a clock signal which it then provides to the master node 110 via the differential pair 140. Master node 110, in response to receiving the clock signal from the control module 130B by way of signal generation module 210, multiplexes the clock signal as an output signal (e.g. a common mode signal) and sends the multiplexed signal via the differential pair 140 to slave node 120A. The slave node 120A via the control module 130B and signal extraction mode 220B demultiplexes the output signal from the data signals received from the master node 110 to obtain a clock signal for the slave node 120A based on TOA thereby allowing synchronisation of the master node 110 with the slave node(s) 120A to then perform TDOA.

[0044] Advantageously, power consumption of nodes performing time difference of arrival (TDOA) localisation is reduced where the nodes are connected only via a differential pair such as CAN. It will be appreciated that the control module 130B can include within itself the signal generation module 210 or can be configured to perform the function of the signal generation module 210.

[0045] Figure 3A is a detailed schematic diagram 300A according to a preferred embodiment of the present invention illustrating a master node 110 and a slave node 120A provided along differential pair 140. The master node 110 includes a microcontroller 310A which is in communication with a master node data transceiver 320A (e.g. CAN Transceiver), a master node Ultra-Wideband transceiver 330A and a control module 130A. The control module 130A generates a clock signal 340A that is then multiplexed with the data signals generated by the data transceiver 320A as an output signal 345A.

[0046] The slave node 120A includes a microcontroller 315A, a data transceiver 325A (e.g. CAN transceiver), a slave node Ultra-Wideband transceiver 335A, a High

Pass filter 370A and a signal extraction module 220A which demultiplexes the output signal 345A received via the differential pair 140. It will be appreciated that a Band Pass filter may be used in place of the High Pass filter 370A with suitable modifications to the system architecture as would be understood by persons skilled in the art. [0047] It will be appreciated that other suitable arrangements of the master node and the one or more slave nodes may be possible. For example, as shown in Figure 3B, there is provided, a detailed schematic diagram 300B according to an alternative embodiment of the present invention illustrating a master node 110, a slave node 120A and a control module 130B provided along differential pair 140. The master node 110 may include a microcontroller 310B, which is in communication with a master node data transceiver 320B (e.g. CAN Transceiver), a master node Ultra-Wideband transceiver 330B and a control module 130B. The control module 130B generates a clock signal to be multiplexed via the differential pair 140. The control module 130B further generates a synchronisation signal to be multiplexed with the clock signal (SYNC + CLK 340B) via the differential pair 140.

[0048] The slave node 120A includes a microcontroller 315B, a data transceiver 325B (e.g. CAN transceiver), a slave node Ultra-Wideband transceiver 335B, a High Pass filter 370B and a signal extraction module 220B which receives the multiplexed output signal (e.g. a common mode signal) 345B via the differential pair 140. It will be appreciated that a Band Pass filter may be used in place of the High Pass filter 370B with suitable modifications to the system architecture as would be understood by persons skilled in the art.

[0049] In operation, the control module 130B residing within the master node 110 generates a clock signal for the master node 110. The control module 130B further generates a synchronisation signal and multiplexes the clock signal with the synchronisation signal (SYNC + CLK 340B). The SYNC + CLK 340B signal is multiplexed with data signals output from the data transceiver 320B as an output signal (e.g. a common mode signal) to be sent via the differential pair to slave node 120A. The slave node 120A via the control module 130 and signal extraction module 220B demultiplexes the output signal 345B from the data signals received from the master node 110 to obtain a clock signal for the slave node 120A to synchronize the master node 110 with the slave node(s) 120A to then perform TDOA. Advantageously, power consumption of nodes performing time difference of arrival (TDOA) localisation may be reduced where the nodes are connected only via a differential pair such as CAN. It will be appreciated that the control module can include within itself a signal generation module 210 or can be configured to perform the function of signal generation module 210 to generate the clock signal 340B.

[0050] It will be appreciated that in an embodiment of the invention, the control module 130B (not shown) may reside outside of the master node 110 and generate a clock signal 340B which it then provides to the master node 110 via the differential pair 140.

[0051] Figure 4A is a schematic diagram 400A illustrating a preferred embodiment of a control module 130A which may be utilised with the present invention. The control module 130A which resides within the master node 110 includes a number of components namely, a local oscillator 405A which feeds into a buffer 410A. Output from the buffer 410A is a clock signal which is received by an injector 420A. A synchronisation trigger signal is generated by the Microprocessor 425A and sent to a UWB Transceiver 330A and also to the data transceiver 320A along with data signal (e.g. CAN data). It will be appreciated that a microcontroller may be used in place of the microprocessor 425A with suitable modifications to the system architecture as would be understood by persons skilled in the art. Output of the data transceiver 320A is the data signal and synchronisation trigger signal (e.g. CAN + SYNC) which is fed to the output of the injector 420A to multiplex the clock signal with the data and synchronisation signals as an output signal onto the differential pair 140.

[0052] It will be appreciated that the control module may have other suitable configurations. For example, as shown in Figure 4B, there is provided a schematic diagram 400B illustrating an alternative embodiment of a control module 130B which may be utilised with the present invention. The control module 130B includes a number of components namely, a local oscillator 405B which feeds into a buffer 410B and the master node Ultra-Wideband (UWB) transceiver 330B. Transistor 415B receives the output from the buffer 410B as well as a synchronisation trigger from the Microprocessor 425B to provide a CLK + SYNC signal to an injector component 420B. Synchronisation signal is also sent from the Microprocessor 425B to the master node UWB Transceiver 330B. Data signal is sent from the Microprocessor 425B to the data transceiver (e.g. CAN Transceiver) 320B. The CLK + SYNC signal is multiplexed with data signals from the data transceiver 320B as an output signal (e.g. a common mode signal) 340B to be sent via the differential pair 140.

[0053] Figure 5A is a schematic diagram 500A illustrating a preferred embodiment of a signal extraction module 220A including a phase locked loop 505A which may be a pre-existing chip (for example an ADF4001 and/or LMX2595) and a local oscillator 405A’. The phase locked loop component 505A receives as input the data signals and clock signal 340A multiplexed as an output signal (e.g. a common mode signal) 345A vie a High pass Filter 370A as well as input from the local oscillator 405A’. Phase locked loop PLL 505A demultiplexes the clock signal from the multiplexed output signal 345A and sends the clock signal to the slave node Ultra-Wideband transceiver 335A. It will be appreciated that a Band Pass filter may be used in place of the High Pass filter 370A with suitable modifications to the system architecture as would be understood by persons skilled in the art.

[0054] It will be appreciated that the signal extraction module may have other suitable configurations. For example, as shown in Figure 5B, there is provided a schematic diagram 500B illustrating a signal extraction module 220B including a phase locked loop 505B which may be a pre-existing chip (for example an ADF4001 and/or LMX2595) and a local oscillator 405B’. A High Pass filter 370B receives a multiplexed output signal (e.g. a common mode signal) 345B (Data + CLK + SYNC) and sends the CLK + SYNC to the phase locked loop component 505B. It will be appreciated that a Band Pass filter may be used in place of the High Pass filter 370B with suitable modifications to the system architecture as would be understood by persons skilled in the art. The phase locked loop component 505B also receives an input from the local oscillator 405B’. CLK + SYNC is also provided to a comparator 510 which compares the output of the phase locked loop component 505B with the input CLK + SYNC. The clock from the phase locked loop component 505B and the SYNC from the comparator component 510 are then provided to the slave node Ultra-Wideband transceiver 335B. It will be appreciated that the sync trigger could be sent as a precisely timed frame (for example a CAN frame on a CAN bus system) to the nodes within the system.

[0055] Figure 6 is a chart illustrating a clock signal which has a violation superimposed on it, the properties of which are utilised in an embodiment of the present invention where it can be seen that the violation 620 is where the CLK + SYNC has not synced with the actual clock signal 610. While a violation of the clock signal 620 is not essential to synchronise the nodes in the system, it is advantageous since its implementation means the synchronisation technique is independent of the communication protocol. The recovered "CLK" signal will largely follow the sinusoidal trace 610 in the waveform of Figure 6 and the "SYNC" signal will be “high” for the clock pulse that is missing, an UWB transceiver will read the "SYNC" trigger at the rising edge of the clock filled in by the PLL block 505B of Figure 5. It will be appreciated that this output waveform is only an exemplary output of the system as claimed in this invention. [0056] While the invention has been described in conjunction with a limited number of embodiments, it will be appreciated by those skilled in the art that many alternative, modifications and variations in light of the foregoing description are possible. Accordingly, the present invention is intended to embrace all such alternative, modifications and variations as may fall within the spirit and scope of the invention as disclosed.