System for therapeutic treatments with electromagnetic waves TEXT OF THE DESCRIPTION Technical field The present disclosure relates to a system for therapeutic treatments with electromagnetic waves. Background European patent application No. EP 3160582 A1 and International patent application No. WO 2012/172504 A1, which are incorporated herein by reference, describe systems that are able to subject various types of biological tissues and/or organs, usually of a mammal, typically a human, to an electromagnetic stimulus that drives into resonance the cell structures of the aforesaid tissues and organs. For example, as also described in European patent application No. EP 3160582 A1, it appears that different tissues and organs respond, in vivo, to frequencies of weak electromagnetic fields that have the property of sending specific cell structures of those tissues or organs into resonance. The characteristic frequencies are, for example, those of the electroencephalogram, which have a frequency range that falls between 0.1 and 42 Hz. Likewise, also other organs, tissues, and cell structures have typical frequency ranges, which have the property of responding to "resonance stimuli", if exposed to electromagnetic fields pulsating at these frequencies. For example, typically the electromagnetic field may be in a range between 40 nT and 100 ^T. Moreover, in addition to resonance phenomena on organs, apparatus and tissues, effects on the cells that constitute them and in particular on the cell membrane may be observed. For example, it has been suggested that the electromagnetic fields applied to the cells are able to orient the water molecules, widely present in them, in resonance to the frequency of the electromagnetic field generated by the antennas. This orientation causes a local modification of the electrochemical gradient which in turn modifies the Van Der Waals forces that regulate the plasticity of the membrane lipids, as well as the ionic pumps (Sodium, Calcium, Potassium, etc.). Therefore, by stimulating the cellular systems at appropriate frequencies, it is possible to improve the functioning of the whole cell, including the respiration activities (exchange of oxygen), the production of energy (mitochondria), the protein synthesis and even the DNA replication. Figure 1 shows an example of a system for therapeutic treatments. In the example considered, the system comprises an apparatus 20 that generates at least one drive signal for at least one antenna or diffuser 30, which emits a corresponding electromagnetic treatment signal. In particular, in the example considered, the apparatus 20 comprises a control circuit 22 configured to generate a signal S that is sent through a power amplifier 24 to at least one antenna 30. For instance, in the example considered, three antennas 30a, 30b, and 30c are illustrated. Typically, the number of the antennas 30 is between one and twenty. As mentioned previously, typically the electromagnetic field emitted by an antenna 30 is between 40 nT and 100 ^T. In general, the antennas 30 are built for specific applications or treatments and may be in different forms, such as for example in the form of pads or mats, which may be plane or modeled anatomically to reproduce the area of application, or hand-pieces, thereby permitting a global or a local application of the electromagnetic field. Typically, the above diffusers/antennas are obtained via plane solenoids that are applied on a support. For instance, the diffusers illustrated in Figures 6 and 7 of document WO 2012/172504 A1 may be used for this purpose. A possible process for producing such antennas 30 is disclosed in European patent application No. EP 3115999 A1. Specifically, in the example illustrated in Figure 1, the control circuit 22 generates only a single drive signal S, which is sent by means of an amplifier 24 to one or more antennas 30; i.e., the antennas 30 are driven with the same signal S. In general, also a plurality of amplifiers 24 may be provided, for example one amplifier could be provided for each antenna 30, and each amplifier 24 could be set with a different amplification coefficient. Instead, Figure 2 shows an example, in which the control circuit 22 generates a plurality of driving signals S. For instance, in the example considered, the control circuit 22 generates three drive signals S ₁ , S ₂ and S ₃ that are sent through respective amplifiers 24a, 24b, and 24c to three diffusers 30a, 30b, 30c; i.e., each antenna 30 is driven by a respective driving signal S and via a respective amplifier 24. In general, the arrangements illustrated in Figures 1 and 2 may also be combined in such a way that a plurality of antennas 30 is driven via at least one drive signal S, where at least one amplifier 24 is provided for each drive signal S and where each amplifier 24 can have a fixed or configurable amplification coefficient. For instance, in this way, a first drive signal S ₁ may be used for a stimulation with systemic effect. For this purpose, an antenna 30 may be used, which is designed to emit electromagnetic radiation on a particular system of the person treated, such as for example the endocrine system, the immune system, the lymphatic system, or the muscular system. Instead, a second drive signal S ₂ may be used for a stimulation with local effect. For this purpose, the first signal S ₁ may comprise the characteristic frequencies of the system to be treated, whereas the second signal S ₂ may comprise the characteristic frequencies of the local area to be treated, for example of the tissue or organ. In Figures 1 and 2 is moreover shown a block 26, which represents a power supply circuit, such as for example a DC/DC or AC/DC electronic converter and/or a battery. In general, this power supply circuit 26 may be incorporated in the apparatus 20 (see Figure 2) or be provided at least in part externally (see Figure 1). The apparatus 20 may comprise a user interface 50, which includes, for example, a plurality of keys and/or state indicators, a touch screen, etc. The system may also comprise an external processing unit 10, such as for example a PC, which is asrranged to communicate with the apparatus 20, for instance for configuring the apparatus 20 and/or for downloading a treatment protocol from the apparatus 20. Generally, any suitable communication interface may be used for exchanging data between the control circuit 22 and the processing circuit 10. For instance, for this purpose the apparatus 20 may comprises a wired or wireless communication interface, or a reader device for reading and/or writing a portable memory, such as a memory card. According to document WO 2012/172504 A1, in order to determine a stimulus that is positive for tissue repair, it is necessary to obtain simultaneously resonance effects from the different organs/tissues involved. To be able to create simultaneously such well-defined frequencies only within certain ranges, document WO 2012/172504 A1 proposes an apparatus that generates an electromagnetic wave with specific contributions in frequency that is constituted by a cascade of base pulses I generated at a certain frequency. Figure 3 illustrates possible waveforms of such a base pulse I. For example, the base pulse I can be a sawtooth or triangular waveform (Figure 3a), a square waveform (Figure 3b), or a sinusoidal waveform (Figure 3c). Generally, the base pulse I may also have other waveforms. For example, Figure 3d shows a base pulse I comprising a series of three curved profiles in such a way that the waveform is increasing and comprises two cusps 2 and 4. According to document WO 2012/172504 A1, the base pulse I may have a frequency f _imp (f _imp = 1/T _imp ) in a range between 100 Hz and 1 kHz, preferably between 100 and 400 Hz, even more preferably between 150 and 250 Hz. For example, preferably the base pulse I has a frequency f _imp of 190 Hz (in particular 189.75 Hz), 213 Hz (in particular 212.76 Hz) or 231 Hz (in particular 231.48 Hz). As shown in Figures 3a, 3b and 3c, a pulse-width modulation (PWM) may optionally be applied to the base pulse I with a switching period T _imp . Consequently, the pulse is activated for a duration T _{imp_on} and the pulse is deactivated for a duration T _{imp_off} (with T _{imp_off} = T _imp - T _{imp_on} ), where the durations T _{imp_on} and T _{imp_off} can be varied in the interval ]0; T _imp [. According to document WO 2012/172504 A1, a given number n _imp of these base pulses I are grouped together to generate a packet P, i.e., the base pulses I within a packet P with a duration T _pac (T _pac = 1/f _pac ) are activated for a duration T _{pac_on} (corresponding to a multiple of the duration T _imp ) and deactivated for a remaining duration T _{pac_off} (T _{pac_off} = T _pac - T _{pac_on} ). For example, Figure 4 shows an example of a packet P comprising four base pulses I. The duration of the packet T _pac may be, e.g., between 5 ms and 2 s, preferably between 20 ms and 1 s, even more preferably between 25 ms and 500 ms. According to document WO 2012/172504 A1, a given number n _pac of these packets P are grouped to generate a train of packets Tr, i.e., the packets P within a train Tr with a duration T _tr (T _tr = 1/f _tr ) are activated for a duration T _{tr_on} (corresponding to a multiple of the duration T _pac ) and deactivated for a remaining duration T _{tr_off} (T _{tr_off} = T _tr - T _{tr_on} ). For example, Figure 5 shows an embodiment of a train Tr comprising four packets P. The duration of the train T _tr may be, e.g., between 25 ms and 10 s, preferably between 100 ms and 5 s, even more preferably between 1 and 5 s. Thus, a series of identical packets P are generated by the apparatus of document WO 2012/172504 A1, wherein each packet P comprises a series of base pulses I. Specifically, in the case where the base pulses I were always activated (i.e., T _{pac_off} = 0 and T _{tr_off} = 0), the spectrum of the signal would contain only the spectrum of the base pulse I. For example, in the case of a base pulse I with sinusoidal waveform at 212.76 Hz, the spectrum would contain a single peak at 212.76 Hz. However, due to the fact that the periodic signal is truncated remaining defined only within a certain interval of definition, the resulting spectrum is broadened in the frequency domain by a value equal to the inverse of the interval of definition of the signal itself. Consequently, the final signal also comprises the characteristics in frequency of the packets P and of the trains T, i.e., the harmonics for the frequencies f _pac and f _tr . Substantially, in this way it is possible to define via the frequency f _tr a minimum frequency and via the frequency f _pac a maximum frequency. Consequently, the apparatus 20 stimulates the cells not via the fundamental harmonics of the base pulse I but via the secondary harmonics resulting in the interval between f _tr and f _pac . For example, document WO 2012/172504 A1 discloses that the apparatus may comprise the following treatment programs, which can be present also individually or in groups for carrying out a specific therapeutic treatment: 1) program 1: saw-tooth base pulse with frequency f _imp = 212.76 Hz (see Figure 1a), where the duration of the base pulse is T _imp = 4.7 ms, the number of base pulses in a pulse packet is 44, the pause between the packets is T _{pac_off} = 140 ms, the number of pulse packets in a pulse train is 4, and the pause between the trains is T _{tr_off} = 1450 ms; 2) program 2: saw-tooth base pulse with frequency f _imp = 231.48 Hz, where the duration of the base pulse is T _imp = 4.32 ms, the number of base pulses in a pulse packet is 34, the pause between the packets is T _{pac_off} = 105 ms, the number of pulse packets in a pulse train is 4, and the pause between the trains is T _{tr_off} = 1100 ms; 3) program 3: saw-tooth base pulse with frequency f _imp = 212.76 Hz, where the duration of the base pulse is T _imp = 4.7 ms, the number of base pulses in a pulse packet is 20, the pause between the packets is T _{pac_off} = 55 ms, the number of pulse packets in a pulse train is 4, and the pause between the trains is T _{tr_off} = 600 ms; 4) program 4: saw-tooth base pulse with frequency f _imp = 231.48 Hz, where the duration of the base pulse is T _imp = 4.32 ms, the number of base pulses in a pulse packet is 18, the pause between the packets is T _{pac_off} = 37 ms, the number of pulse packets in a pulse train is 4, and the pause between the trains is T _{tr_off} = 480 ms; 5) program 5: saw-tooth base pulse with frequency f _imp = 231.48 Hz, where the duration of the base pulse is T _imp = 4.32 ms, the number of base pulses in a pulse packet is 16, the pause between the packets is T _{pac_off} = 24 ms, the number of pulse packets in a pulse train is 4, and the pause between the trains is T _{tr_off} = 380 ms; 6) program 6: saw-tooth base pulse with frequency f _imp = 231.48 Hz, where the duration of the base pulse is T _imp = 4.32 ms, the number of base pulses in a pulse packet is 14, the pause between the packets is T _{pac_off} = 16 ms, the number of pulse packets in a pulse train is 4, and the pause between the trains is T _{tr_off} = 350 ms; 7) program 7: saw-tooth base pulse with frequency f _imp = 212.76 Hz, where the duration of the base pulse is T _imp = 4.7 ms, the number of base pulses in a pulse packet is 12, the pause between the packets is T _{pac_off} = 6.6 ms, the number of pulse packets in a pulse train is 4, and the pause between the trains is T _{tr_off} = 220 ms; 8) program 8: saw-tooth base pulse with frequency f _imp = 231.48 Hz, where the duration of the base pulse is T _imp = 4.32 ms, the number of base pulses in a pulse packet is 10, the pause between the packets is T _{pac_off} = 2.55 ms, the number of pulse packets in a pulse train is 4, and the pause between the trains is T _{tr_off} = 176 ms; and 9) program 9: base pulse with cusps with frequency f _imp = 189.75 Hz (see Figure 1d), where the duration of the base pulse is T _imp = 5.27 ms, the number of base pulses in a pulse packet is 5, the pause between the packets is T _{pac_off} = 36 ms, the number of pulse packets in a pulse train is 20, and the pause between the trains is T _{tr_off} = 3000 ms. For example, the timing in [ms] of the above programs may be summarized according to the following table: For example, document WO 2012/172504 A1 discloses that the duration of the treatment for the above programs may be 480 s. Document WO 2012/172504 A1 also discloses that this process of construction of the signal can be extended to further levels beyond the trains (i.e., constructing "sets of trains" and so forth, with a construction at progressively higher levels) in the case where it were desired to obtain a further capacity of regulation of the frequency contents within specific and pre-determined ranges. For example, Figure 6 shows an example in which three trains Tr are grouped to form a set of trains. Figure 6 shows also that the polarity of the set of trains can be alternated, i.e., reversed for each successive set of trains. For example, document WO 2012/172504 A1 discloses that the polarity of the programs 1 to 8 may be reversed every 120 s, whilst the polarity of the program 9 may be reversed every 180 s. The frequency content of these pulses, packets, and trains is hence equivalent to obtaining the resonance frequencies, and those alone, that characterize the typical range of the various organs/tissues. Moreover, this structure of the signal enables not only the desired frequencies to be obtained and only those, but also enables modification thereof on one and the same apparatus in a simple and deterministic way, adjusting the typical parameters of the components of the signal. Generally, the base pulses I may also contain some spikes, which guarantee that in addition to the main frequency there is an adequate content of additional harmonics. For example, Figure 3e shows an embodiment of a base pulse I having a sawtooth shape that comprises a spike S. For example, document WO 2012/172504 A1 discloses that the above- mentioned programs may stimulate the parts of the body and/or generate the effects in a human body as listed below: 1) program 1: central nervous system (CNS), limiting its function as far as creating sub- hypnotic states; ansiolytic, sedative, hypno-inducing effect; 2) program 2: paranasal sinuses and cranial sinuses, bronchia and respiratory tree, generalized organic stimulus; improvement of pulmonary ventilation; 3) program 3: CNS and peripheral nervous system, stimulation, and stimulating and repairing effect; 4) program 4: neurovegetative system and correlated functions; 5) program 5: system of metabolization of endogenous and exogenous substances, liver, lungs, stomach; anti-inflammatory and disintoxicating effect in support of pharmacological therapies in progress and release of states of homotoxicological deposit; 6) program 6: artero-venous and lymphatic circulatory system; 7) program 7: synovial membranes, articular capsules, tendons, cartilage, and mediators involved in flogosis; anti-inflammatory and antalgic effect; 8) program 8: musculoskeletal apparatus and mediators involved in generation of pain, including the production of substance P; antalgic effect; 9) program 9: psychological system, neurological system, endocrine system, immunitary stimulation; regulating and cell-regenerating effect. For example, document WO 2012/172504 A1 discloses that, for treating a diabetic foot, the apparatus 20 may use a sequence that comprises in order program 9, program 6, and program 8; namely, for the indicated duration of a program of 480 s, the duration of the entire treatment would be 1440 s. Object and summary Recent experiments conducted by the present applicant have demonstrated the effectiveness of the higher frequency programs 6 to 9. However, the lower frequency programs 1 to 4, while showing a positive result, seem to have a lower efficiency than expected. For example, when using programs 1 or 3 of the apparatus of document WO 2012/172504 A1 for the treatment of the central and/or peripheral nervous system, e.g. for treating chronic neuroinflammation and/or neurodegenerative diseases such as Alzheimer's disease, multiple sclerosis or Parkinson's disease, only minor improvements could be shown. Considering the foregoing, it is therefore an object of various embodiments to provide solutions which improve the treatment efficiency of the apparatus of document WO 2012/172504 A1. According to one or more embodiments, the above object is achieved by a system for therapeutic treatments with electromagnetic waves having the distinctive elements set forth specifically in the ensuing claims. The claims form an integral part of the technical teaching of the description provided herein. As described in the foregoing, various embodiments of the present disclosure relate to a system for therapeutic treatments with electromagnetic waves, comprising an antenna and an apparatus configured to generate a supply current for the antenna in order to generate the electromagnetic wave. Accordingly, various embodiments relate to a system for therapeutic treatments with electromagnetic waves. The system comprises an antenna 30 and an apparatus 20a configured to generate a supply current i _out for the antenna 30 in order to generate the electromagnetic waves. In various embodiments, the apparatus comprises a digital processing circuit configured to generate a first PWM signal having a given duty cycle, wherein the first PWM signal is set, for each switching cycle, to high for a switch-on period and to low for a switch-off period, a switching stage configured to generate an amplified PWM signal by amplifying the first PWM signal, and an analog low-pass or band-pass filter configured to generate the supply current by filtering the amplified PWM signal; Specifically, in various embodiments, the digital processing circuit is configured to generate a sequence of first digital values of a periodic base pulse having a given frequency. Moreover, in various embodiments, the digital processing circuit is configured to generate an enable signal with a particular timing. For example, for this purpose, the digital processing circuit is configured to generate a second PWM signal, wherein the second PWM signal is set, for each switching cycle, to a respective first logic level for a packet switch-on period and to a respective second logic level for a packet switch-off period, and a third PWM signal, wherein the third PWM signal is set, for each switching cycle, to a respective first logic level for a train switch-on period and to a respective second logic level for a train switch-off period. In this case, the digital processing circuit is configured to set to the enable signal to a respective first logic level when the second PWM signal has the respective first logic level and the third PWM signal has the respective first logic level, and to a respective second logic level when the second PWM signal has the respective second logic level or the third PWM signal has the respective second logic level. In various embodiments, the digital processing circuit may then generate a second digital value, wherein the second digital value is set to the first digital value when the enable signal has the respective first logic level and to zero when the enable signal has the respective second logic level. Specifically, in the embodiment considered, this second digital value represents a reference value for the supply current i _out for the antenna 30. Accordingly an analog-digital converter could be used to supply the antenna as a function of the second digital value. Conversely, as mentioned before, in various embodiments, the digital processing circuit is configured to generate the first PWM signal, which is then amplified by the switching stage and filtered by the analog low-pass or band-pass filter. Accordingly, in various embodiments, the digital processing circuit is configured to generate the first PWM signal as a function of the second digital value. Specifically, in various embodiments, the apparatus comprises also a current sensor configured to provide a digital sample indicative of the amplitude of the supply current, and the digital processing circuit is configured to generate the first PWM signal as a function of a third digital value indicative of the given duty cycle, and vary this third digital value via a discrete proportional-derivative regulation configured to regulate the difference between the second digital value and the digital sample to zero. For example, in various embodiments, the digital processing circuit is implemented with an FPGA or an ASIC comprising a digital signal generator configured to generate the sequence of first digital values, a first digital PWM generator circuit configured to generate the first PWM signal as a function of the third digital value indicative of the given duty cycle, a second digital PWM generator circuit configured to generate the second PWM signal, a third digital PWM generator circuit configured to generate the third PWM signal, a first combinational logic circuit configured to generate the enable signal as a function of the second PWM signal and the third PWM signal, a second combinational logic circuit configured to generate the second digital value as a function of the first digital value and the enable signal, and a discrete proportional- derivative regulator circuit configured to vary the third digital value as a function of the second digital value and the digital sample. For example, in various embodiments, the periodic base pulses has a saw-tooth profile. In this case, the digital signal generator may comprise a counter configured to, in response to a clock signal having a given frequency, increase the first digital values by an increment value, and reset the first digital values when the first digital values reaches a given maximum value. In this case, the digital signal generator may also comprises an increment control circuit configured to generate the increment value for the counter as a function of data identifying the frequency or the clock signal, data identifying the frequency of the periodic base pulses, and the maximum value of the counter. Instead, for arbitrary base pulse waveforms, the digital signal generator may comprises a look-up table comprising a plurality of elements corresponding to a given number of samples of a standard waveform of the base pulses with a given standard frequency. Specifically, each element of the LUT has stored the amplitude of a respective sample of the standard waveform of the base pulses. Accordingly, the look-up table may receive at input a (phase) count value selecting a given sample, and the first digital value may be determined as a function of the amplitude of the respective selected sample read from the LUT. Accordingly, a (phase) counter may be configured to, in response to a clock signal, increase the (phase) count value by an increment value, whereby the counter represents a phase accumulator. In this case, an increment control circuit may be configured to generate the increment value as a function of data identifying the standard frequency of the standard waveform and data identifying the frequency of the periodic base pulses. In various embodiments, in order to improve the precision of the frequency of the base pulse, such increment control circuits may be configured to calculate an internal increment value, wherein the internal increment value has an integer part having a number of bits corresponding to the number of bits of the increment value, and a fractional part, e.g. having between 4 and 16 bits, preferably between 8 and 12 bits. Accordingly, the increment control circuit may be configured to vary the increment value, such that the increment value has an average value corresponding to the (higher resolution) internal increment value. In various embodiments, the apparatus may also be configured to invert the polarity of the supply current i _out . For example, in this case, the digital processing circuit comprises a third digital PWM generator circuit configured to generate a polarity signal indicating the polarity for the supply current i _out . For example, in this case, the switching stage may comprises a first half- bride comprising a first and a second electronic switch, wherein the intermediate node between the first and the second electronic switch is a first switching node, and a second half-bride comprising a third and a fourth electronic switch, wherein the intermediate node between the third and the fourth electronic switch is a second switching node, wherein the amplified PWM signal corresponds to the voltage between the first switching node and the second switching node. Accordingly, a driver circuit of the switching stage may be configured to generate drive signals for the first, second, third and fourth electronic switch as a function of the first PWM signal and the polarity signal. In various embodiments, the apparatus may also comprise a further digital processing unit. For example, in various embodiments, the digital processing circuit comprises a communication interface for exchanging data with the further digital processing unit; and a control circuit configured to receive via the first communication interface data identifying a treatment program to be executed and determine, as a function of the data identifying a treatment program to be executed, the frequency of the periodic base pulse, the packet switch-on period and the packet switch-off period, and the train switch-on period and the train switch-off period. For example, the data identifying a treatment program to be executed may comprise a program number or the respective timing data. The data identifying the treatment program to be executed may also identify the duty cycle of a PWM modulation applied directly to each base pulse. For example, the further digital processing unit may be configured to receive data identifying a treatment application, determine a sequence of a plurality of treatment programs as a function of the data identifying the treatment application and then execute sequentially the treatment programs of the sequence of treatment programs by sending data identifying the respective treatment program to the digital processing unit. For example, the further digital processing unit may be configured to receive the data identifying the treatment application via a user interface and/or a communication interface configured to exchange data with a processing system, such as a computer or smartphone. In various embodiments, the digital processing unit is an FPGA programmable via respective program data stored to a first non-volatile memory and/or the further digital processing unit is a microprocessor programmable via a respective firmware stored to a second non-volatile memory. In this case, the further digital processing unit may be configured to receive new program data for the digital processing unit and store the new program data to the first non-volatile memory, and/or receive a new firmware for the further digital processing unit and store the new firmware to the second non-volatile memory. In various embodiments, the apparatus may be configured to generate one or more further signals, synchronized with the supply current i _out for the antenna, such as an audio signal, e.g. applied to a headphone or speaker, a signal used to drive one or more light sources, and/or a signal used to drive a vibration transducer. For example, in various embodiments, the apparatus is configured to generate theses one or more further signals as a function of the second digital value. Brief description of the annexed drawings The embodiments of the present disclosure will now be described with reference to the annexed plates of drawings, which are provided purely to way of non-limiting example and in which: The features and advantages of the present invention will become apparent from the following detailed description of practical embodiments thereof, shown by way of non-limiting example in the accompanying drawings, in which: - Figures 1 and 2 show examples of systems for therapeutic treatments wherein electromagnetic waves are generated as a function of a drive signal comprising base pulses organized as packets and trains; - Figures 3a to 3e show exemplary waveforms of the base pulses of the drive signal of Figures 1 and 2; - Figure 4 shows an example of a pulse packet of the drive signal of Figures 1 and 2; - Figure 5 shows an example of a train of packets of the drive signal of Figures 1 and 2; - Figure 6 shows an example of the inversion of the polarity of the drive signal of Figures 1 and 2; - Figure 7 shows a further example of a system for therapeutic treatments with electromagnetic waves; - Figure 8 shows an embodiment of a drive signal according to the present disclosure; - Figure 9 shows an embodiment of a system for therapeutic treatments with electromagnetic waves, wherein the system comprises an apparatus configured to generate the drive signal of Figure 8, wherein the apparatus comprises a first digital processing circuit, a second digital processing circuit and a power amplifier; - Figure 10 shows a flow chart of the operation of the first digital processing circuit of the apparatus of Figure 9; - Figures 11A and 11B show embodiments of a switching stage of the power amplifier of Figure 9; - Figures 12A and 12B show embodiments of the drive signals of the switching stages of Figures 11A and 11B, respectively; - Figure 13 shows an embodiment of the power amplifier of the apparatus of Figure 9 comprising a switching stage of Figure 11A or 11B; - Figure 14 shows a block diagram of the second digital processing circuit of the apparatus of Figure 9; - Figure 15 shows embodiments of various signals generated by the second digital processing circuit of Figure 14; and - Figures 16 and 17 show embodiments of a waveform generator used by the second digital processing circuit of Figure 14. Detailed description of embodiments In the ensuing description, various specific details are illustrated aimed at enabling an in- depth understanding of the embodiments. The embodiments may be provided without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not shown or described in detail so that various aspects of the embodiments will not be obscured. Reference to “an embodiment” or “one embodiment” in the framework of this description is meant to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as “in an embodiment”, “in one embodiment”, or the like that may be present in various points of this description do not necessarily refer to one and the same embodiment. Moreover, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments. The references used herein are only provided for convenience and hence do not define the sphere of protection or the scope of the embodiments. In Figures 7 to 17 described below, parts, elements or components that have already been described with reference to Figures 1 to 6 are designated by the same references used previously in these figures. The description of these elements has already been made and will not be repeated in what follows in order not to burden the present detailed description. As explained in the foregoing, various embodiments of the present description relate to a system for therapeutic treatments with electromagnetic waves. As described in the foregoing, when using programs 1 or 3 of the apparatus of document WO 2012/172504 A1 for the treatment of the central and/or peripheral nervous system, e.g. for treating chronic neuroinflammation and/or neurodegenerative diseases such as Alzheimer's disease, multiple sclerosis or Parkinson's disease, only minor improvements could be shown. Generally, the inventor has observed that this problem could have various reasons, such as incorrect frequencies of the programs, or that a single program is insufficient for the treatment of a particular decease. In this respect, the inventor of the present application has observed, that the combination of programs 1, 3 and 6 seems to be most suitable for the treatment of the central and/or peripheral nervous system, e.g. for the treatment of the above mentioned diseases, insofar as an improvement of the result of the treatment could be observed. However, a rather surprising improvement could be observed when slightly adapting the embodiment shown in Figure 5 of document WO 2012/172504 A1, and which is reproduced herein as Figure 7. Specifically, in the embodiment shown in Figure 7, the apparatus 20 comprises a control circuit 22 configured for generating a signal S that corresponds to the signal described previously. In the embodiment considered, the signal S is sent through a power amplifier 24 to an antenna 30. Specifically, according to document WO 2012/172504 A1, the signal S comprises a plurality of base pulses I grouped in pulse packets P and in pulse trains Tr, wherein each pulse packet P consists of a series of base pulses I followed by a first pause T _{pac_off} , and wherein each pulse train Tr consists of a series of pulse packets P followed by a second pause T _{tr_off} . For example, each base pulse I may have a saw-tooth, square-wave, or sinusoidal waveform; or each base pulse I may comprise a series of curved profiles in such a way that in a pulse time interval T _{imp_on} the waveform is increasing and comprises a plurality of cusps 2 and 4. In the embodiment considered, the control circuit 22 comprises a waveform generator 226 configured to generate different waveforms (see for example Figure 3) with a certain frequency f _imp . In the embodiment considered, the control circuit 22 comprises also a processing unit 220 configured to generate the signal S. In the embodiment considered, the control circuit 22 comprises also a memory 222 in which the characteristic data of the signal S are saved, such as for example data identifying the durations T _{pac_on} , T _{pac_off} , T _{tr_on} and T _{tr_off} . In the case also the base pulses I are configurable, the memory 222 may also store data identifying the respective waveform and/or the durations T _{imp_on} and T _{imp_off} (see Figure 3). As described in the foregoing, document WO 2012/172504 A1 generates a signal having trains Tr of identical packets P, each comprising a given number n _imp of base pulses I. This is also shown in Figures 4 and 5, where the base pulses I start with the beginning of a packet P and all packets P are identical, thereby permitting that precise and constant harmonics are generated. Accordingly, by using a waveform generator 226, such a sequence of trains Tr of packets P may e obtained by: - activating the waveform generator 226 at the beginning of a packet P and deactivating the waveform generator 226 at the end of the interval T _{pac_on} , or, e.g. in case a PWM modulation of the base pulse I is performed, activating the waveform generator 226 at the beginning of each interval T _imp and deactivating the waveform generator 226 at the end of the interval T _{imp_on} ; or - by using switch-off durations T _{pac_off} and T _{tr_off} , which are multiples of the time T _imp of the base pulse I, whereby the start of a packet intrinsically corresponds to the start of a base pulse I. Generally, the second option may be rather unfeasible, because the switch-off durations T _{pac_off} and T _{tr_off} are not necessarily multiples of the time T _imp . Accordingly, in the embodiment of document WO 2012/172504 A1, the control circuit 22 uses the first option, wherein the processing unit 220 is configured to activate and deactivate the signal provided by the waveform generator 226 according to the data identifying durations T _{pac_on} , T _{pac_off} , T _{tr_on} and T _{tr_off} , and possibly also of the durations T _{imp_on} and T _{imp_off} (as stored to the memory 222). However, the inventor has observed that the result of the treatment improves significantly for the low frequency programs 1 to 4 when the waveform generator 226 is not activated at the beginning of each packet P, or even each interval T _imp , but the waveform generator 226 is maintained running and provides at output continuous base pulses I, with a given frequency f _imp / a given period T _imp . As mentioned before, while the frequency f _imp / period T _imp is usually constant for a given treatment program 1 to 9, the frequency f _imp / period T _imp may still be settable, e.g. for the frequencies 213 Hz and 231 Hz mentioned before. As mentioned before, for the specific programs 1 to 9 mentioned before, the period T _pac of a packet P does not correspond to a multiple of the period T _imp of the base pulse I. Accordingly, as also shown in Figure 8, a shifting effect is introduced between the packets P of a sequence of packets P. Thus, also in this case, the duration T _{pac_on} corresponds to a multiple of the period T _imp , but the packet P usually do not consist in a series of identical base pulses I, because the first pulse starts usually at an intermediate position of the base pulse I and similarly the last pulse usually ends at an intermediate position of the base pulse I. Thus, in such an arrangement, the packets P are not identical, and the spectrum of the signal S is broadened around the harmonics, more or less as in a dithering operation of the signal S. A similar effect occurs also for the trains, because the period T _tr of a train Tr does not correspond to a multiple of the period T _imp of the base pulse I. As mentioned before, such a broadening of the spectrum would be undesirable according to document WO 2012/172504 A1, which provides an arrangement configured to generate clearly defined series of frequencies only within certain ranges, while avoiding a wider frequency ranges, which according to document WO 2012/172504 A1 would provide only a low probability of inducing the effect of therapeutic resonance. In this respect, document EP 3160582 A1 already mentioned that the dynamic variation of the harmonics could be useful, e.g. in order to prevent the phenomenon of cell adaptation, with reduction of the sensitivity to the stimulation induced and of the consequent responses. Accordingly, the inventor performed further experiments, in particular: - varying the frequency f _imp of the base pulse, and the switch-off durations T _{pac_off} and T _{tr_off} of the packets in the apparatus of document WO 2012/172504 A1 according to a random dithering operation; and - varying the frequencies of the sinusoidal signals of the apparatus of document EP 3160582 A1 according to a random dithering operation. However, surprisingly the above described shifting operation by activating/deactivating a continuously running base pulse I obtained the best results. A possible explanation may reside in the fact that a dithering operation results in a random and rather chaotic variation of the frequencies of the electromagnetic wave. Conversely, the shift operation maintains the frequency of the trains, but additional and variable low power harmonics of the truncated first and last packet P, and similarly the first and last base pulses are added. Moreover, the shifting operation is not casual, but essentially results in a repetitive and cyclic pattern, which seems to be useful for the resonance effects. Figure 9 shows an embodiment of an apparatus 20a according to the present description. Specifically, the general architecture corresponds the architecture already described with respect to Figures 1 and 2, and the respective description fully applies. Specifically, also in this case, the apparatus 22a comprises a power amplifier, and a control circuit 22a configured to generate a drive signal DRV for the power amplifier. Specifically, as will be described in greater detail in the following, in various embodiments, the power amplifier is a class D power amplifier comprising a power/switching stage 24a receiving at input a PWM signal switching between two logic levels, e.g. a voltage Vdd and ground. For example, the voltage Vdd may correspond to the supply voltage of the control circuit 22a, such as a voltage between 2 and 5 V. In a class D amplifier, the power/switching stage provides thus at output terminals 240a and 240b an amplified PWM signal, e.g. switching between a voltage Vcc and ground, with Vcc being greater than the voltage Vdd, or between Vcc and –Vcc. For example, the voltage Vss may be between 9 and 48 V. In a class D amplifier, the amplified PWM signal at the output 240a/240b of the power stage 24a is provided to a filter stage 28, such as a low-pass or band-pass filter, which thus provides at output a signal having an amplitude proportional to the duty cycle of the amplified PWM signal. Accordingly, the signal at the output of the filter stage 28 may be provided to an antenna 30. For example, as shown in Figure 9, the apparatus 20a may comprise for this purpose two terminals 202a and 202b configured to be connected to an antenna/diffuser 30. Generally, the filter stage 28 may also be external with respect to the apparatus 20a and, e.g., incorporated in the antenna/diffuser 30. Generally, the filter stage 28 may also comprise the capacitance and inductance of the antenna 30. Accordingly, the terminals 202a and 202b may be connected to the output of the filter stage 28 (when the filter stage 28 is incorporated in the apparatus 20a) or to the output of the power stage 24a (when the filter stage 28 is external with respect to the apparatus 20a). Accordingly, the apparatus 20a may also comprise a power supply 26a configured to receive an input voltage Vin and generate the supply voltage Vdd (and possible further supply voltages) for the control circuit 22a and the supply voltage Vcc for the power stage 24a. Generally, the power supply 26a may be any AC/DC or DC/DC power supply adapted to generate a plurality of supply voltages (e.g. from the mains and/or a battery integrated in the apparatus 20a). For example, in various embodiments, the power supply 26a may comprise an electronic converter, such as a flyback, forward or half-bridge converter, comprising a transformer with a plurality of secondary windings, each secondary winding providing a respective supply voltage. Alternatively may be used a cascade of voltage regulators, wherein a first voltage regulator generates the supply voltage Vcc from the input voltage Vin and a second voltage regulator generates the voltage Vdd from the voltage Vcc. Generally, as mentioned before the power supply 26a may be also at least in part external with respect to the apparatus 20a. For example, an external AC/DC electronic converter may generate a DC voltage Vin from the mains, and one or more internal DC/DC voltage regulators may generate the voltages Vcc and Vdd. Generally, the mentioned DC/DC voltage regulators may be e.g. switched mode electronic converters (e.g. in order to reduce power losses) or linear regulators (e.g. in order to reduce the electromagnetic interference). In various embodiments, the apparatus 20a may also comprise a user interface 50, e.g. for receiving an input from a user and/or for providing status information to the user. For example, the user interface 50 may be used to select a treatment program corresponding to one of the programs 1 to 9 (or a subset thereof) or a treatment application corresponding to a predetermined sequence of programs 1 to 9, e.g. programs 1, 3 and 6. Conversely, the status information shown to the user may include one or more of the following information: whether a treatment program is running, which treatment program has been selected. the time remaining of the treatment program, and/or diagnostic information, e.g. indicating that no antenna 30 has been connected to the terminals 202a and 202b. Accordingly, the user interface 50 may include buttons, a keyboard, luminous indicators (such as LEDs), a display, a touch screen, etc. Figure 9 shows also an embodiment of the control circuit 22a. Specifically, in the embodiment considered, the control circuit 22a comprises a first digital processing circuit 220a, such as a microprocessor programmable via software instructions. Generally, the microprocessor may also form part of a microcontroller. The first digital processing circuit 220a is connected to a non-volatile memory 222a. For example, the non-volatile 222a may correspond to the program memory of the microprocessor 220a, such as an EEPROM (Electrically Erasable Programmable Read-Only Memory) or a FLASH memory, i.e. the memory having stored the firmware/software executed by the microprocessor 220a. Specifically, in various embodiments, the non volatile memory 222a is used to store the timing data of the signal S to be generated, such as data identifying the frequency f _imp of the base pulse I, optionally the type of the base pulse if different waveforms are supported, such as saw-tooth and profile with cusps, data identifying the durations T _{pac_on} and T _{pac_off} of a package P, and data identifying the durations T _{tr_on} and T _{tr_off} of a train Tr. As mentioned before, in various embodiments, the duration T _{pac_on} corresponds to a multiple of the period T _imp = 1/f _imp and the duration T _{tr_on} corresponds to a multiple of the period T _pac = T _{pac_on} + T _{pac_off} . In various embodiments, the control circuit 224 may also comprise a communication interface 224a for connection to an external processing system 10, such as a PC, a tablet, a smartphone or a remote server, e.g. a web-server. For example, the communication interface 224a may comprise at least one of: - a reader device for a portable memory support; - a communication interface for a wired communication with the processing system 10, such as a serial communication interface, e.g. a RS-232 or USB (Universal Serial Bus) communication interface, or an Ethernet network adapter; - a short-range wireless communication interface, such as a NFC (Near Field Communciation) or Bluetooth® communication interface; - a Wi-Fi communication interface according to the IEEE 802.11 standard; and - a mobile communication interface, such as a GPRS (General Packet Radio Service), UMTS (Universal Mobile Telecommunications System) modem, HSPA (High-Speed Packet Access), or LTE (Long Term Evolution) modem. Accordingly, the communication with the processing system 10 may be indirectly via a portable memory support, directly via a wired or wireless communication, via a LAN (Local- Area Network) or even via a WAN (Wide-Area Network), such as Internet. Generally, the communication interface and/or the memory 222a may also be integrated in a microcontroller comprising the microprocessor 220a. In the embodiment considered, the communication interface 224a may be used to communicate with the processing circuit 220a, e.g. in order to control the operation of the apparatus 20a. For example, the processing circuit 220a may be configured to implement one or more of the above functions described with respect to the user interface 50 by exchanging commands and/or status information with the processing system 10. For example, in this way, a smartphone or tablet may be used to control and/or monitor the operation of the apparatus 20a, e.g. via a Bluetooth® or Wi-Fi communication. In various embodiments, the processing circuit 220a may also be configured to receive new timing data of the signal S from the processing system 10 and store these data to the memory 222a. Similarly, in various embodiments, the communication interface 224a and the processing system 220a may also be configured to receive a new firmware for the processing unit 220a from the processing system 10 and store the new firmware to the memory 222a. In various embodiments, the control circuit 22a comprises also a second digital processing circuit 220b, preferably a digital hardware circuit, such as an ASIC (Application- specific integrated circuit) or an FPGA (Field Programmable Gated Array). Accordingly, the control circuit 22a may also comprise a second non-volatile memory 222b having stored the firmware/program data for the second digital processing circuit 220b. In various embodiments, the communication interface 224a and the processing system 220a may thus also be configured to receive a new firmware for the processing circuit 220b from the processing system 10 and store the new firmware to the memory 222b. Generally, the operation of the various circuits of the processing circuit 220b may also be implemented via software modules implementing the same function. For example, in this way, the operation of the processing circuit 220a and 220b may also be implemented in a single processing circuit, such as a DSP (Digital Signal Processor). However, as will be described in the following, several parallel processing operations are implemented within the processing circuit 220b, which would require a rather fast microprocessor in order to implement the same operations via software instructions. The inventor has observed that, also taking into account a typical production volume of the apparatus 20a, the most cost efficient solution is a microprocessor 220a configured to manage the user interface and the optional communication interface 224a, and a FPGA 220b for managing the generation of the signal S. Specifically, in the embodiment considered, the second digital processing circuit 220b essentially implements a custom programmable signal generator, wherein the operation of the second digital processing circuit 220b is controlled by the first processing circuit 220a. Figure 10 shows a flow chart of an embodiment of the operation of the first digital processing circuit 220a. Specifically, in the flowchart, it is assumed that the first digital processing circuit 220a already has received at instructions (e.g. via the user interface 50 or the communication interface 224a) requesting the execution of a treatment application. As mentioned before, the treatment application may correspond to a given single treatment program selected, e.g. from one of the previously described programs 1 to 9, or a subset thereof, or a given sequence of treatment programs, e.g. programs 1, 3 and 6. Specifically, in various embodiments, the apparatus 20a may have stored the timing data of the previous described treatment programs 1 to 9. Conversely, in various embodiments, also different treatment programs may be stored. Specifically, the inventor has observed that the frequency f _imp of the base pulse I (when maintained substantially constant) seems to be less relevant with the described shifting operation, while the most relevant data are the times T _pac and T _tr of the packets and trains, and the number n _pac . Accordingly, the programs could also have, e.g., a different frequency f _imp . In various embodiments the frequency f _imp is however still selected in a range between 100 Hz and 1 kHz, preferably between 100 and 400 Hz, even more preferably between 150 and 250 Hz. For example, in various embodiments, a slight modification of program 5 has been performed: - new program 5: saw-tooth base pulse with frequency f _imp = 212.76 Hz, where the duration of the base pulse is T _imp = 4.70 ms, the time T _{pac_on} is set to 75.20 ms (corresponding to the time of 16 base pulses), the pause between the packets is reduced to T _{pac_off} = 21 ms, the time T _{tr_on} is set to 384.80 ms (corresponding to the time of 4 packets) and the pause between the trains is T _{tr_off} = 370 ms; Conversely, program 9 of document WO 2012/172504 A1 uses a base pulse with cusps and provides the broadest frequency spectrum with the highest number of harmonics. Generating such a profile with cusps may be rather complex with a digital circuit. Accordingly, in various embodiments, a similar broad frequency spectrum has been obtained by using the following timing data for a modified program 9: - new program 9: saw-tooth base pulse with frequency f _imp = 189.75 Hz, where the duration of the base pulse is T _imp = 5.27 ms, the time T _{pac_on} is set to 26.35 ms (corresponding to the time of 5 base pulses), the pause between the packets is set to T _{pac_off} = 16.85 ms, the time T _{tr_on} is set to 1728.00 ms (corresponding to the time of 40 packets) and the pause between the trains is T _{tr_off} = 1600 ms. Thus, in various embodiments, the other programs 1-4 and 6-8 may have the following characteristics: - program 1: saw-tooth base pulse with frequency f _imp = 212.76 Hz, where the duration of the base pulse is T _imp = 4.70 ms, the time T _{pac_on} is set to 206.80 ms (corresponding to the time of 44 base pulses), the pause between the packets is T _{pac_off} = 140.00 ms, the time T _{tr_on} is set to 1387.20 ms (corresponding to the time of 4 packets) and the pause between the trains is T _{tr_off} = 1450 ms; - program 2: saw-tooth base pulse with frequency f _imp = 231.48 Hz, where the duration of the base pulse is T _imp = 4.32 ms, the time T _{pac_on} is set to 146.88 ms (corresponding to the time of 34 base pulses), the pause between the packets is T _{pac_off} = 105.00 ms, the time T _{tr_on} is set to 1007.52 ms (corresponding to the time of 4 packets) and the pause between the trains is T _{tr_off} = 1100 ms; - program 3: saw-tooth base pulse with frequency f _imp = 212.76 Hz, where the duration of the base pulse is T _imp = 4.70 ms, the time T _{pac_on} is set to 94.00 ms (corresponding to the time of 20 base pulses), the pause between the packets is T _{pac_off} = 55.00 ms, the time T _{tr_on} is set to 596.00 ms (corresponding to the time of 4 packets) and the pause between the trains is T _{tr_off} = 600 ms; - program 4: saw-tooth base pulse with frequency f _imp = 231.48 Hz, where the duration of the base pulse is T _imp = 4.32 ms, the time T _{pac_on} is set to 77.76 ms (corresponding to the time of 18 base pulses), the pause between the packets is T _{pac_off} = 37.00 ms, the time T _{tr_on} is set to 459.04 ms (corresponding to the time of 4 packets) and the pause between the trains is T _{tr_off} = 480 ms; - program 6: saw-tooth base pulse with frequency f _imp = 231.48 Hz, where the duration of the base pulse is T _imp = 4.32 ms, the time T _{pac_on} is set to 60.48 ms (corresponding to the time of 14 base pulses), the pause between the packets is T _{pac_off} = 16.00 ms, the time T _{tr_on} is set to 305.92 ms (corresponding to the time of 4 packets) and the pause between the trains is T _{tr_off} = 350 ms; - program 7: saw-tooth base pulse with frequency f _imp = 212.76 Hz, where the duration of the base pulse is T _imp = 4.70 ms, the time T _{pac_on} is set to 56.40 ms (corresponding to the time of 12 base pulses), the pause between the packets is T _{pac_off} = 6.60 ms, the time T _{tr_on} is set to 252.00 ms (corresponding to the time of 4 packets) and the pause between the trains is T _{tr_off} = 220 ms; - program 8: saw-tooth base pulse with frequency f _imp = 231.48 Hz, where the duration of the base pulse is T _imp = 4.32 ms, the time T _{pac_on} is set to 43.20 ms (corresponding to the time of 10 base pulses), the pause between the packets is T _{pac_off} = 2.44 ms, the time T _{tr_on} is set to 183.00 ms (corresponding to the time of 4 packets) and the pause between the trains is T _{tr_off} = 176 ms. For example, the timing in [ms] of the above programs may be summarized according to the following table: As described in the foregoing, in various embodiments, a PWM modulation may also be applied to each base pulse. For example, in various embodiments, a PWM modulation with a duty cycle of 50% is used, i.e. T _{imp_on} = T _{imp_off} = T _imp /2. As mentioned before, the apparatus 20a may support only a single treatment application or support plural treatment applications. For example, in various embodiments, the apparatus 20a is configured to support at least the following treatment applications: - a first treatment application executing only program 1; - a second treatment application executing only program 3; - a third treatment application executing only program 6; - a fourth treatment application executing the sequence of programs 1, 3 and 6, wherein any order may be used, but preferably the order 1, 3 and 6 is used. Specifically, in various embodiments, the apparatus 20a is configured to support a total and/or a local operating mode. Specifically, in the total operating mode, a large planar antenna 30 is connected to the apparatus 20a, thereby permitting a global/total stimulation of the body of the target (human). For example, in this case, the antenna 30 may be a planar pad or mat having a length between 120 cm and 250 cm, preferably between 150 cm and 200 cm, and a width between 40 cm and 120 cm, preferably between 60 cm and 90 cm. Conversely, in the local operating mode, a smaller antenna 30 is connected to the apparatus 20a, thereby permitting a local stimulation of only a part of the body of the target (human). For example, in this case, the antenna 30 may be a planar pad or mat having a length between 20 cm and 120 cm, preferably, between 20 cm and 60 cm, and a width between 20 cm and 60 cm, or an anatomically modeled antenna, e.g. having a shape being complementary to the area to be treated. Generally, the apparatus 20a may support only a single operating mode (total or local), or both operating modes. In the latter case, the apparatus 20a may comprise (in line with the description of Figure 2) two separate outputs: a first output configured to be connected to a global antenna and a second output configured to be connected to a local antenna. For example, in this case, the outputs may have different mechanical connectors. However, the apparatus 20a may also comprise only a single output and selection between the global or local operating mode may be performed explicitly via a switch of the user interface 50, or by selecting a given treatment application. For example, in various embodiments, the apparatus is configured to, once having selected a treatment application, execute first a respective total treatment application and then one or more respective local treatment applications. However, the apparatus may also be configured to permit a separate selection of the total and local treatment applications. For example, in various embodiments, the apparatus 20a is configured to support one or more of the following global and/or local treatment applications: - e.g. for treating osteoarticular and musculoskeletal pathologies, a total and/or a local (trauma area) treatment application executing both the sequence of programs 6 and 8; - e.g. for treating vascular pathologies, a total and/or a local (trauma area) treatment application executing both the sequence of programs 6 and 5; - e.g. for treating ulcers or a ischemic diabetic foot, a total and/or a local (ulcer area or foot) treatment application executing both the sequence of programs 6 and 8; and - e.g. for treating a neuropathic diabetic foot, a total treatment application executing the sequence of programs 3, 6 and 8 and/or a local (foot) treatment application executing the sequence of programs 6 and 8. As mentioned before, while also showing improvements for the programs 6 to 8 (and permitting a simplification of the implementation of the program 9), the apparatus 20a has been developed mainly in order to improve the programs 1 to 4. Accordingly, in addition to or as alternative to the above treatment applications, in various embodiments, the apparatus 20a is configured to support one or more of the following global and/or a local treatment applications: - e.g. for treating multiple sclerosis, a total treatment application executing the sequence of programs 1, 3 and 6 and/or a local (head) treatment application executing the sequence of programs 3 and 6; - e.g. for treating Parkinson's disease, a total treatment application executing the sequence of programs 3, 6 and 3 and/or a first local (head) treatment application executing the sequence of programs 3 and 6 and/or a second local (abdomen) treatment application executing the sequence of programs 8 and 8; - e.g. for treating Alzheimer's disease or senile dementia, a total treatment application executing the sequence of programs 3, 6 and 9 and/or a local (head) treatment application executing the sequence of programs 3 and 6; - e.g. for treating postictal states, a total treatment application executing the sequence of programs 3, 3 and 6 and/or a local (head) treatment application executing the sequence of programs 6 and 6; - e.g. for treating fibromyalgia or chronic fatigue syndrome, a total treatment application executing the sequence of programs 3, 6 and 9 and/or a local (pain area) treatment application executing the sequence of programs 6 and 8; and - e.g. for treating the Psycho-Neuro-Endocrine-Immunology (P.N.E.I.) system, a total treatment application executing the sequence of programs 9, 6 and 9 and/or a local (head) treatment application executing the sequence of programs 3 and 6. Accordingly, usually a sequence of treatment programs has to be executed, wherein each treatment program may has associated respective timing data. Specifically, after a start step 1000, the first digital processing circuit 220a determines at a step 1002 the treatment program to be executed. As mentioned before, the treatment program may also correspond to the first treatment program of a treatment application. For example, the sequence of treatment program to be executed for a given treatment application may be stored in a Look-Up Table. In various embodiments, the first digital processing circuit 220a sends at the step 1002 one or more control commands CTRL to the second digital processing circuit 220b including data identifying the treatment program to be executed. For example, in various embodiment, the data identifying the treatment program to be executed may comprise timing data of the signal S. Accordingly, in this case, the first digital processing circuit 220a may read the timing data from the memory 222a and send at the step 1002 one or more control commands CTRL to the second digital processing circuit 220b, wherein the one or more control commands CTRL comprise the timing data of the signal S to be generated, such as: - data identifying the frequency f _imp of the base pulse I; - optionally data identifying the duty cycle of the base pulse I; - optionally the type of the base pulse if different waveforms are supported, such as saw- tooth and profile with cusps; - data identifying the durations T _{pac_on} and T _{pac_off} of a package P; - data identifying the durations T _{tr_on} and T _{tr_off} of a train Tr; - optionally data identifying the inversion period of the signal S. Generally, these data may correspond to the data stored to the memory 222a or may be determined as a function of the timing data stored to the memory 222a. Additionally or alternatively, the timing data of one or more treatment programs may also be stored directly in the second digital processing circuit 220b or in the memory 222b and read by the second digital processing circuit 220b. For example, in this way, a first set of standard programs, e.g. programs 1, 3 and 6, may already be pre-configured within the second digital processing circuit 220b, and one or more additional programs may be configured by storing the respective timing data to the memory 222a. Accordingly, in this case, the first digital processing circuit 220a may send at the step 1002 one or more control commands CTRL to the second digital processing circuit 220b, wherein the one or more control commands comprise a program number to be executed. Generally, the program number does not necessarily corresponds to the above mentioned treatment program numbers, but e.g. program 1 could correspond to treatment program 1, program 2 could correspond to treatment program 3, program 3 could correspond to treatment program 6. At a step 1004, the first digital processing circuit 220a sends a control command CTRL to the second digital processing circuit 220b requesting that the generation of the signal S should be started with the characteristics communicated at the step 1002. Generally, the steps 1002 and 1004 may also be combined, because the data identifying the treatment program to be executed (step 1002) may also be included in the instruction requesting the generation of the signal S. Accordingly, in response to the start instruction, the second digital processing circuit 220b generates the signal S as will be described in greater detail in the following. In various embodiments, once having sent the start command (step 1004), the first digital processing circuit 220a proceeds then to a step 1006. The step 1006, essentially corresponds to a wait step. For example, during the step 1006, the first digital processing circuit 220a may monitor the operation of the second digital processing circuit 220b, e.g. by sending one or more control commands CTRL to the second digital processing circuit 220b requesting status data, or the second digital processing circuit 220b may send autonomously status data to the first digital processing circuit 220a. In the embodiment considered, the first digital processing circuit 220a then verifies at a step 1008 whether the treatment time of the current treatment program has elapsed. For example, in various embodiments, the first digital processing circuit 220a monitors the treatment time and determines whether a predetermined treatment time associated with the current treatment program has been reached, such as 480 s. Additionally or alternatively, the second digital processing circuit 220b may monitor the treatment time and determine whether a predetermined treatment time associated with the current treatment program has been reached. In this case, the second digital processing circuit 220b may include in the status information (sent at the step 1006 to the first digital processing circuit 220a) data indicating whether the treatment program is running or whether the treatment time has elapsed. In case the first digital processing circuit 220a determines that the treatment time of the current treatment program has not elapsed (output “N” of the verification step 1008), the first digital processing circuit 220a returns to the step 1006. Conversely, in case the first digital processing circuit 220a determines that the treatment time of the current treatment program has elapsed (output “Y” of the verification step 1008), the first digital processing circuit 220a proceeds to a step 1010. Specifically, in various embodiments, the first digital processing circuit 220a verifies at a step 1010 whether the current treatment program was the last treatment program to be executed. As mentioned before, a single treatment program or a sequence of treatment programs may be executed. In case the first digital processing circuit 220a determines that the current treatment program was not the last treatment program to be executed (output “N” of the verification step 1010), the first digital processing circuit 220a returns to the step 1002, where the next treatment program of a sequence of treatment programs is selected and the above procedure is repeated for the next treatment program. Conversely, in case the first digital processing circuit 220a determines that the current treatment program was the last treatment program to be executed (output “Y” of the verification step 1010), e.g. because only a single program has to be executed or because the treatment program was the last of a sequence of treatment programs, the procedure terminates at a stop step 1012. Generally, as described in the foregoing, the digital processing circuit 220a may also provide status data of the execution of the treatment application to the processing system 10. Accordingly, in various embodiments, the second digital processing circuit 220b may be configured to support at least one of: - a generic operation mode, in which the second digital processing circuit 220b is configured to generate the signal S as a function of timing data received from the digital processing circuit 220a; and/or - one or more specific operation modes, in which the second digital processing circuit 220b is configured to generate the signal S as a function of timing data determined as a function of a program number received from the digital processing circuit 220a. As described in the foregoing (see also Figure 9), in various embodiments, the power amplifier is implemented with a power/switching stage 24a and a filter stage 28, thereby forming a class D amplifier. For example, Figures 11A and 11B show possible embodiments of the power stage 24a. Specifically, the power stage 24a of Figure 11A is based on a half-bridge, and the power stage 24a of Figure 11B is based on a full-bridge. For example, in Figure 11A, the power stage 24a comprises two electronic switches SW1 and SW2, such as Field-Effect Transistors (FET), e.g. MOSFETs, connected (e.g. directly) in series between the voltage Vcc and ground, wherein the intermediate node between the electronic switches SW1 and SW2 represents a switching node. Accordingly, the switching node may be set to Vcc (SW1 closed and SW2 opened) or ground (SW1 opened and SW2 closed). Accordingly, the output terminal 240a may correspond to the switching node between the switches SW1 and SW2, and the output terminal 240b may correspond to ground. In the embodiment considered, the power stage 24a comprises thus also a driver circuit 242 configured to generate drive signals DRV1 and DRV2 for the electronic switches SW1 and SW2, respectively, wherein the drive signals DRV1 and DRV2 are generated as a function of the drive signal DRV. Generally, in such an arrangement, only one of the electronic switches of the half bridge is closed. For example, in various embodiments, the logic level of the drive signal DRV1 may correspond to the logic level of the drive signal DRV, and the logic level of the drive signal DRV2 may correspond to the inverted version of the logic level of the drive signal DRV. Conversely, Figure 12A shows an embodiment of the drive signals, wherein also dead times TD1 and TD2 are introduced between the edges of the drive signals. Generally, the PWM drive signal DRV is a pulsed signal, wherein the signal DRV is set to high for a given switch-on time T _ON and to low for a given switch-off time T _OFF , wherein the switching period T _SW of the signal DRV corresponds to the sum of the switch-on time T _ON and the switch-off time T _OFF (T _SW = T _ON + T _OFF ), and the duty cycle D corresponds to the ratio between the switch-on time T _ON and the switching period T _SW (D = T _ON /T _SW ). Generally, while being preferable, it is not particularly relevant whether the switching period T _SW is constant, but the duty cycle D of the drive signal DRV should indicate a requested average voltage between the terminals 240a and 240b. For example, with such drive signal DRV, the driver circuit 242 may be configured to determine rising and falling edges in the signal DRV, and: - in response to detecting a rising edge, set the signal DRV2 immediately to low and set the signal DRV1 to high after a delay TD1 (with respect to the rising edge); and - in response to detecting a falling edge, set the signal DRV1 immediately to low and set the signal DRV2 to high after a delay TD2 (with respect to the falling edge). Such delays may be useful in order to avoid that the switches of a half-bridge are closed contemporaneously. However, such delays TD1 and TD2 are usually small and thus will be neglected in the following. Conversely, in Figure 11B, the power stage 24a comprises a first half-bridge comprising two electronic switches SW1 and SW2, such as FETs, e.g. MOSFETs, connected (e.g. directly) in series between the voltage Vcc and ground, and a second half-bridge comprising two electronic switches SW3 and SW4, such as FETs, e.g. MOSFETs, connected (e.g. directly) in series between the voltage Vcc and ground. Accordingly, the switching node between the electronic switches SW1 and SW2 and the switching node between the electronic switches SW3 and SW4 may be set to Vcc (SW1/SW3 closed and SW2/SW4 opened) or ground (SW1/SW3 opened and SW2/SW4 closed). In this case, the output terminal 240a may correspond to the switching node between the switches SW1 and SW2, and the output terminal 240b may correspond to the switching node between the switches SW3 and SW4. Specifically: - when the switches SW1 and SW4 are closed (with the switches SW2 and SW3 opened), the voltage between the terminals 240a and 240b corresponds to Vcc, - when the switches SW2 and SW3 are closed (with the switches SW1 and SW4 opened), the voltage between the terminals 240a and 240b corresponds to -Vcc, - when the switches SW1 and SW3 are closed (with the switches SW2 and SW4 opened), the voltage between the terminals 240a and 240b corresponds to zero, and - when the switches SW2 and SW4 are closed (with the switches SW1 and SW3 opened), the voltage between the terminals 240a and 240b corresponds to zero. Accordingly, the arrangement of Figure 11B may be used when also the polarity of the signal S should be inverted (see Figure 6). In the embodiment considered, the power stage 24a comprises thus also a driver circuit 242 configured to generate drive signals DRV1, DRV2, DRV3 and DRV4 for the electronic switches SW1, SW2, SW3 and SW4, respectively, wherein the drive signals DRV1, DRV2, DRV3 and DRV4 are generated as a function of the drive signal DRV and a polarity signal POL. For example, Figure 12B shows an embodiment for generating the drive signals DRV1 to DRV4. Generally, Figure 12B does not show the dead times, but also in this case may be introduced dead times between the edges of the drive signals DRV1 and DRV, and the drive signals DRV3 and DRV4, respectively. Specifically, in the embodiment considered, the driver circuit 242 is configured to determine rising and falling edges in the polarity signal POL and the drive signal DRV, and: - in response to detecting a first type of edge (e.g. a rising edge) in the polarity signal POL, set the drive signal DRV3 to low (immediately) and the drive signal DRV4 to high (immediately or possibly after a delay), and: - in response to detecting a rising edge in the signal DRV, set the signal DRV1 to high (immediately or possibly after a delay) and set the signal DRV2 to low (immediately), whereby the voltage V ₂₄₀ between the terminals 240a and 240b corresponds to Vcc, and - in response to detecting a falling edge in the signal DRV, set the signal DRV1 to low (immediately) and set the signal DRV2 to high (immediately or possibly after a delay), whereby the voltage V ₂₄₀ between the terminals 240a and 240b corresponds to zero; and - in response to detecting a second type of edge (e.g. a falling edge) in the polarity signal POL, set the drive signal DRV3 to high (immediately or possibly after a delay) and the drive signal DRV4 to low (immediately), and: - in response to detecting a rising edge in the signal DRV, set the signal DRV2 to high (immediately or possibly after a delay) and set the signal DRV1 to low (immediately), whereby the voltage V ₂₄₀ between the terminals 240a and 240b corresponds to -Vcc, and - in response to detecting a falling edge in the signal DRV, set the signal DRV2 to low (immediately) and set the signal DRV1 to high (immediately or possibly after a delay), whereby the voltage V ₂₄₀ between the terminals 240a and 240b corresponds to zero. Accordingly, in various embodiments, the second digital processing circuit 220b is configured to generate the drive signal DRV for the power stage 24a, wherein the drive signal DRV corresponds to a PWM signal, and optionally the polarity signal POL. Generally, the information of the polarity signal POL may also be transmitted via the drive signal DRV, e.g. by switching the drive signal DRV between three levels (“+1”, “0”, “-1”). For example, Figure 13 shows an embodiment of the complete power amplifier at the example of a half-bridge as shown in Figure 11A, but also the full-bridge of Figure 11B could be used. Specifically, in the embodiment considered, the input terminals of the filter stage 28 are connected to the output terminals 240a and 240b of the power stage 24a, and the output terminals of the filter stage 28 are connected to the antenna 30, e.g. via the terminals 202a and 202b. For example, in the embodiment considered, the filter stage 28 implements an LC low pass filter. For example, in this case, and inductance L _F , such as an inductor may be connected between the terminals 240a and 202a, and a capacitance C _F , such as a capacitor may be connected between the terminals 202a and 202b. However, also other analog low-pass or band-pass filters may be used, preferably passive filters comprising only reactive components (inductances and capacitances). As mentioned before, the filter stage 28 may also comprise the inductance (and similarly capacitance and/or resistance) of the antenna 30. Accordingly, the voltage applied to the antenna 30 (approximately) corresponds to the average voltage between the terminals 240a and 240b (e.g., between Vcc and ground, or between Vcc and –Vcc). However, indeed the signal S should correspond to the current i _out provided via the terminals 202a and 202b to the antenna 30. For this reason, in various embodiments, the apparatus 20a comprises a current sensor 228 configured to generate a signal CS indicative of (and preferably proportional to) the current i _out . For example, in various embodiments, the current sensor 228 is connected (e.g. directly) in series with the terminals 202a and 202b. However, the current sensor 228 may also be connected (e.g. directly) in series with the output terminals 240a and 240b of the power stage 24a, because the current provided by the power/switching stage 24a may also be used to estimate the current i _out . For example, the current sensor 228 may be a shunt resistor R _S , e.g. a shunt resistor R _S connected in series with the terminals 202a and 202b, wherein the voltage at the resistor R _S is proportional to the current i _out provided via the terminals 202a and 202b. In this case, the second digital processing circuit 220b may be configured to vary the PWM drive signal DRV as a function of the signal CS in order to regulate the requested profile of the current i _out , i.e. of the signal S. Specifically, for this purpose, the control circuit 22a may comprise an analog-to-digital converter (A/D) 228b, such as a sigma-delta converter, which is configured to provide digital samples CS _D of the signal CS. Generally, e.g. in case the signal CS is not directly proportional to the current flowing through the antenna 30 (e.g. because the sensor 228 is connected to the output terminals of the power stage 24a), a low-pass filter 228a may be connected between the current sensor 228 and the A/D 228b, i.e. the A/D 228b may receive a low-pass filtered version CS’ of the signal CS. Additionally or alternatively, the block 228a may comprise a rectifier circuit, i.e. the A/D 228b may receive a rectified version CS’ of the signal CS. For example, this may be useful in case the polarity of the voltage between the terminals 240a and 240b may be inverted (see the description of Figures 11B and 12B). Generally, the low pass filtering and/or rectification of the block 228a may also be implemented digitally within the second digital processing circuit 220b. Accordingly, in various embodiments, the second digital processing circuit 220b is configured to obtain digital samples CS _D indicative of (and preferably proportional to) the (e.g. absolute value of the) current flowing through the antenna 30. As mentioned before, the second digital processing circuit 220b may be configured to vary the PWM drive signal DRV as a function of the samples CS _D . However, the samples CS _D may also be used for other purposes. For example, the first or the second digital processing circuit 220a/220b may use the samples in order to determine whether the antenna 30 is disconnected, e.g. because the values CS _D are below a given minimum threshold, or damaged, e.g. because the values CS _D are above a given maximum threshold. Figure 14 shows an embodiment of the second digital processing circuit 220b. Specifically, in the embodiment considered, the second digital processing circuit 220b is configured to generate the drive signal DRV as a function of digital data S _D identifying a requested amplitude and the data CS _D indicating the actual amplitude of the current flowing through the antenna 30. Substantially, in the embodiment considered, the data S _D correspond to digital values of the signal S, i.e. the evolution of the values S _D should correspond to the profile of the signal S described with respect to Figures 3 to 6 (with the additional shifting effect). Accordingly, in the embodiment considered, the second digital processing circuit 220b comprises a digital hardware circuit 2240 configured to generate the sequence of values S _D as a function of the timing data of the treatment program to be executed. For example, in the embodiment considered, the second digital processing circuit 220b comprises a communication interface 2220 for exchanging data with the first digital processing unit 220a, in particular the previous mentioned control commands CTRL. Specifically, in various embodiments, the control commands CTRL comprise data identifying the treatment program to be executed, such as a program number or the respective timing data. For example, in various embodiments, the communication interface 2220 may be an Universal Asynchronous Receiver/Transmitter (UART), Inter-Integrated Circuit (I2C) or Serial Peripheral Interface (SPI) communication interface. In various embodiments, a circuit 2222 is thus configured to determine the timing data of the treatment program to be executed as a function of the data identifying the treatment program to be executed, e.g. by extracting the timing data from the control command(s) CTRL, or extracting the program number from the control command(s) CTRL and determining the timing data as a function of the program number. Generally, in the latter case, the timing data associated with a given the program number may be fixed or programmable, e.g. by storing respective timing data to the memory 222b. In various embodiments, the circuit 2222 is configured to provide the following data to the digital hardware circuit 2240: - data identifying the frequency f _imp of the base pulse I; - optionally data identifying the duty cycle of the base pulse I; - optionally the type P _imp of the base pulse if different waveforms are supported, such as saw-tooth and profile with cusps; - data identifying the durations T _{pac_on} and T _{pac_off} of a package P; - data identifying the durations T _{tr_on} and T _{tr_off} of a train Tr; - optionally data identifying the inversion period of the signal S. Figure 14 also shows a possible embodiment of the digital hardware circuit 2240. Specifically, in the embodiment considered, the digital hardware circuit 2240 comprises: - a digital base pulse generator 2224 configured to generate a sequence of (continuous) digital samples S _imp of the base pulse I as a function of the data identifying the frequency f _imp of the base pulse I and optionally the type P _imp of the base pulse; and - an enable circuit 2226 configured to generate an enable signal EN as a function of the data identifying the durations T _{pac_on} and T _{pac_off} of a package P and data identifying the durations T _{tr_on} and T _{tr_off} of a train Tr. For example, the digital samples S _imp may have 8, 16, 24 or 32 bit. In various embodiments, the digital hardware circuit 2240 comprises also logic gates 2234, such as a multiplexer or AND gates, configured to generate the values S _D by: - when the enable signal EN has a first logic level (e.g. high), setting the value S _D to the value S _imp ; and - when the enable signal EN has a second logic level (e.g. low), setting the value S _D to a predetermined value (e.g. zero) indicating that the output of the power stage 24a should be set to zero volt (see also the description of Figures 11 and 12. Accordingly, in the embodiment considered, the signal S _D (having usually the same number of bits as the signal S _imp ) at the output of the logic gates 2234 corresponds to the signal S described with respect to Figure 8. For example, in various embodiments, the enable circuit 2226 comprises: - a first digital PWM generator circuit configured to generate a first PWM signal PWM _P , wherein, during each switching cycle with period T _pac , the signal PWM _P is set to high for the time T _{pac_on} and low for the time T _{pac_off} ; - a second digital PWM generator circuit configured to generate a second PWM signal PWM _Tr , wherein, during each switching cycle with period T _tr , the signal PWM _Tr is set to high for the time T _{tr_on} and low for the time T _{tr_off} ; and - a logic gate 2232, such as an AND gate, configured to generate the enable signal EN by combining the signals PWM _P and PWM _Tr . For example, this is also shown in Figure 15. Specifically, Figure 15 shows the variation of the digital values S _imp which periodically follows the profile of the base pulse I, e.g. having a sawtooth profile. Moreover, the PWM signal PWM _P is periodically set to high for the time T _{pac_on} and low for the time T _{pac_off} , and the PWM signal PWM _Tr is periodically set to high for the time T _{tr_on} and low for the time T _{tr_off} , wherein the enable signal EN is set to high when the signals PWM _P and PWM _Tr are both high. Thus, as extremely shown in Figure 15, the pulses in the signal EN do not have the same duration because the frequency f _pac is usually not a multiple of the frequency f _tr . Finally, the values S _D are generated by modulating the base-pulse values S _imp with the enable signal EN. However, also in this case, the signal S _imp and the enable signal EN are not synchronized. For example, the PWM signal generator circuits 2228 and 2230 may be implemented with one or more digital counters. For example, a PWM signal generator may be implemented by increasing a count value in response to a clock signal, wherein: - the output of the PWM signal generator circuit is set to high when the count value is between 0 and a first value proportional to the time T _{pac_on} (or T _{tr_on} ); - the output of the PWM signal generator circuit is set to low when the count value is greater than the first value; and - the count value is reset to 0 when the count value reaches a second value proportional to the time T _pac (or T _tr ). For example, the inventor has observed that with a clock frequency of 48 Mhz, the PWM signal generators 2228 and 2230 may be implemented with counters having 24 bits. The base pulse generator circuit 2224 may have different implementation forms, which essentially depend on the fact whether the frequency f _imp may be variable and whether a single or plural base pulse types are required. For example, in various embodiments, the second digital processing circuit 220b should be able to generate (at least) the programs 1, 3 and 6, i.e.: - program 1: saw-tooth base pulse with frequency f _imp = 212.76 Hz, where the duration of the base pulse is T _imp = 4.70 ms, the time T _{pac_on} is set to 206.80 ms (corresponding to the time of 44 base pulses), the pause between the packets is T _{pac_off} = 140.00 ms, the time T _{tr_on} is set to 1387.20 ms (corresponding to the time of 4 packets) and the pause between the trains is T _{tr_off} = 1450 ms; and - program 3: saw-tooth base pulse with frequency f _imp = 212.76 Hz, where the duration of the base pulse is T _imp = 4.70 ms, the time T _{pac_on} is set to 94.00 ms (corresponding to the time of 20 base pulses), the pause between the packets is T _{pac_off} = 55.00 ms, the time T _{tr_on} is set to 596.00 ms (corresponding to the time of 4 packets) and the pause between the trains is T _{tr_off} = 600 ms; - program 6: saw-tooth base pulse with frequency f _imp = 231.48 Hz, where the duration of the base pulse is T _imp = 4.32 ms, the time T _{pac_on} is set to 60.48 ms (corresponding to the time of 14 base pulses), the pause between the packets is T _{pac_off} = 16.00 ms, the time T _{tr_on} is set to 305.92 ms (corresponding to the time of 4 packets) and the pause between the trains is T _{tr_off} = 350 ms; Accordingly, these three programs use a saw-tooth base pulse, but two different frequencies f _imp may be used. As mentioned before, also the modified program 9 may use a saw- tooth base pulse, but with a further frequency. Figure 16 shows in this respect a possible embodiment of the base pulse generator circuit 2224 configured to generate saw-tooth base pulses with settable frequency. Specifically, in the embodiment considered, the base pulse generator circuit 2224 is implemented with a digital counter 2260 configured to: - in response to a clock signal CLK having a given frequency f _CLK , increase a count value by a given increment value INC; - reset the count value when the counter 2224 reaches a given maximum value S _Dmax . Accordingly, a circuit 2262 may determine the number n _CLK required to obtain a the requested frequency f _imp . For example, when receiving at input data indentifying the requested frequency, the circuit 2262 may calculate n _CLK = f _CLK /f _imp . However, the circuit 2262 may also receive directly the number n _CLK , i.e. the data identifying the frequency f _imp of the base pulse I may correspond to the number n _CLK . Next, the circuit 2262 may calculate the increment value INC as a function of maximum value S _Dmax and the number n _CLK , i.e. INC = S _Dmax /n _CLK . Generally, e.g. based on the resolution of the counter 2260, the calculated number n _CLK and/or the increment value INC will not necessarily be an integer number. For example, assuming a clock frequency f _CLK = 48 Mhz, and a requested frequency f _imp = 212.76, n _CLK would correspond to approximately 225,606.32 clock cycles. Moreover, assuming a counter with 24 bit, wherein the maximum value SD _max is set to 16,777,215, the “optimal” increment value INC would be approximately 74.365. For example, when the counter uses the increment value INC = 74 indeed 226,720 clock cycles would be required to reach the maximum value SD _max , thereby resulting in a frequency of 211.715 Hz, and when the counter uses the increment value INC = 75 indeed 223,697 clock cycles would be required to reach the maximum value SD _max , thereby resulting in a frequency of 214.576 Hz. Accordingly, in various embodiments, the circuit 2262 is configured to vary the increment value INC provided to the counter 2260, preferably for each clock cycle, such that the average value of the increment value INC corresponds the optimal increment value INC (with fraction). For example, for this purpose, the circuit 2262 may manage internally an increment value INC’ having a resolution being greater than the resolution of the increment value INC provided to the counter 2260, wherein the value INC’ is calculated according to the previous method by considering a given number of the most significant bits as integer part, wherein the given number corresponds to the number of bits of the signal INC, and the remaining least significant bits are considered as fraction part, e.g. the 16 least significant bits. Accordingly, the increment value INC may be varied such that the increment value INC corresponds in average to the value INC’. In various embodiments, e.g. in order to permit a programmability of the base pulse profile or to support also other base pulse types, the base pulse generator circuit 2224 may also be based on a digital signal generator circuit using Direct Digital Synthesis (DDS). Figure 17 shows a possible embodiment of the base pulse generator circuit 2224 comprising a DDS signal generator 2250. In particular, DDS indicates a method for generating, using digital electronics, an arbitrary periodic waveform starting from a single reference oscillator. Basically, in this case, a look-up table (LUT) 2254 is used, wherein the LUT 2254 has stored the amplitudes A _k for a given number of samples of a standard waveform with a frequency f _s . In various embodiments, the LUT 2254 may also have stored a plurality of standard waveforms, such as a saw-tooth waveform, a square waveform and/or the waveform comprising cusps (Figure 3d). Accordingly, in this case, a type signal P _imp (provided by the circuit 2222) may be used to select one of the standard waveforms. Instead, for effective generation of the base pulse values S _imp at the desired frequency, a counter 2252 is used that represents a phase accumulator, which is incremented by a given increment value INC at each iteration, i.e. in response to a clock signal CLK, where the increment value INC is determined as a function of the ratio between the frequency f _imp of the required base pulse I and the frequency f _s of the standard waveform. For example, similar to Figure 16, a circuit 2258 may be used, which is configured to calculate the increment value INC as a function of the frequencies f _imp and f _s , e.g. INC = f _imp /f _s . Consequently, to determine the amplitude A _k (f _imp ) of a base pulse at the desired frequency f _imp at a given instant k, it is sufficient to use the value of the respective counter 2220, i.e., the phase, as address for the LUT 2254, or the portion of the LUT associated with the waveform profile selected via the signal P _imp . In various embodiments, the amplitude A _k (f _imp ) may refer to a standard amplitude, and a multiplier circuit 2256 may be configured to determine the value S _imp by multiplying the value A _k (f _imp ) with a coefficient a. Generally, the multiplier 2256 is purely optional and the value S _imp may correspond to the value A _k (f _imp ). Such data identifying the coefficient a may be received from the circuit 2222 similar to the timing data. For example, such data identifying the coefficient a may be stored for the treatment programs or received via the first digital processing circuit 220a from the user interface 50 or the communication interface 226a. Thus, also in this case the optimal increment value INC may not be an integer value. Accordingly, also in this case, the circuit 2258 may manage internally an increment value INC’ having a resolution being greater than the resolution of the increment value INC provided to the counter 2260, wherein the value INC’ is calculated according to the previous method by considering a given number of the most significant bits as integer part, wherein the given number corresponds to the number of bits of the signal INC, and the remaining least significant bits are considered as fraction part, e.g. the 16 least significant bits. Accordingly, the increment value INC may be varied, preferably for each clock cycle, such that the increment value INC corresponds in average to the value INC’. For example, assuming a clock frequency of f _CLK = 48 Mhz and standard waveforms being stored for base pulse profiles having f _s = 10 Hz, the LUT would comprise 4,800,000 samples. Generally, instead of storing all these samples, the circuit 2224 may operate with a down-scaled version of the clock signal CLK, i.e. the circuit 2224 may operate with a frequency f’ _CLK , e.g. corresponding to f _CLK /4, f _CLK /8, f _CLK /16, f _CLK /24 or f _CLK /32, etc. For example, in various embodiments, the frequency f’ _CLK is between 100 kHz and 2 MHz. For example, in the following will be assumed that the frequency f’ _CLK corresponds to 375,000 Hz (f _CLK /128), i.e. for f _s = 10 Hz, the LUT would comprise 37,500 samples. Accordingly, in order to generate a base pulse with f _imp = 212.76, the internal increment value INC’ may comprise the bits of the signal INC for the integer part and e.g. 10 bits for the fraction part. Accordingly the internal increment value INC’ would correspond to 21.276, e.g. binary encoded as “10101.0100011010”, which approximately corresponds to 21.27539. Thus, the circuit 2258 may set the increment value INC either to 21 (“10101”) or 22 (“10110”), such that the average value of the increment value INC corresponds to the value INC’. For example, in the embodiment considered, the fractional part “.0100011010” corresponds to “0100011010” / “10000000000” = 282/1024. Accordingly, the circuit 2258 may be configured to apply 282 times the value 22 and 1024-282 = 742 times the value 21, which would result in an average increment value of (282 x 22 + 742 x 21)/1024 = 21.27539. The inventor has observed that this averaging operation implemented by the circuits 2258 and 2262 may introduces a further small dithering operation of the harmonics of the base pulse I, which seems to be useful in order to improve the result of the low frequency treatment programs. Thus, in various embodiments, a first dithering operation may be performed directly during the generation of the base pulse values S _imp by the averaging operation of the increment value INC provided to the signal generator 2250 or 2260. A second dithering operation (which indeed is not casual due to the shifting effect) is then performed by enabling and disabling the base pulse values S _imp according to the timing of the packet P and the train Tr. As describe in the foregoing, a PWM modulation may also be applied to the base pulse I. For example, in the embodiment shown in Figure 16, the counter 2260 may directly compare the count value with a further threshold (being smaller than SDmax), wherein the further threshold is indicative of the duty cycle. Accordingly, when the count value is greater than the further threshold, the counter 2260 may set the value S _imp to zero. Similarly, also in the embodiment shown in Figure 17 the count/phase value provided by the counter 2252 may be compared with a threshold (being smaller than the number of sample stored to the LUT 2254), wherein the further threshold is indicative of the duty cycle. Accordingly, when the count value is greater than the further threshold, a combinational logic circuit (e.g. within the block 2256) may set the value S _imp to zero. However, in Figure 17, the LUT 2254 may already have stored the profile of one or more standard waveforms having already applied a PWM modulation. The inventor has observed that the disclosed digital solution provides surprisingly better treatment results than a complete analog implementation of the block 2240, or a mixed digital/analog solution comprising an analog waveform generator (implementing the operation of the block 2224) and a digital circuit (implementing the operation of the clock 226) configured to selectively connected the output of the analog waveform generator to a power amplifier. Presumably, this results from the fact that the described digital implementation of the circuit 2224 permits to control more precisely the frequency of the base pulses. In fact, the described solutions permit to obtain a precise clock frequency, being not correlated with the frequency of the packets and trains, which ensures that the harmonics do not overlap. Moreover, the additional dithering operation of the averaging operation permits to slightly broaden the harmonics of the base pulses. A further possible reason may reside in the additional control of the current flowing through the antenna 30. Specifically, as described in the foregoing, the values S _D represent the requested values of the current i _out to be provided to the antenna 30. Specifically, as shown in Figure 14, in various embodiments, the value S _D and the sample CS _D indicative of the current provided to the antenna 30 are provided to a digital regulator circuit 2236 comprising an Integral (I) component and a Proportional (P) components. Specifically, the digital regulator circuit 2236 is configured to generate a digital signal D indicative of the duty cycle of the signal DRV as a function of the requested values S _D and the actual value CS _D . Substantially, the regulator circuit 2236 is configured to vary (via the PI regulation) the digital value D such that the value CS _D corresponds to the value S _D , i.e. increases the value D when the value CS _D is smaller than the value S _D and decreases the value D when the value CS _D is greater than the value S _D . Digital/discrete implementations of PI (or PID) regulators are per se well known in the art, e.g. from the respective Wikipedia page (version of April 19, 2020) relating to “PID_controller”, in particular the section “Discrete_implementation”, or document AN21990-13, “ADSP-21990: Implementation of PI Controllers” Analog Devices Inc., December 2001, which are incorporated herein by reference for this purpose. Generally, with such a PI (or PID) regulator, the value S _D represents the set-point and the value CS _D represents the process variable. For example, a PI regulator may perform the following operations for each step k (which may correspond to a single clock cycle or a plurality of clock cycles): - calculate an error value E(k) as a function of the difference between the set-point S _D (k) and the process variable CS _D (k), i.e.: E(k) = S _D (k) - CS _D (k) - calculate, e.g. via an accumulator, an integral value EI(k) indicative of the integral of the error values E(k), e.g.: EI(k) = EI(k-1) + E(k), with EI(0) = 0; - calculate the output D(k) as a function of the proportional component E(k) and the integral component EI(k) by using respective coefficients Kp and Ki, i.e.: D = Kp × E(k) + Ki × EI(k) In the embodiment considered, the value D is provided to a digital PWM generator circuit 2238 configured to generate the drive signal DRV as a function of the signal D. For example, also the PWM signal generator 2238 may be implemented with one or more digital counters. For example, the PWM signal generator 2238 may be implemented by increasing a count value in response to the clock signal CLK, wherein: - the signal DRV at the output of the PWM signal generator 2238 is set to high when the count value is between 0 and a first value proportional to (and preferably corresponding to) the value D; - the output of the PWM signal generator is set to low when the count value is greater than the first value; and - the count value is reset to 0 when the count value reaches a given maximum value. For example, in various embodiments, the counter 2238 has the same number of bits as the signal S _D , e.g. 8 bits, which e.g. permits to obtain a PWM signal DRV with a switching frequency of 48 MHz/256 = 187,500 Hz. Thus, in various embodiments, the digital PI regulator 2236, the digital PWM signal generator 2238, the power/switching stage 24a, the filter 28, the current sensor 228 and the A/D 228b (and possibly the filter 228a) implement a regulated current generator, configured to regulate the output current i _out provided via the terminals 202a and 202b to the requested value S _D . For example, the embodiment shown in Figure 13 essentially implements a buck converter. However, the implementation of the digital PI regulator 2236 and the digital PWM signal generator 2238 within the second digital processing circuit 220b has several advantages compared to the use of a separate regulated current generator. For example, the solution is more cost efficient, because instead of using a digital-to analog (D/A) converter for the signal S _D and a separate regulated current generator, only an A/D converter 228b is required and the control operation of the regulated current generator (usually implemented in a dedicated current control IC) may be implemented by digital processing within the second processing circuit 220b. Moreover, due to the implementation within a FPGA or ASIC, a faster regulation of the current i _out is possible, thereby permitting that the current i _out follows precisely the profile of the values S _D . In fact, such control ICs for regulated current generators usually are for constant current applications, such as for powering LEDs, and thus do not provide a sufficient bandwidth in order to follow a constantly varying profile of current pulses. Moreover, also the inversion of the polarity may be implemented easier. In fact, as described in the foregoing, the power/switching stage (while amplifying the PWM signal DRV) may also invert the polarity of the voltage between the terminals 240a and 240b as a function of a polarity signal POL. For example, as shown in Figure 14, for this purpose, the second digital processing circuit 220b may comprise a further signal generator 2242 configured to generate the polarity signal POL as a function of timing data received from the circuit 2222. Substantially, in various embodiments, the polarity signal corresponds to a PWM signal with 50% duty cycle. For example, the signal generator circuit 2242 may be implemented with a counter, e.g. configured to increase a count value in response to a clock signal, wherein the output of the signal generator 2242 is inverted and the count value is reset to 0 when the count value reaches a threshold value proportional to the inversion period, e.g.120 s. Finally, as shown in Figure 14, in various embodiments the apparatus 20a may also be configured to generate one or more further signals to be applied to other transducers, such as acoustic, light or haptic transducers, in order to further stimulate the patient/target. For example, such a further signal may be generated by implementing a further class D amplifier comprising: - a digital PWM signal generator 2236b configured to generate a PWM signal PWM _A , wherein the duty cycle of the signal PWM _A is proportional to the signal S _D , wherein the digital PWM signal generator 2236b is preferably integrated in the second digital processing circuit 220b; - a power/switching stage 24b configured to generate an amplified PWM signal by amplifying the PWM signal PWM _A ; and - an analog low-pass or band-pass filter 28b configured to generate the further signal by filtering the amplified PWM signal generated by the power/switching stage 24b, wherein the power/switching stage 24b and the filter 28b are preferably external with respect to the second digital processing circuit 220b. For example, in this way may be generated one or more further signals, synchronized with the signal applied to the antenna 30. For example, the further signal may be at least one of: - as shown in Figure 14, an audio signal, which e.g. may be applied to an audio jack, which in turn may be connected to a headphone or speaker 32 configured to receive such an audio signal; - a signal used to drive one or more light sources, such as e.g. LEDs, configured to be arranged in the vicinity of the eyes of the patient, e.g. by mounting the light sources in a headset or glasses; - a signal used to drive a vibration transducers, such as a piezoelectric vibration transducer, e.g. incorporated in a global and/or local antenna 30. Accordingly, in various embodiments, the further signal(s) use the same signal profile S _D (frequencies of base pulses, packets and trains) generated for the antenna(s) 30 (total and/or local applicators). The further signal(s) are supplied in a synchronous mode, e.g. to drive a headphone, LED glasses and piezoelectric Transducers. Accordingly, these one or more additional stimuli may be perceived by receptors of the patient, thereby stimulating given areas in the brain of the patient associated with the respective receptors, such as acoustic receptors (audio), visual receptors (light), and/or proprioceptive and/or nociceptive receptors (vibration). Specifically, e.g. because the transducers are not fast enough or similarly because human eyes would be unable to perceive the variation of saw-tooth base pulses having a frequency around of 200 Hz, in various embodiments, one or more further signals may be generated by filtering the samples S _D . For example, in various embodiments, a binarized version of the samples S _D is used. For example, as described in the foregoing, in various embodiments, the base pulses I uses a PWM modulation, e.g. of 50%. Accordingly, in this case, the digital PWM signal generator 2236b may be configured to generate the PWM signal PWM _A by setting the signal PWM _A to high when the value S _D is greater than a first threshold, e.g. zero, and to low when the value S _D is smaller or equal to the first threshold, e.g. zero. For example, this simplifies also the generation of further signal, because the low-pass filter 28b may be omitted. Moreover, for the above mentioned transducers, the value of the polarity signal POL is not relevant. Accordingly, in various embodiments, one or more further signals (such as the audio signal and the signal used to drive one or more LEDs, and optionally the signal used to drive a vibration transducers) have a square waveform, but follow the timing of the base pulses (T _imp , T _{imp_on} , T _pac , T _tr ). For example, test have demonstrated that, while a human brain is typically able to elaborate images with up to 30 fps, indeed a human eye is able to perceive frequencies up to (approximately) 250 Hz. Accordingly, various embodiments relate to a system for therapeutic treatments with electromagnetic waves. The system comprises an antenna 30 and an apparatus 20a configured to generate a supply current i _out for the antenna 30 in order to generate the electromagnetic waves. In various embodiments, the apparatus 20a comprises a digital processing circuit 220b. According to the first aspect, the digital processing circuit 220b is configured to generate a sequence of values S _D corresponding to the signal S shown in Figures 8 and 15. Specifically, in various embodiments, in order to generate the sequence of values S _D , the digital processing circuit 220b is configured to generate via the circuit or module 2224 a sequence of digital values S _imp of a periodic base pulse I having a given frequency f _imp . The digital processing circuit 220b is also configured to generate via the circuit or module 2228 a PWM signal PWM _P , wherein the PWM signal PWM _P is set, for each switching cycle T _pac , to a respective first logic level (e.g. high) for a packet switch-on period T _{pac_on} and to a respective second logic level (e.g. low) for a packet switch-off period T _{pac_off} , and via the circuit or module 2230 a PWM signal PWM _Tr , wherein the PWM signal PWM _Tr is set, for each switching cycle T _tr , to a respective first logic level (e.g. high) for a train switch-on period T _{tr_on} and to a respective second logic level (e.g. low) for a train switch-off period T _{tr_off} . Moreover, the digital processing circuit 220b is configured to generate via the circuit or module 2232 an enable signal EN, wherein the enable signal EN is set to a respective first logic level (e.g. high) when the PWM signal PWM _P has the respective first logic level (e.g. high) and the PWM signal PWM _Tr has the respective first logic level (e.g. high), and to a respective second logic level (e.g. low) when the PWM signal PWM _P has the respective second logic level (e.g. low) or the PWM signal PWM _Tr has the respective second logic level (e.g. low). Specifically, in this case, the digital processing circuit 220b is configured to generate via the circuit or module 2234 the digital value S _D , wherein the digital value S _D is set to the digital value S _imp when the enable signal EN has the respective first logic level (e.g. high) and to zero when the enable signal EN has the respective second logic level (e.g. low). Generally, these values S _D could be provided to the antenna via an A/D converter. Conversely, according to a second aspect, the digital processing circuit 220b is configured to generate a PWM signal DRV having a given duty cycle, wherein the PWM signal DRV is set, for each switching cycle T _SW , to high for a switch-on period T _ON and to low for a switch-off period T _OFF . In this case, the apparatus 20a comprises also a switching stage 24a configured to generate an amplified PWM signal V ₂₄₀ by amplifying the PWM signal DRV and an analog low- pass or band-pass filter 28 configured to generate the supply current i _out by filtering the amplified PWM signal V ₂₄₀ . Accordingly, in this case, the digital processing circuit 220b may be configured to generate the PWM signal DRV as a function of the digital value S _D . For example, in various embodiments, the apparatus comprises also a current sensor 228 configured to provide a digital sample CS _D indicative of the amplitude of the supply current i _out . In this case, the digital processing circuit 220b may be configured to generate via the circuit or module 2238 the PWM signal DRV as a function of a digital value D indicative of a duty cycle of the PWM signal DRV. Moreover, the digital processing circuit 220b may be configured to vary the digital value D via a discrete proportional-derivative regulation configured to regulate the difference between the digital value S _D and the digital sample CS _D to zero. Of course, without prejudice to the principle of the invention, the details of construction and the embodiments may vary widely with respect to what has been described and illustrated herein purely by way of example, without thereby departing from the scope of the present invention, as defined by the ensuing claims.