FIELD OF DISCLOSURE

[0001] The present disclosure relates generally to electronic devices. More specifically, the present disclosure relates to systems and methods for determining in- phase and quadrature imbalance.

BACKGROUND

[0002] Some electronic devices (e.g., circuits, circuitry, cellular phones, smart phones, etc.) process electronic signals. For example, a transceiver may process signals for wireless communication. In some applications, processed signals may need to meet stringent requirements. For example, wireless communication signals may need to be processed with a high level of accuracy to ensure high quality transmission and/or reception.

[0003] Some circuit components used to process signals may introduce errors into the signals being processed. For example, some circuit components may introduce phase and/or gain errors. In some approaches, additional circuitry may be added to reduce errors. Implementing additional circuitry may increase the size of circuitry (e.g., die area) and/or may decrease circuitry efficiency. As can be observed from this discussion, systems and methods that improve signal processing and/or circuit implementation may be beneficial.

SUMMARY

[0004] An apparatus is described. The apparatus includes a main circuitry path configured to receive a wireless communication signal. The apparatus also includes a secondary circuitry path coupled to the main circuitry path. The secondary circuitry path includes a first mixer, a second mixer, and phase rotation circuitry. The phase rotation circuitry is configured to introduce a known phase shift to the secondary circuitry path from within the secondary circuitry path as part of determining in-phase and quadrature (IQ) imbalance error metrics related to the first mixer and the second mixer. The first mixer may be used for down-conversion and the second mixer may be used for up- conversion.

[0005] The secondary circuitry path may be coupled in parallel to the main circuitry path and may be non-overlapping with the main circuitry path. The secondary path may be a blind interference cancellation (BIC) path. The BIC path may be configured to determine a blocking signal in the received wireless communication signal.

[0006] The phase rotation circuitry may be a cancellation gain and phase matching circuit reused to introduce the known phase shift as part of a calibration procedure. The calibration procedure may be performed after a calibration of a receive mixer and a calibration of a transmit mixer.

[0007] Determining the IQ imbalance error metrics may include sending a first calibration tone through the secondary circuitry path and may include determining a first set of measurements corresponding to the first calibration tone. Determining the IQ imbalance error metrics may also include introducing the known phase shift to the secondary circuitry path and may include sending a second calibration tone through the secondary circuitry path. Determining the IQ imbalance error metrics may further include determining a second set of measurements corresponding to the second calibration tone and may include using the first set of measurements and the second set of measurements to determine the IQ imbalance error metrics.

[0008] A method is also described. The method includes introducing, from phase rotation circuitry within a secondary circuitry path, a known phase shift to the secondary circuitry path. The secondary circuitry path is coupled to a main circuitry path. The method also includes determining in-phase and quadrature (IQ) imbalance error metrics related to a first mixer and a second mixer in the secondary circuitry path. The method further includes compensating the first mixer and the second mixer based on the IQ imbalance error metrics.

[0009] An apparatus is also described. The apparatus includes phase rotation means for introducing, within a secondary path means, a known phase shift to the secondary path means. The secondary path means is coupled to a main path means. The apparatus also includes means for determining in-phase and quadrature (IQ) imbalance error metrics related to a first mixing means and a second mixing means in the secondary path means. The apparatus further includes means for compensating the first mixing means and the second mixing means based on the IQ imbalance error metrics. [0010] A computer-program product is also described. The computer-program product includes a non-transitory computer-readable medium with instructions. The instructions include code for causing an apparatus to introduce, from phase rotation circuitry within a secondary circuitry path, a known phase shift to the secondary circuitry path. The secondary circuitry path is coupled to a main circuitry path. The computer-program product also includes code for causing the apparatus to determine in- phase and quadrature (IQ) imbalance error metrics related to a first mixer and a second mixer in the secondary circuitry path. The computer-program product further includes code for causing the apparatus to compensate the first mixer and the second mixer based on the IQ imbalance error metrics.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a block diagram illustrating an example of an apparatus in which systems and methods for determining in-phase and quadrature (IQ) imbalance may be implemented;

[0012] Figure 2 is a flow diagram illustrating one configuration of a method for determining IQ imbalance;

[0013] Figure 3 is a graph illustrating examples of blind interference cancellation (BIC) performance based on IQ imbalance;

[0014] Figure 4 is a flow diagram illustrating a more specific configuration of a method for determining IQ imbalance;

[0015] Figure 5 is a block diagram illustrating a more specific example of an apparatus in which systems and methods for determining IQ imbalance may be implemented;

[0016] Figure 6 is a graph illustrating an example of null impact with different IQ imbalance;

[0017] Figure 7 is a block diagram illustrating another more specific example of an apparatus in which systems and methods for determining IQ imbalance may be implemented;

[0018] Figure 8 is a block diagram illustrating another more specific example of an apparatus in which systems and methods for determining IQ imbalance may be implemented; [0019] Figure 9 is a flow diagram illustrating a more specific configuration of a method for determining IQ imbalance;

[0020] Figure 10 illustrates certain components that may be included within an electronic device configured to implement various configurations of the systems and methods disclosed herein; and

[0021] Figure 11 is a block diagram illustrating an example of phase rotation circuitry that may be implemented in accordance with some configurations of the systems and methods disclosed herein.

DETAILED DESCRIPTION

[0022] The systems and methods disclosed herein may relate to determining in- phase and quadrature (IQ) imbalance (e.g., mismatch). Some configurations of the systems and methods disclosed herein may relate to blind interference cancellation (BIC) and IQ mismatch determination. Some configurations of the systems and methods disclosed herein may enable separate estimation of the IQ imbalance for multiple mixers (e.g., a first mixer and a second mixer). This may allow a deterministic approach to finding the IQ imbalance (as opposed to a search algorithm, for example).

[0023] Blind interference cancellation (BIC) may be utilized to ameliorate (e.g., to solve) the problem of concurrently transmitting and receiving signals. For example, a transmit (Tx) signal may block, interfere with, and/or mask a receive (Rx) signal. For instance, transmitting a wireless local area network (WLAN) signal (e.g., an Institute of Electrical and Electronics Engineers (IEEE) 802.11 (Wi-Fi) signal) while concurrently attempting to receive a wireless personal area network (WPAN) signal (e.g., a Bluetooth (BT) signal) may create a blocking signal. A blocking signal may make it difficult to concurrently receive a signal. This may also occur when attempting to receive WLAN Rx signals while concurrent transmitting BT Tx signals. This problem may be ameliorated by reducing (e.g., cancelling) the blocking signal. To reduce or cancel the blocking signal, a secondary path (e.g., a BIC path) may be utilized. The secondary path may down-convert a signal (e.g., a received signal) to baseband, may apply a phase rotation to align the signal with a signal on the main path, may apply a filter (e.g., a high-pass filter (HPF)) to remove a target signal, and/or may up-convert the signal. The secondary path (e.g., BIC path) may provide a signal that contains (e.g., only contains) the blocking signal. The blocking signal may then be reduced (e.g., cancelled out). It should be noted that the term "cancel" may not mean perfect cancellation in some cases. For example, "cancelling" a blocking signal may mean significantly reducing the blocking signal.

[0024] In some configurations of blind interference cancellation, two mixers may be implemented and/or utilized in the BIC path. These two mixers may be used to up- convert and down-convert a signal (e.g., a received signal). The two mixers may exhibit an IQ imbalance (e.g., mismatch). The IQ imbalance may significantly affect the BIC algorithm cancellation performance. [0025] A problem that arises is how to calibrate the two mixers independently, since their IQ mismatch may be unknown. For example, the IQ mismatch can change for each device. Accordingly, calibration may be performed each time a device is activated (e.g., booted up). The calibration may need to be relatively precise with good performance, since the IQ mismatch may need to be reduced and/or removed.

[0026] In some configurations, the secondary path (e.g., BIC path) may not need (or utilize) a reference signal between wireless communication subsystems. For example, a transmit circuitry path may not provide a reference signal (via an analog or digital wired connection, for example) to the receive circuitry path and/or secondary path for cancellation. Accordingly, the secondary circuitry path (e.g., BIC path) may be utilized to reduce a blocking signal (received wirelessly from the transmit circuitry or antenna) without a reference signal in some configurations. Additionally or alternatively, some configurations of the systems and methods disclosed herein may be less susceptible to coupling changes. For example, a coupling path may only be between an input of a low- noise amplifier (LNA) and a subtraction block in some implementations. Accordingly, the group delay may be mostly inserted by a filter (e.g., high-pass filter) and may not change with user interaction in some implementations.

[0027] Various configurations are now described with reference to the Figures, where like reference numbers may indicate functionally similar elements. The systems and methods as generally described and illustrated in the Figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following more detailed description of several configurations, as represented in the Figures, is not intended to limit scope, as claimed, but is merely representative of the systems and methods.

[0028] Figure 1 is a block diagram illustrating an example of an apparatus 101 in which systems and methods for determining in-phase and quadrature (IQ) imbalance may be implemented. The apparatus 101 may be implemented in hardware (e.g., circuitry, an integrated circuit, an application-specific integrated circuit (ASIC), etc.) or a combination of hardware and software (e.g., a processor with instructions).

[0029] It should be noted that arrows and/or lines may indicate couplings in one or more of the block diagrams (e.g., Figures 1, 5, 7-8, and/or 10-11) described herein. The term "couple" and variations thereof may denote a direct connection or an indirect connection. For example, a first component may be directly connected (without one or more intervening components, for instance) or indirectly connected (with one or more intervening components, for instance) to a second component.

[0030] The apparatus 101 may include a main circuitry path 102, a secondary circuitry path 104, a calibration controller 112, and/or antenna 114. The main circuitry path 102 may be configured to receive a wireless communication signal 116. For example, the main circuitry path 102 may be coupled to one or more antennas 114. The antenna(s) 114 may provide a wireless communication signal to the main circuitry path 102. The wireless communication signal 116 or one or more portions of the wireless communication signal 116 may include information (e.g., data, audio signals, voice call signals, video signals, Internet data, etc.).

[0031] In some configurations, the main circuitry path 102 may include one or more components for receiving the wireless communication signal 116. Examples of components that may be included main circuitry path 102 may include one or more amplifiers (e.g., low-noise amplifier(s), transconductance amplifier(s) (e.g., GM amplifier(s)), etc.), mixer(s), filter(s), anti-aliasing filter(s) (AAF(s)), analog-to-digital converter(s) (ADC(s)), summer(s), subtractor(s), etc. In some configurations, the main circuitry path 102 may produce a received signal 118. The received signal 118 may be signal (e.g., a digital signal) resulting from the processing performed by the component(s) of the main circuitry path 102. In some configurations, the main circuitry path 102 may be and/or may include a receive chain. In some configurations, the main circuitry path 102 may be utilized to receive different signals from different radio access technologies (RATs) (e.g., Wi-Fi and Bluetooth, etc.). For example, one or more of the amplifiers included in the main circuitry path 102 may be shared to amplify signals from different RATs.

[0032] The secondary circuitry path 104 may include a first mixer 106, a second mixer 110, and phase rotation circuitry 108. The secondary circuitry path 104 may be coupled to the main circuitry path 102. In some configurations, the secondary circuitry path 104 may be coupled in parallel with the main circuitry path 102. The secondary circuitry path 104 may not overlap (e.g., may be non-overlapping) with the main circuitry path 102 in some configurations. For example, the secondary circuitry path 104 may be coupled to the main circuitry path 102 and may not include any component that is also included in the main circuitry path 102 (e.g., may not include one or more mixers in common). The first mixer 106 may be used for down-conversion in some implementations. Additionally or alternatively, the second mixer 110 may be used for up-conversion in some implementations.

[0033] In some configurations, the secondary circuitry path 104 may be a blind interference cancellation (BIC) path. For example, the secondary circuitry path 104 (e.g., BIC path) may be configured to determine a blocking signal in the wireless communication signal 116. For instance, the wireless communication signal 116 may include two or more signals. One or more of the signals may be target receive signals and one or more of the signals may be blocking signals. In some configurations, a blocking signal may be a signal transmitted from the apparatus 101 that is received as part of the wireless communication signal 116. For example, a blocking signal may be a transmitted WLAN signal (from another antenna of the apparatus 101, for instance) that is received by the antenna 114 as part of the wireless communication signal 116. An example of a target receive signal may be a BT signal transmitted from a remote device. In some cases, the blocking signal may have a larger amplitude than the target receive signal. Accordingly, the blocking signal(s) may block, interfere with, and/or mask the target receive signal(s). It should be noted that although the BIC path is described as an example of the secondary circuitry path 104, the systems and methods disclosed herein may be implemented in other kinds of circuitry that include two or more mixers.

[0034] In some configurations, the secondary circuitry path 104 (e.g., a BIC path) may determine a blocking signal as follows. The first mixer 106 may down-convert the wireless communication signal 116. For example, the first mixer 106 may shift (e.g., lower) the wireless communication signal 116 in frequency. For instance, the first mixer 106 may convert the wireless communication signal 116 to baseband.

[0035] The phase rotation circuitry 108 may rotate the phase of the signal (e.g., the down-converted wireless communication signal, baseband wireless communication signal, etc.). For example, the phase rotation circuitry 108 may rotate the phase of the signal to match the phase of a signal going through the main circuitry path 102 (e.g., a signal based on the wireless communication signal 116). For instance, one objective of the phase rotation circuitry 108 may be to match the phase of signals (from the wireless communication signal 116) on the main circuitry path 102 and the secondary circuitry path 104. In some configurations, the phase rotation circuitry 108 may additionally or alternatively adjust the gain of the signal to match the gain of a signal going through the main circuitry path 102 (e.g., a signal based on the wireless communication signal 116). The phase rotation circuitry 108 may be a cancellation gain and phase matching circuit (for performing BIC, for example) in some implementations.

[0036] In some configurations, the secondary circuitry path 104 may filter one or more target receive signals from the signal (e.g., from the rotated baseband wireless communication signal). For example, the secondary circuitry path 104 may include one or more filters for filtering one or more target receive signals. In some implementations, the secondary circuitry path 104 may include a high-pass filter (HPF). The high-pass filter may filter (e.g., reduce and/or remove) one or more lower frequency signals. For example, the high-pass filter may filter a BT signal that is near 0 frequency (e.g., direct current (DC)) and may pass a WLAN signal that is at a higher frequency. The filtered signal may include (e.g., only include) the blocking signal(s).

[0037] The second mixer 110 may up-convert the signal. For example, the second mixer 110 may shift (e.g., raise) the signal (e.g., the down-converted, phase rotated, and/or filtered signal) in frequency. For instance, the second mixer 110 may convert the filtered and rotated baseband signal to a radio frequency (RF) signal (and/or carrier frequency signal). In some approaches, the second mixer 110 may convert (e.g., up- convert) the signal back to the original frequency of the wireless communication signal 116. The secondary circuitry path 104 may output (e.g., may provide to the main circuitry path 102) the blocking signal(s) (at the original frequency of the wireless communication signal 116, for example).

[0038] The main circuitry path 102 may reduce and/or remove (e.g., cancel) the blocking signal(s) from the wireless communication signal 116. For example, the main circuitry path 102 may subtract the blocking signal(s) from the wireless communication signal 116. Accordingly, the target receive signal(s) may remain after reducing (e.g., removing, cancelling, etc.) the blocking signal(s) from the wireless communication signal 116.

[0039] The first mixer 106 may exhibit an in-phase and quadrature (IQ) imbalance (e.g., mismatch). Additionally or alternatively, the second mixer 110 may exhibit an IQ imbalance (e.g., mismatch). For example, the first mixer 106 and/or the second mixer 110 may distort signals during processing. In particular, the first mixer 106 and/or the second mixer 110 may have non- uniform gain characteristics and/or non- ideal phase rotation characteristics. [0040] The apparatus 101 may conduct one or more calibration procedures in order to compensate for the IQ imbalance(s) of the first mixer 106 and/or the second mixer 110. For example, the phase rotation circuitry 108 may be configured to introduce a known phase shift to the secondary circuitry path 104 from within the secondary circuitry path 104 as part of determining IQ imbalance error metrics related to the first mixer 106 and to the second mixer 110. Examples of IQ imbalance error metrics may include gain errors (e.g., ε) and phase errors (e.g., Θ). In some approaches, the calibration of the first mixer 106 and/or the second mixer 110 may be performed after calibration of a receive mixer (in the main circuitry path 102, for example) and/or after calibration of a transmit mixer (in a transmit chain of the apparatus 101, for example).

[0041] In some configurations, the calibration controller 112 may conduct one or more calibration procedures and/or one or more operations for the calibration procedure(s). The calibration controller 112 may be an ASIC, a general purpose processor, a special purpose processor, etc., in some configurations. The calibration controller 112 may be coupled to the secondary circuitry path 104 and/or to the main circuitry path 102. For example, the calibration controller 112 may provide one or more signals to, may receive one or more signals from, and/or may take one or more measurements from the secondary circuitry path 104 and/or the main circuitry path 102. For example, the calibration controller 112 may supply one or more signals (e.g., tone signals, sinusoidal waves, etc.). Additionally or alternatively, the calibration controller 112 may provide one or more control signals (e.g., signal(s) to cause the phase rotation circuitry 108 to apply a phase shift or no phase shift, signal(s) to set mixer frequencies, and/or signal(s) to disable rotation in the main circuitry path 102 and/or the secondary circuitry path 104, etc.). Additionally or alternatively, the calibration controller 112 may receive one or more signals and/or take measurements (e.g., take IQ imbalance or mismatch measurements, measure local oscillator leakage, etc.). It should be noted that the first mixer 106, the second mixer 110, and/or one or more additional mixers (e.g., receive mixer, transmit mixer, etc.) may be coupled to one or more local oscillators (LOs). A local oscillator may supply a signal for mixing (e.g., shifting) one or more signals in frequency.

[0042] The apparatus 101 (e.g., calibration controller 112) may determine IQ imbalance metrics for the first mixer 106 and/or the second mixer 110. For example, the apparatus 101 (e.g., calibration controller 112) may send a first calibration tone through the secondary circuitry path 104. The apparatus 101 (e.g., calibration controller 112) may determine a first set of measurements (e.g., IQ imbalance measurements, Measl, Meas2, etc.) corresponding to the first calibration tone. The first set of measurements may be taken without a phase shift being applied (or with a phase shift, for example).

[0043] The apparatus 101 (e.g., the phase rotation circuitry 108) may introduce a known phase shift to the secondary circuitry path 104. The apparatus 101 (e.g., calibration controller 112) may send a second calibration tone through the secondary circuitry path 104. The apparatus 101 (e.g., calibration controller 112) may determine a second set of measurements (e.g., IQ imbalance measurements, Meas3, Meas4, etc.). The apparatus 101 (e.g., calibration controller 112) may use the first set of measurements and the second set of measurements to determine the IQ imbalance (e.g., mismatch) metrics.

[0044] In some configurations, the IQ imbalance (e.g., mismatch) may be reduced (e.g., corrected) by the phase rotation circuitry 108. For example, the reduction or correction of the IQ imbalance may be applied in a BIC rotation block (applied after the calibration, for instance). In some approaches, the apparatus 101 may select (e.g., the calibration controller 112 may select) and apply (e.g., the phase rotation circuitry 108 may apply) gains that compensate for the IQ imbalance indicated by the IQ imbalance metrics. In some implementations, the phase rotation circuitry 108 (e.g., BIC rotation block) may contain four different gains that are controlled digitally (e.g., from the calibration controller 112). This may allow applying the correction (in gain and/or phase, for instance) so that the signal (after passing through the second mixer 110, for example) has reduced (e.g., corrected) IQ imbalance. Figure 11 illustrates an example of gains applied by the phase rotation circuitry 108 to reduce IQ imbalance. It should be noted that not all IQ imbalance (e.g., mismatch) may be removed in some cases. A gain mismatch of 1 degree and 3% may achieve greater than -30 dB of attenuation for blind interference cancellation in some implementations. Figure 3 illustrates examples of attenuation in accordance with some configurations of the systems and methods disclosed herein.

[0045] As described above, the phase rotation circuitry 108 may be a cancellation gain and phase matching circuit in some configurations. The cancellation gain and phase matching circuit may be reused to introduce the known phase shift as part of a calibration procedure. This may reduce circuit size (e.g., die area) and/or may increase efficiency. For example, some approaches to calibrating mixers may include and/or use an additional and/or separate circuit for introducing a phase shift. Instead of utilizing additional and/or separate circuitry outside of the secondary circuitry path 104, some configurations of the systems and methods disclosed herein may utilize the phase rotation circuitry 108 for multiple functions. For example, the phase rotation circuitry 108 may be utilized to introduce the phase shift in a calibration procedure and may be utilized to perform cancellation gain and phase matching. In this way, the phase shift functionality may be consolidated with the cancellation and phase matching functionality into one circuit in the secondary circuitry path 104.

[0046] In some configurations, the apparatus 101 may be, or may be part of, an electronic device. For instance, the apparatus 101 may be a smart phone or may be included in a smart phone. Examples of electronic devices that may include the apparatus 101 may include wireless communication devices, cameras, cellular phones, smart phones, computers (e.g., desktop computers, laptop computers, servers, etc.), tablet devices, media players, televisions, vehicles, automobiles, virtual reality devices (e.g., headsets), augmented reality devices (e.g., headsets), mixed reality devices (e.g., headsets), robots, aircraft, drones, unmanned aerial vehicles (UAVs), smart appliances, healthcare equipment, gaming consoles, personal digital assistants (PDAs), set-top boxes, appliances, etc.

[0047] Figure 2 is a flow diagram illustrating one configuration of a method 200 for determining in-phase and quadrature (IQ) imbalance. The method 200 may be performed by an apparatus (e.g., the apparatus 101 described in connection with Figure 1).

[0048] The apparatus 101 may introduce 202, from phase rotation circuitry within a secondary circuitry path, a known phase shift to the secondary circuitry path. This may be accomplished as described in connection with Figure 1. For example, the apparatus 101 (e.g., phase rotation circuitry 108) may introduce 202 a known phase shift (e.g., 45° or another value) to the secondary circuitry path 104. In some configurations, the phase rotation circuitry may receive a signal from a calibration controller that causes the phase rotation circuitry to introduce the phase shift.

[0049] The apparatus 101 may determine 204 (e.g., calculate) IQ imbalance error metrics related to a first mixer and a second mixer in the secondary circuitry path. This may be accomplished as described in connection with Figure 1. For example, the apparatus 101 (e.g., calibration controller 112) may calculate IQ imbalance error metrics (e.g., ει, 62, θ\, 6¾ for the first mixer and the second mixer.

[0050] The apparatus 101 may compensate 206 the first mixer and the second mixer based on the IQ imbalance error metrics. This may be accomplished as described in connection with one or more of Figures 1 and 11. For example, the apparatus 101 may select one or more gains and/or apply one or more gains to the phase rotation circuitry 108 that compensate for the IQ imbalance indicated by the IQ imbalance error metrics. Compensating 206 the first mixer and the second mixer may reduce (e.g., remove) the effect of the IQ imbalance exhibited by the first mixer and/or the second mixer.

[0051] In some configurations, the apparatus 101 (e.g., an electronic device, wireless communication device, etc.) may concurrently transmit a first signal (e.g., wireless local area network (WLAN) signal, Wi-Fi signal, Bluetooth signal, etc.) and receive a second signal (e.g., a personal area network (PAN) signal, Bluetooth signal, Wi-Fi signal, etc.). For example, at least part of the first signal transmission may overlap in time with at least part of the second signal reception. In some configurations, the first signal and the second signal may occupy similar or overlapping frequency spectrum (e.g., a 2.4 gigahertz (GHz) band). Some configurations of the systems and methods disclosed herein may utilize a calibration procedure (e.g., determine and/or compensate for IQ imbalance or mismatch) in order to allow transmitting a first signal while concurrently receiving a second signal.

[0052] Figure 3 is a graph 324 illustrating examples of blind interference cancellation (BIC) performance based on IQ imbalance (e.g., mismatch). The graph 324 is illustrated in attenuation 320 (in decibels (dB)) over phase 322 (in degrees). For example, Figure 3 illustrates one example of a requirement for IQ imbalance. The second mixer gain mismatch and phase mismatch may be fixed in the graph 324. In Figure 3, each of the plot lines represents a sweep of different first mixer gain mismatch, where the horizontal axis represents the first mixer phase mismatch.

[0053] It should be noted that although the IQ imbalance appears asymmetric, the IQ imbalance (e.g., mismatch, residual image, etc.) itself is symmetric for positive and negative phases. This may be true for some receiver chains. In some cases, however, the mismatch may be applied on the BIC path. Then, the value may be subtracted.

[0054] Figure 4 is a flow diagram illustrating a more specific configuration of a method 400 for determining in-phase and quadrature (IQ) imbalance. The method 400 may be performed by an apparatus (e.g., the apparatus 101 described in connection with Figure 1).

[0055] The apparatus 101 may send 402 a first calibration tone through the secondary circuitry path. This may be accomplished as described in connection with Figure 1. For example, the apparatus 101 (e.g., calibration controller 112) may send 402 a 1 megahertz (MHz) sinusoidal tone (or a tone with a different frequency) through the secondary circuitry path.

[0056] The apparatus 101 may determine 404 a first set of measurements corresponding to the first calibration tone. This may be accomplished as described in connection with Figure 1. For example, the apparatus 101 (e.g., calibration controller 112) may take two measurements (e.g., Measl and Meas2) from the secondary circuitry path. In some approaches, no phase shift (e.g., 0° phase shift) may be utilized to take the measurements corresponding to the first calibration tone. In some configurations, this may be accomplished in accordance with Equations (8)-(9).

[0057] The apparatus 101 may introduce 406 a known phase shift to the secondary circuitry path. This may be accomplished as described in connection with one or more of Figures 1 and 2. For example, the apparatus 101 (e.g., phase rotation circuitry 108) may introduce 406 a known phase shift (e.g., 45° or another value) to the secondary circuitry path. In some configurations, this may be accomplished in accordance with Equation (10).

[0058] The apparatus 101 may send 408 a second calibration tone through the secondary circuitry path. This may be accomplished as described in connection with Figure 1. For example, the apparatus 101 (e.g., calibration controller 112) may send 408 a 1 megahertz (MHz) sinusoidal tone (or a tone with a different frequency) through the secondary circuitry path.

[0059] The apparatus 101 may determine 410 a second set of measurements corresponding to the second calibration tone. This may be accomplished as described in connection with one or more of Figures 1 and 2. For example, the apparatus 101 (e.g., calibration controller 112) may take two measurements (e.g., Meas3 and Meas4) from the secondary circuitry path. In some configurations, this may be accomplished in accordance with Equations (11)— (12).

[0060] The apparatus 101 may use 412 the first set of measurements and the second set of measurements to determine IQ imbalance error metrics. This may be accomplished as described in connection with Figure 1. For example, the apparatus 101 (e.g., calibration controller 112) may calculate IQ imbalance error metrics (e.g., ει, ¾, θ\ , 6¾ for the first mixer and the second mixer based on the first set of measurements

(e.g., Measl and Meas2) and the second set of measurements (e.g., Meas3 and Meas4). In some configurations, this may be accomplished in accordance with Equation (13).

[0061] Figure 5 is a block diagram illustrating a more specific example of an apparatus 501 in which systems and methods for determining in-phase and quadrature (IQ) imbalance may be implemented. The apparatus 501 may be implemented in hardware (e.g., circuitry, an integrated circuit, an application-specific integrated circuit (ASIC), etc.) or a combination of hardware and software (e.g., a processor with instructions). The apparatus 501 described in connection with Figure 5 may be an example of the apparatus 101 described in connection with Figure 1.

[0062] The apparatus 501 may include a main circuitry path 502, a BIC path 504, a calibration controller 512, and/or antenna 514. The main circuitry path 502 may be configured to receive a wireless communication signal 516. For example, the main circuitry path 502 may be coupled to one or more antennas 514. The antenna(s) 514 may provide a wireless communication signal to the main circuitry path 502. In some configurations, the main circuitry path 502 may include one or more components for receiving the wireless communication signal 516. In the example given in Figure 5, the main circuitry path 502 includes a first stage LNA 530, a subtracter 532, a second stage LNA 534, a receive mixer 536, an analog filter 538, an analog-to-digital converter (ADC) 540. In some configurations, the main circuitry path 502 may produce a received signal 518. The received signal 518 may be signal (e.g., a digital signal) resulting from the processing performed by the component(s) of the main circuitry path 502. In some configurations, the main circuitry path 502 may be and/or may include a receive chain.

[0063] The main circuitry path 502 may receive the wireless communication signal 516 from the antenna(s) 514. The wireless communication signal 516 may include one or more target receive signals and one or more blocking signals. The first stage LNA 530 may amplify the wireless communication signal 516. The amplified wireless communication signal may be provided to the subtractor 532.

[0064] The subtractor 532 may subtract one or more blocking signals (provided by the BIC path 504) from the amplified wireless communication signal. This may reduce (e.g., remove, cancel, etc.) the one or more blocking signals. Accordingly, the output of the subtracter 532 (e.g., one or more target receive signals, a subtracted signal, etc.) may substantially include only the one or more target receive signals.

[0065] The output of the subtracter 532 may be provided to the second stage LNA 534. The second stage LNA 534 may amplify the one or more target receive signals. The amplified target receive signal(s) may be provided to the receive mixer 536.

[0066] The receive mixer 536 may shift (e.g., down-convert) the amplified target receive signal(s) in frequency. For example, the receive mixer 536 may shift (e.g., down-convert) the amplified target receive signal(s) to baseband. The baseband target receive signal(s) may be provided to the analog filter 538.

[0067] The analog filter 538 may filter the baseband target receive signal(s). For example, the analog filter 538 may reduce noise in the baseband target receive signal(s). The filtered baseband target receive signal(s) may be provided to the ADC 540.

[0068] The ADC 540 may convert the filtered baseband target receive signal(s) to produce the received signal(s) 518. For example, the ADC 540 may convert the filtered baseband target receive signal(s) from analog signal(s) to digital signal(s). The resulting digital signal(s) may be the one or more received signal(s) 518. In some configurations, the received signal(s) 518 may be provided for further processing (e.g., decoding, descrambling, error detection, error correction, de-interleaving, etc.). For example, the apparatus 501 (or an electronic device that includes the apparatus 501) may perform further processing on the received signal(s) 518.

[0069] The BIC path 504 described in connection with Figure 5 may be an example of the secondary circuitry path 104 described in connection with Figure 1. The BIC path 504 may be configured to determine a blocking signal in the wireless communication signal 516. The BIC path 504 may include a first mixer 506, a second mixer 510, phase rotation circuitry 508, a low-pass filter (LPF) 526, and/or a high-pass filter (HPF) 528. The BIC path 504 may be coupled to the main circuitry path 502 (e.g., coupled in parallel and/or non-overlapping, etc.). The BIC path 504 may be referred to as a BIC unit in some implementations.

[0070] The first mixer 506 may down-convert the wireless communication signal 516. For example, the first mixer 506 may shift (e.g., lower) the wireless communication signal 516 in frequency. For instance, the first mixer 506 may convert the wireless communication signal 516 to baseband. The baseband wireless communication signal may be provided to the LPF 526. [0071] The LPF 526 may filter the baseband wireless communication signal. For example, the LPF 526 may filter noise from the baseband wireless communication signal in a frequency range above the frequency range(s) of the one or more target receive signals and/or the of the one or more blocking signals. The low-pass filtered baseband wireless communication signal may be provided to the phase rotation circuitry 508.

[0072] The phase rotation circuitry 508 may rotate the phase of the low-pass filtered baseband wireless communication signal. For example, the phase rotation circuitry 508 may rotate the phase of the low-pass filtered baseband wireless communication signal to match the phase of the wireless communication signal 516. In some configurations, the phase rotation circuitry 508 may additionally or alternatively adjust the gain of the low- pass filtered baseband wireless communication signal to match the gain of the wireless communication signal 516. The phase rotation circuitry 508 may be a cancellation gain and phase matching circuit (for performing BIC, for example) in some implementations. The phase rotation circuitry 508 may provide the phase-rotated signal to the HPF 528.

[0073] The HPF 528 may filter the phase-rotated signal. For example, the HPF 528 may filter (e.g., reduce and/or remove) one or more lower frequency signals. For instance, the HPF 528 may filter (e.g., reduce, remove, etc.) one or more target receive signals from the phase-rotated signal. The one or more target receive signal(s) may be in one or more lower frequency ranges relative to the blocking signal(s). The HPF 528 may filter out the one or more lower frequency ranges. Accordingly, the high-pass filtered signal may include (e.g., only include) the blocking signal(s).

[0074] The second mixer 510 may up-convert the high-pass filtered signal (e.g., the blocking signal(s). For example, the second mixer 510 may shift (e.g., raise) the signal (e.g., the down-converted, phase rotated, and/or filtered signal) in frequency. For instance, the second mixer 510 may convert the filtered and rotated baseband signal to a radio frequency (RF) signal (and/or carrier frequency signal). In some approaches, the second mixer 510 may convert (e.g., up-convert) the signal back to the original frequency of the wireless communication signal 516. The BIC path 504 may output (e.g., may provide to the main circuitry path 502) the blocking signal(s) (at the original frequency of the wireless communication signal 516, for example). [0075] As described above, the first mixer 506 may exhibit an in-phase and quadrature (IQ) imbalance (e.g., mismatch). Additionally or alternatively, the second mixer 510 may exhibit an IQ imbalance (e.g., mismatch).

[0076] A tone (e.g., perfect tone) may be represented in accordance with Equation (1).

In Equation (1), s(t) is the tone in time t, e is the exponential function, j is the imaginary unit, cos is the cosine function, sin in the sine function, ω is angular frequency, n is a sample number, and N is a number of samples per period.

[0077] The model for IQ imbalance (e.g., mismatch) with a perfect tone may be represented as follows in Equations (2)-(5).

In Equations (2)-(5), Θ is an angle IQ imbalance (e.g., mismatch) for a mixer, x _Ic is an in-phase output after angle IQ imbalance (e.g., mismatch), and γ _Qc is a quadrature output after angle IQ imbalance (e.g., mismatch). [0078] When the apparatus 501 is performing blind interference cancellation, a null is created in one frequency. The HPF 528 may have a group delay, so the phase delay for each frequency may be different. IQ imbalance (e.g., mismatch) may add a phase offset (as shown in Equation Error! Reference source not found., for example) and may make the null move based on the value of the IQ phase imbalance.

[0079] Figure 6 is a graph 648 illustrating an example of null impact with different IQ imbalance (e.g., mismatch). The graph 648 is illustrated in power/frequency 644 (in decibel-milliwatts (dBm) over hertz (Hz)) over frequency 646 (in megahertz (MHz)). In particular, Figure 6 illustrates one example of null impact after BIC subtraction (e.g., after the subtractor 532 described in connection with Figure 5).

[0080] Figure 7 is a block diagram illustrating another more specific example of an apparatus 701 in which systems and methods for determining in-phase and quadrature (IQ) imbalance may be implemented. The apparatus 701 may be implemented in hardware (e.g., circuitry, an integrated circuit, an application-specific integrated circuit (ASIC), etc.) or a combination of hardware and software (e.g., a processor with instructions). The apparatus 701 described in connection with Figure 7 may be an example of one or more of the apparatuses 101, 501 described in connection with one or more of Figures 1 and 5.

[0081] The apparatus 701 may include a main circuitry path 702, a secondary circuitry path 704, a calibration controller 712, one or more receive antennas 714, a transmit circuitry path 754, and/or one or more transmit antennas 756. One or more of the components described in connection with Figure 7 may function similarly to, and/or may be configured similarly to one or more corresponding components (e.g., circuitries, blocks, components, elements, etc.) described in connection with one or more of Figures 1-2 and 4-5.

[0082] The main circuitry path 702 may receive a wireless communication signal 716 with one or more receive antennas 714. In the example given in Figure 7, the main circuitry path 702 includes a first stage LNA 730, a subtractor 732, a second stage LNA 734, a transconductance amplifier 752, and a receive mixer 736. The first stage LNA 730, subtractor 732, second stage LNA 734, and receive mixer 736 may function similarly to and/or may be configured similarly to one or more corresponding components described in connection with one or more of Figures 1-2 and 4-5. The transconductance amplifier 752 may produce a current signal that is proportional to the input voltage (of the signal output from the second LNA amplifier 734, for example). In some configurations, the main circuitry path 702 may be and/or may include a receive chain.

[0083] The transmit circuitry path 754 may be included in the apparatus 701 or may be separate from the apparatus 701. In some configurations, the transmit circuitry path 754 may be included in an electronic device (e.g., transceiver) with the main circuitry path 702 (e.g., a receive path) and the secondary circuitry path 704. In some cases, the transmit circuitry path 754 may transmit a signal (e.g., a WLAN signal) while the main circuitry path 702 receives another signal (e.g., a BT signal). In the example illustrated in Figure 7, the transmit circuitry path 754 includes a transmit mixer 760 and a power amplifier (PA) 758. The transmit circuitry path 754 is also coupled to one or more transmit antennas 756. The transmit mixer 760 may up-convert a signal and the PA 758 may amplify the signal for transmission by the transmit antenna(s) 756.

[0084] The secondary circuitry path 704 described in connection with Figure 7 may be an example of the secondary circuitry path 104 described in connection with Figure 1 and/or may be an example of the BIC path 504 described in connection with Figure 5. The secondary circuitry path 704 may be configured to determine a blocking signal in the wireless communication signal 716. The secondary circuitry path 704 may include a first mixer 706, a second mixer 710, phase rotation circuitry 708, HPF A 728a, HPF B 728b, and/or a summer 750. The first mixer 706, second mixer 710, phase rotation circuitry 708, HPF A 728a, and/or HPF B 728b may function similarly to and/or may be configured similarly to one or more corresponding components described in connection with one or more of Figures 1-2 and 4-5. The secondary circuitry path 704 may be coupled to the main circuitry path 702 (e.g., coupled in parallel and/or non-overlapping, etc.). In the example illustrated in Figure 7, the wireless communication signal 716 may be split into an in-phase (/) channel 762 and a quadrature (Q) channel 764. One or more of the functions of the first mixer 706, the phase rotation circuitry 708, the HPF 728 (e.g., HPF A 728a and HPF B 728b), and/or the second mixer 710 may be respectively performed on each of the in-phase channel 762 and the quadrature channel 764. The summer 750 may sum the in-phase channel 762 and the quadrature channel 764 (e.g., the blocking signal components corresponding to the in-phase channel 762 and the quadrature channel 764). [0085] As described herein, the first mixer 706 may exhibit IQ imbalance errors. The IQ imbalance errors for the first mixer 706 may be quantified as a first gain error ε\ and a first phase error θ\ . The IQ imbalance errors for the second mixer 710 may be quantified as a second gain error ¾ and a second phase error θ ₂ - The phase rotation circuitry 708 may rotate signals in accordance with a rotation matrix β.

[0086] Some configurations of the systems and methods disclosed herein may use the phase rotation circuitry 708 (e.g., a BIC phase rotation block) as an anchor and/or may use the phase rotation circuitry 708 to apply a known phase shift. This procedure may provide enough equations to isolate the IQ imbalance (e.g., mismatch) of the first mixer 706 and the second mixer 710 (of the secondary circuitry path 704, BIC path, etc., for example).

[0087] Since there are two mixers, the first mixer 706 and the second mixer 710, there are four unknowns (ει, ε2, θ\, θ ₂ ). The phase rotation circuitry 708 in the middle may be accessible (by the calibration controller 712, for example). Accordingly, the phase rotation circuitry 708 may be used to create a phase shift. As described above, a HPF 728 (e.g., HPF A 728a and HPF B 728b) may be in the calibration path. The impact of the HPF 728 may be limited if the calibration signal is relatively far in frequency from DC (e.g., at 2 MHz). In some configurations, the receive mixer 736 and/or the transmit mixer 760 may be assumed to be pre-calibrated with respective IQ imbalance (e.g., mismatch) calibration.

[0088] As described herein, the apparatus 701 (e.g., calibration controller 712) may send a first calibration tone through the secondary circuitry path 704. The apparatus 701 (e.g., calibration controller 712) may determine a first set of measurements (e.g., Measl and Meas2) corresponding to the first calibration tone. The apparatus 701 (e.g., phase rotation circuitry 708) may introduce a known phase shift (e.g., 45° or another value) to the secondary circuitry path 704.

[0089] The apparatus 701 (e.g., calibration controller 712) may send a second calibration tone through the secondary circuitry path 704. The apparatus 701 (e.g., calibration controller 712) may determine a second set of measurements (e.g., Meas3 and Meas4) corresponding to the second calibration tone. The apparatus 701 (e.g., calibration controller 712) may then use the first set of measurements and the second set of measurements to determine the IQ imbalance error metrics (e.g., ε ₁ , ε ₂ , θ ₁ , θ ₂ ). In some approaches, calibration may be performed in accordance with Equation (6).

In Equation (6), M may represent an overall system (e.g., secondary circuitry path 704). For example, M may represent a first mixer (e.g., first mixer 706), a rotation matrix (e.g., phase rotation circuitry 708), and a second mixer (e.g., second mixer 710). A may represent a first mixer (e.g., first mixer 706), C ^-1 may represent a correction applied or a rotation matrix (e.g., phase rotation circuitry 708), and B may represent a second mixer (e.g., second mixer 710). Accordingly, the secondary circuitry path 704 illustrated in Figure 7 may be represented as given in Equation (6) in some configurations.

[0090] Figure 8 is a block diagram illustrating another more specific example of an apparatus 801 in which systems and methods for determining in-phase and quadrature (IQ) imbalance may be implemented. The apparatus 801 may be implemented in hardware (e.g., circuitry, an integrated circuit, an application-specific integrated circuit (ASIC), etc.) or a combination of hardware and software (e.g., a processor with instructions). The apparatus 801 described in connection with Figure 8 may be an example of one or more of the apparatuses 101, 501, 701 described in connection with one or more of Figures 1, 5 and 7. For example, the apparatus 801 may be (or may be include in) a Bluetooth/frequency modulation (BT/FM) system-on-a chip (SOC).

[0091] The apparatus 801 may include a main circuitry path 802, a BIC path 804, a calibration controller 812, and/or one or more receive antennas 814. One or more of the components described in connection with Figure 8 may function similarly to, and/or may be configured similarly to one or more corresponding components (e.g., circuitries, blocks, components, elements, etc.) described in connection with one or more of Figures 1-2, 4-5, and 7.

[0092] The main circuitry path 802 may receive a wireless communication signal 816 with one or more receive antennas 814. In the example given in Figure 8, the main circuitry path 802 includes a first stage LNA 830, a switch 866, a subtractor 832, a second stage LNA 834, a transconductance amplifier 852, a receive mixer 836, an antialiasing filter (AAF) 838, and an ADC 840. The first stage LNA 830, subtractor 832, second stage LNA 834, transconductance amplifier 852, receive mixer 836, AAF 838, and/or ADC 840 may function similarly to and/or may be configured similarly to corresponding components described in connection with one or more of Figures 1-2, 4- 5, and 7. In some configurations, the main circuitry path 802 may be and/or may include a receive chain.

[0093] The BIC path 804 described in connection with Figure 8 may be an example of one or more of the secondary circuitry paths 104, 704 described in connection with Figure 1 and/or 7, and/or may be an example of the BIC path 504 described in connection with Figure 5. The BIC path 804 may be configured to determine a blocking signal in the wireless communication signal 816. The BIC path 804 may include a first mixer 806, a second mixer 810, BIC rotation circuitry 808, a baseband (BB) LPF 826, and/or a BIC HPF 828. The first mixer 806, second mixer 810, BIC rotation circuitry 808, BB LPF 826, and/or BIC HPF 828 may function similarly to and/or may be configured similarly to one or more corresponding components described in connection with one or more of Figures 1-2, 4-5, and 7. The BIC path 804 may be coupled to the main circuitry path 802 (e.g., coupled in parallel and/or non-overlapping, etc.). In the example illustrated in Figure 8, the wireless communication signal 816 may be split into an in-phase (/) channel and a quadrature (Q) channel. One or more of the functions of the BIC path 804 (e.g., first mixer 806, BB LPF 826, BIC rotation circuitry 808, BIC HPF 828, and/or second mixer 810) and/or one or more of the functions of the main circuitry path 802 (e.g., receive mixer 836, AAF 838, and/or ADC 840) may be respectively performed on each of the in-phase channel and the quadrature channel. In one example, the ADC 840 may produce a 32 MHz signal.

[0094] As described herein, the first mixer 806 and/or the second mixer 810 may exhibit IQ imbalance errors. The IQ imbalance errors for the first mixer 806 may be quantified as a first gain error ε\ and a first phase error θ\ . The IQ imbalance errors for the second mixer 810 may be quantified as a second gain error ¾ and a second phase error θ ₂ - The BIC rotation circuitry 808 may rotate signals in accordance with a rotation matrix β.

[0095] One or more procedures, functions, algorithms, steps, etc., for performing calibration are described in connection with Figure 8 as follows. When performing IQ calibration, it may need to be ensured that there are no other signals on the main circuitry path 802. For example, only a calibration tone may be supplied to the BIC path 804 going into the ADC 840. For instance, if there are one or more other signals on the main circuitry path 802, this may interfere with IQ mismatch calibration and/or may make it difficult to isolate only the signal that went through the BIC path 804. Accordingly, a configurable gain (e.g., -30 dB gain) may be implemented on the main circuitry path 802. As illustrated in Figure 8, for example, a switch 866 may be included on the main circuitry path 802. The switch 866 may be employed (e.g., may be controlled by the calibration controller 812) to provide the attenuation.

[0096] As described herein, some approaches for calibration may be implemented in BT/WLAN products. It should be noted that the systems and methods disclosed herein may be implemented for other electronic devices that utilize concurrent wireless transmission and reception.

[0097] The BIC rotation circuitry 808 may be reused as a phase shift block. This phase shift may allow calibrating both the first mixer 806 and the second mixer 810. Calibration may be employed to ensure that the BIC path 804 can achieve good reduction (e.g., cancellation) performance.

[0098] As can be observed in Figure 8, the mixer(s) 806, 810 are both in the BIC path 804, and the BIC rotation circuitry 808 is reused to perform the intentional phase shift. As noted above, the main circuitry path 802 may be attenuated and/or a calibration signal/tone may be utilized that will not be significantly affected by the BIC HPF 828.

[0099] In some configurations, the apparatus 801 may perform one or more of the following operations in a calibration procedure. The apparatus 801 (e.g., calibration controller 812 and/or switch 866) may reduce the gain on the main circuitry path 802. For example, the apparatus 801 may reduce the gain to approximately -30 dB.

[00100] The apparatus 801 (e.g., calibration controller 812) may set frequencies for the first mixer 806, for the second mixer 810, and the receive mixer 836 to the same frequency. For example, the calibration controller 812 may send a signal (e.g., command) to set the frequencies of the first mixer 806, for the second mixer 810, and the receive mixer 836 to the same frequency.

[00101] The apparatus 801 (e.g., calibration controller 812) may set a rotation matrix (e.g., a BIC rotation matrix, β) to unity. For example, no rotation may be applied initially. For instance, the apparatus 801 (e.g., calibration controller 812) may set the BIC rotation circuitry 808 gains to unity in accordance with Equation (7). In Equation (7), Gl, G2, and G2' represent gains of amplifiers included in the BIC rotation circuitry.

[00102] The apparatus 801 (e.g., calibration controller 812) may disable intermediate frequency (e.g., low-IF) rotation in the BIC path 804 and main circuitry path 802 (e.g., receive path). Low-IF may be one kind of receiver architecture. The low-IF rotation may be disabled by changing the mixer configuration or settings (to down-mix to DC directly rather than create a low-IF signal, for example). The low-IF rotation may be disabled in order to measure a DC offset (e.g., local oscillator (LO) leakage).

[00103] The apparatus 801 (e.g., calibration controller 812) may measure local oscillator (LO) leakage. The LO Leakage at baseband may be a DC offset. The LO leakage may be measured digitally and may be examined to obtain the value of the DC offset. For example, no receive signal (e.g., the wireless communication signal 816) may be sent through the circuitry (e.g., BIC path 804 and/or main circuitry path 802) when measuring the DC offset.

[00104] The apparatus 801 (e.g., calibration controller 812) may send a first calibration tone (e.g., 1 MHz tone). For example, the apparatus may produce a calibration tone for taking a first set of measurements. It should be noted that when the calibration tone (e.g., 1 MHz tone) is sent, one or more measurements may be taken. The previously measured DC offset may be removed from one or more of the measurement(s) to ensure that only the impact of the tone is measured.

[00105] The apparatus 801 (e.g., calibration controller 812) may calculate (e.g., compute) the first set of measurements (e.g., Measl and Meas2). The first set of measurements may be stored (e.g., saved) in memory. When no rotation is applied, the first set of measurements (e.g., Measl and Meas2) may be expressed as given in Equations (8) and (9).

[00106] In Equations (8) and (9), Measl is a first measurement, Meas2 is a second measurement, t is time, E[] is an expected value (e.g., mean) operation, si(t) is an in- phase component of a calibration signal, sQ(t) is a quadrature component of the calibration signal, e _R i is a gain error of a first mixer,∈ _R2 is a gam error of a second mixer, Q _m \ is a phase error of a first mixer, and 0 _m 2 is a phase error of a second mixer.

Measl may indicate one or more gain errors. As illustrated in Equation (8), for example, Measl may correspond to a combination (e.g., sum) of gain errors for the first and second mixers. Measl may indicate one or more phase errors. For example, Measl may correspond to a combination (e.g., sum) of phase errors from the first and second mixers (e.g., a sum of half phase errors for the first and second mixers) as illustrated in Equation (9). It should be noted that in some configurations, Measl, Measl, Measi, and/or MeasA may be taken by a microcontroller (e.g., embedded firmware). For example, the calibration controller 812 may take Measl, Measl, Meas3, and/or MeasA. Additionally or alternatively, Measl, Measl, Measi, and/or MeasA may be calculated in a hardware circuit (e.g., the calibration controller 812 or a separate block of hardware). In some configurations, Measl, Measl, Meas3, and/or MeasA may be taken from a secondary circuitry path (e.g., the BIC path 804).

[00107] The apparatus 801 (e.g., calibration controller 812) may set the BIC rotation to an angle. For example, apparatus 801 (e.g., calibration controller 812) may set the BIC rotation to Θ = 45 degrees in accordance with Equation (10).

[00108] The apparatus 801 (e.g., calibration controller 812) may send a second calibration tone (e.g., 1 MHz tone). For example, the apparatus may produce a calibration tone for taking a second set of measurements.

[00109] The apparatus 801 (e.g., calibration controller 812) may calculate (e.g., compute) the second set of measurements (e.g., Meas3 and Meas4). The second set of measurements may be stored (e.g., saved) in memory in some configurations. When a rotation is applied, the second set of measurements (e.g., Meas3 and Meas4) may be expressed as given in Equations (11) and (12).

In Equations (11) and (12), Meas3 is a third measurement, Meas4 is a fourth measurement, and β is a rotation matrix. For example, β may be defined as the angle (e.g., phase shift) applied by the BIC rotation circuitry 808. As described herein, no rotation (e.g., β = 0) may be utilized to obtain the first set of measurements and a 45 degree rotation (e.g., β = π/4) may be utilized to obtain the second set of measurements (which may result in a total of 4 measurements: Measl, Meas2, Meas3, and Meas4, for example). It should be noted that one or more other rotations may be utilized in accordance with the systems and methods disclosed herein.

[00110] The apparatus 801 (e.g., calibration controller 812) may use the first set of measurements and the second set of measurements to determine IQ imbalance error metrics. For example, apparatus 801 (e.g., calibration controller 812) may solve Equation (13) to determine the IQ imbalance (e.g., mismatch) for the first mixer 806 and the second mixer 810. As illustrated, Equation (13) may be viewed as a set of 4 equations with 4 unknowns.

[00111] Figure 9 is a flow diagram illustrating a more specific configuration of a method 900 for determining in-phase and quadrature (IQ) imbalance. The method 900 may be performed by one or more of the apparatuses 101, 501, 701, 801 described in connection with one or more of Figures 1, 5, 7, and 8. [00112] The apparatus 101 may reduce 902 a gain on the main circuitry path. This may be accomplished as described in connection with one or more of Figures 1 and 8. For example, the apparatus 101 (e.g., calibration controller 112) may switch off one or more antennas and/or may turn down one or more gains (of one or more amplifiers, for example) in the main circuitry path.

[00113] The apparatus 101 may set 904 frequencies for a first mixer in the secondary circuitry path, a second mixer in the secondary circuitry path, and a third mixer (e.g., a receive mixer) in the main circuitry path to the same frequency. This may be accomplished as described in connection with one or more of Figures 1 and 8. For example, the apparatus 101 (e.g., calibration controller 112) may set the local oscillator frequency for each of the mixers at the same frequency.

[00114] The apparatus 101 may set 906 a rotation of the phase rotation circuitry to unity. This may be accomplished as described in connection with one or more of Figures 1 and 8. For example, the apparatus 101 (e.g., calibration controller 112) set the phase rotation circuitry with a rotation of 0 degrees or no rotation.

[00115] The apparatus 101 may disable 908 intermediate frequency (e.g., low-IF) rotation in the main circuitry path and in the secondary circuitry path. This may be accomplished as described in connection with one or more of Figures 1 and 8. For example, the apparatus 101 (e.g., calibration controller 112) may send a signal (e.g., command) to disable low-IF rotation.

[00116] The apparatus 101 may measure 910 local oscillator (LO) leakage. This may be accomplished as described in connection with one or more of Figures 1 and 8.

[00117] The apparatus 101 may send 912 a first calibration tone through the secondary circuitry path. This may be accomplished as described in connection with one or more of Figures 1, 4-5, and 7-8.

[00118] The apparatus 101 may determine 914 a first set of measurements corresponding to the first calibration tone. This may be accomplished as described in connection with one or more of Figures 1, 4-5, and 7-8. In some configurations, this may be accomplished in accordance with Equations (8)-(9).

[00119] The apparatus 101 may introduce 916 a known phase shift to the secondary circuitry path. This may be accomplished as described in connection with one or more of Figures 1-2, 4-5, and 7-8. In some configurations, this may be accomplished in accordance with Equation (10). [00120] The apparatus 101 may send 918 a second calibration tone through the secondary circuitry path. This may be accomplished as described in connection with one or more of Figures 1, 4-5, and 7-8.

[00121] The apparatus 101 may determine 920 a second set of measurements corresponding to the second calibration tone. This may be accomplished as described in connection with one or more of Figures 1-2, 4-5, and 7-8. In some configurations, this may be accomplished in accordance with Equations (11)— (12).

[00122] The apparatus 101 may use 922 the first set of measurements and the second set of measurements to determine IQ imbalance error metrics. This may be accomplished as described in connection with one or more of Figures 1-2, 4-5, and 7- 8. In some configurations, this may be accomplished in accordance with Equation (13).

[00123] Some mathematical derivation providing support for some configurations of the systems and methods disclosed herein is given as follows. In reference to Equation (6), [ ] may be defined as given in Equation (14) in some approaches.

Equation (20) illustrates an example of [ ] in matrix form.

Providing (e.g., transmitting) a tone may be accomplished in accordance with Equations (21)-(22).

Obtaining expected values based on s _j (t) and S _Q (i) may be accomplished in accordance with Equations (23)-(25).

A similar approach may be utilized to obtain Equations (26)-(32) with a rotation.

(26)

Transmitting a tone in accordance with Equation (28) and finding expected values may yield Equations (28)-(30).

Equations (31)— (32) may follow.

[00124] Figure 10 illustrates certain components that may be included within an electronic device 1068 configured to implement various configurations of the systems and methods disclosed herein. The electronic device 1068 may be an access terminal, a mobile station, a user equipment (UE), a smartphone, a digital camera, a video camera, a tablet device, a laptop computer, a desktop computer, a server, etc. The electronic device 1068 may be implemented in accordance with one or more of the apparatuses 101, 501, 701, 801 described herein. For example, the electronic device 1068 may be an example of one or more of the apparatuses 101, 501, 701, 801 described herein or may include one or more of the apparatuses 101, 501, 701, 801 described herein. For example, one or more of the apparatuses 101, 501, 701, 801 described herein may be implemented in the receiver 1082 and/or transceiver 1084.

[00125] The electronic device 1068 includes a processor 1090. The processor 1090 may be a general purpose single- or multi-chip microprocessor (e.g., an ARM), a special purpose microprocessor (e.g., a digital signal processor (DSP)), a microcontroller, a programmable gate array, etc. The processor 1090 may be referred to as a central processing unit (CPU). Although just a single processor 1090 is shown in the electronic device 1068, in an alternative configuration, a combination of processors (e.g., an ARM and DSP) could be implemented.

[00126] The electronic device 1068 also includes memory 1070. The memory 1070 may be any electronic component capable of storing electronic information. The memory 1070 may be embodied as random access memory (RAM), read-only memory (ROM), magnetic disk storage media, optical storage media, flash memory devices in RAM, on-board memory included with the processor, EPROM memory, EEPROM memory, registers, and so forth, including combinations thereof.

[00127] Data 1074a and instructions 1072a may be stored in the memory 1070. The instructions 1072a may be executable by the processor 1090 to implement one or more of the methods 200, 400, 900 described herein. Executing the instructions 1072a may involve the use of the data 1074a that is stored in the memory 1070. When the processor 1090 executes the instructions 1072, various portions of the instructions 1072b may be loaded onto the processor 1090 and/or various pieces of data 1074b may be loaded onto the processor 1090.

[00128] The electronic device 1068 may also include a transmitter 1080 and a receiver 1082 to allow transmission and reception of signals to and from the electronic device 1068. The transmitter 1080 and receiver 1082 may be collectively referred to as a transceiver 1084. One or more antennas 1078a-b may be electrically coupled to the transceiver 1084. The electronic device 1068 may also include (not shown) multiple transmitters, multiple receivers, multiple transceivers and/or additional antennas.

[00129] The electronic device 1068 may include a digital signal processor (DSP) 1086. The electronic device 1068 may also include a communications interface 1088. The communications interface 1088 may allow and/or enable one or more kinds of input and/or output. For example, the communications interface 1088 may include one or more ports and/or communication devices for linking other devices to the electronic device 1068. In some configurations, the communications interface 1088 may include the transmitter 1080, the receiver 1082, or both (e.g., the transceiver 1084). Additionally or alternatively, the communications interface 1088 may include one or more other interfaces (e.g., touchscreen, keypad, keyboard, microphone, camera, etc.). For example, the communication interface 1088 may enable a user to interact with the electronic device 1068.

[00130] The various components of the electronic device 1068 may be coupled together by one or more buses, which may include a power bus, a control signal bus, a status signal bus, a data bus, etc. For the sake of clarity, the various buses are illustrated in Figure 10 as a bus system 1076.

[00131] Figure 11 is a block diagram illustrating an example of phase rotation circuitry 1108 that may be implemented in accordance with some configurations of the systems and methods disclosed herein. The phase rotation circuitry 1108 may be an example of one or more of the phase rotation circuitries 108, 508, 708 described in connection with one or more of Figures 1, 5, and 7, and/or of the BIC rotation circuitry 808 described in connection with Figure 8. As illustrated in Figure 11, the phase rotation circuitry 1108 may include four amplifiers with gains GA 1105, GB 1109, GB'

1111, and GA' 1107. For example, the gains GA 1105, GB 1109, GB' 1111, and GA'

1107 may be four different BIC gains. The gains of one or more of the amplifiers may be controlled with control signal A 1117 and/or control signal B 1119. For example, control signal A 1117 and/or control signal B 1119 may be control signals provided by a controller (e.g., calibration controller 112).

[00132] One or more of the gains (e.g., GA 1105, GB 1109, GB' 1111, and/or GA' 1107) may be controlled in order to reduce (e.g., correct) IQ imbalance. For example, two input signals, xi 1121 and xj 1103, may be provided to the phase rotation circuitry

1108 (from a low pass filter, for instance). One or more of the gains (e.g., GA 1105, GB 1109, GB' 1111, and/or GA' 1107) may be applied to one or more of the input signals xi

1121 and xj 1103 in order to produce signals 1113, 1115 (e.g., output signals).

[00133] The term "determining" encompasses a wide variety of actions and, therefore, "determining" can include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, a database or another data structure), ascertaining and the like. Also, "determining" can include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory) and the like. Also, "determining" can include resolving, selecting, choosing, establishing, and the like.

[00134] The phrase "based on" does not mean "based only on," unless expressly specified otherwise. In other words, the phrase "based on" describes both "based only on" and "based at least on."

[00135] The term "processor" should be interpreted broadly to encompass a general purpose processor, a central processing unit (CPU), a microprocessor, a digital signal processor (DSP), a controller, a microcontroller, a state machine, and so forth. Under some circumstances, a "processor" may refer to an application specific integrated circuit (ASIC), a programmable logic device (PLD), a field programmable gate array (FPGA), etc. The term "processor" may refer to a combination of processing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[00136] The term "memory" should be interpreted broadly to encompass any electronic component capable of storing electronic information. The term memory may refer to various types of processor-readable media such as random access memory (RAM), read-only memory (ROM), non-volatile random access memory (NVRAM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable PROM (EEPROM), flash memory, magnetic or optical data storage, registers, etc. Memory is said to be in electronic communication with a processor if the processor can read information from and/or write information to the memory. Memory that is integral to a processor is in electronic communication with the processor.

[00137] The terms "instructions" and "code" should be interpreted broadly to include any type of computer-readable statement(s). For example, the terms "instructions" and "code" may refer to one or more programs, routines, sub-routines, functions, procedures, etc. "Instructions" and "code" may comprise a single computer-readable statement or many computer-readable statements.

[00138] The functions described herein may be implemented in software or firmware being executed by hardware. The functions may be stored as one or more instructions on a computer-readable medium. The terms "computer-readable medium" or "computer- program product" refers to any tangible storage medium that can be accessed by a computer or a processor. By way of example and not limitation, a computer-readable medium may comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray ^® disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. It should be noted that a computer-readable medium may be tangible and non-transitory. The term "computer-program product" refers to a computing device or processor in combination with code or instructions (e.g., a "program") that may be executed, processed, or computed by the computing device or processor. As used herein, the term "code" may refer to software, instructions, code, or data that is/are executable by a computing device or processor.

[00139] Software or instructions may also be transmitted over a transmission medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio and microwave are included in the definition of transmission medium.

[00140] The methods disclosed herein comprise one or more steps or actions for achieving the described method. The method steps and/or actions may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of steps or actions is required for proper operation of the method that is being described, the order and/or use of specific steps and/or actions may be modified without departing from the scope of the claims.

[00141] Further, it should be appreciated that modules and/or other appropriate means for performing the methods and techniques described herein, can be downloaded, and/or otherwise obtained by a device. For example, a device may be coupled to a server to facilitate the transfer of means for performing the methods described herein. Alternatively, various methods described herein can be provided via a storage means (e.g., random access memory (RAM), read-only memory (ROM), a physical storage medium such as a compact disc (CD) or floppy disk, etc.), such that a device may obtain the various methods upon coupling or providing the storage means to the device.

[00142] It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes, and variations may be made in the arrangement, operation, and details of the systems, methods, and apparatus described herein without departing from the scope of the claims.