TECHNICAL FIELD

This disclosure relates to tandem photovoltaic cells, methods of fabricating the same and photovoltaic systems.

CROSS REFERENCE TO RELATED APPLICATION

The present application claims priority from Australian Provisional Patent Application No. 2021903892, the entire contents of which is incorporated herein by reference.

BACKGROUND ART

Photovoltaic cells, or solar cells as they are more commonly known, are one of the most important technologies driving the renewable energy revolution. Research into solar cells has resulted in significant gains in conversion efficiency. However, it remains desirable to improve the efficiency of photovoltaic modules. Higher efficiency photovoltaic modules can allow the fabrication of a system that is more compact thereby reducing the balance-of-system costs (i.e. the same amount of electricity can be generated with a smaller area panel thus resulting in lower balance-of-system costs). However, single junction solar cells have an upper efficiency limit (the Shockley-Queisser limit) beyond which efficiency cannot be improved. Given this, one of the strategies to improve efficiency of photovoltaic modules is through the use of a tandem cells.

Tandem cells incorporate multiple sub-cells, comprising materials with different absorption properties, that allow the tapping a wider range of wavelengths from the solar spectrum. In particular, tandem cells integrate a high-efficiency wide- bandgap upper solar cell with a low-bandgap bottom solar cell to improve overall efficiency. Tandem configurations allow the high-energy photons to be absorbed in the upper sub-cell, which can generate a high voltage to reduce thermalization loss, and allow the lower sub-cell to absorb lower-energy photons (which have been transmitted through the upper sub-cell), thus enabling broader energy harvesting.

Due to its band gap properties, silicon solar cells are often used as the lower subcells in tandem configurations. Silicon heterojunction (SHJ) lower sub-cells, dominate tandem research. In order to develop tandem configurations suitable for commercial-scale production, it is desirable to optimise the performance and costs of the lower sub-cell, as well as its compatibility with the subsequent process steps associated with forming the tandem configuration. Complex processing steps can be required to form both the lower sub-cell and connect it to the upper sub-cell. The use of a silicon sub-cell and associated doped charge transport/passivation layers may place limitations on the material choices and processing.

Accordingly, it is desired to address the above or at least provide a useful alternative. For example, it is desirable to simplify the deposition and/or the structure of tandem photovoltaic cells.

SUMMARY

In a first aspect, the present invention provides a tandem photovoltaic cell, comprising, in order relative to incident light: a first sub-cell; and a second sub-cell, said second sub-cell comprising: a silicon-free upper carrier-selective transport layer; and a crystalline silicon substrate.

In some embodiments, the first sub-cell comprises an absorber layer comprising a perovskite material. The perovskite material may comprise a compound of formula (I):

ABX ₃ (I), wherein: A is a cation selected from a group consisting of: methyl ammonium (MA), formamidinium (FA), Cs, or Rb or any combination thereof;

B is a metal cation selected from a group consisting of: Pb, Sn, Sb, Bi or any combination thereof; and

X is a halide anion.

In some embodiments, A comprises one or more cations selected so that the molar percentage of A being: formamidinium ranges from 0% to 100%; methyl ammonium ranges from 0% to 100%; Cs ranges from 0% to 100%; and Rb ranges from 0% to 25%.

In some embodiments, the perovskite material is a mixed-cation perovskite; and A comprises two or more cations. Alternatively, or additionally, X may be two or more different halide anions. In some embodiments, X is selected from the group consisting of I, Br, Cl, and mixtures thereof.

In some embodiments, the perovskite material is Cso.o5Rbo.o5FAo.765MAo.135PbI2.55Bro.45.

In some embodiments of the first sub-cell, the first sub-cell comprises a first carrier-selective charge transport layer between the absorber layer and the silicon- free upper carrier-selective transport layer. In some embodiments, the first subcell comprises a second carrier-selective charge transport layer deposited, in order relative to incident light, on top of the absorber layer. Some embodiments of the first sub-cell may comprise: a first passivating layer between the absorber layer and the first carrier-selective charge transport layer; and a second passivating layer between the absorber layer and the second carrier-selective charge transport layer.

In some embodiments, the silicon-free upper carrier-selective transport layer of the second sub-cell is configured as a hole-transport layer. In some of these embodiments, the silicon-free upper carrier-selective transport layer comprises a material selected from the group consisting of: transition metal oxides; poly(3,4- ethylenedi oxythiophene) polystyrene sulfonate (PEDOT); poly(3-hexylthiophene- 2,5-diyl) (P3HT); Poly[bis(4-phenyl)(2,4,6-trimethylphenyl)amine (PTAA); Copper(II) Phthalocyanine(CuPc), Cui and CuSCN. The transition metal oxides may be selected from the group consisting of: MoCh; WCh; V2O5; NiO _x ; and CuOx.

In some embodiments in which the silicon-free upper carrier-selective transport layer of the second sub-cell is configured as a hole-transport layer: the first subcell comprises a first carrier-selective charge transport layer between the absorber layer and the silicon-free upper carrier-selective transport layer; and the first carrier-selective charge transport layer is configured as an electron-transport layer. In some of these embodiments, the first carrier selective charge transport layer comprises a material selected from the group consisting of: SnCh, TiCh, Nb2Os, Ta2Os, SrTiCh, and Ceo.

In some embodiments, the silicon-free upper carrier selective transport layer (i.e. of the second sub-cell) is configured as an electron-transport layer. In some of these embodiments, the silicon-free upper carrier-selective transport layer comprises a material selected from the group consisting of: SnCh, TiCh, Nb2Os, Ta2Os, SrTiCh, ZnO and Ceo

In some embodiments in which the silicon-free upper carrier-selective transport layer of the second sub-cell is configured as an electron-transport layer: the first sub-cell comprises a first carrier-selective charge transport layer between the absorber layer and the silicon-free upper carrier-selective transport layer; and the first carrier-selective charge transport layer is configured as a hole-transport layer. In some of these embodiments, the first carrier-selective charge transport layer comprises a material selected from the group consisting of: 2,2',7,7'-Tetrakis-9,9'- spirobifluorene; poly[bis(4-phenyl)(2,5,6-trimethylphenyl)amine; 2, 2', 7, 7'- Tetra(N,N-di-p-tolyl)amino-9,9-spirobifluorene; CuSCN; NiO _x ; and CuMCh, wherein M is Ga, Al, or Cr.

In some embodiments, the silicon-free upper carrier-selective transport layer (i.e. of the second sub-cell) directly contacts the first sub-cell. Alternatively, in some embodiments, the tandem photovoltaic cell comprises an interconnecting layer between the first sub-cell and the silicon-free upper carrier-selective transport layer. In some embodiments, the interconnecting layer may be in the form of a transparent conducting oxide layer or a tunnelling junction layer.

In some embodiments, the silicon-free upper carrier- selective transport layer directly contacts the crystalline silicon substrate. Alternatively, in some embodiments, the tandem photovoltaic cell comprises a first passivating layer between the crystalline silicon substrate and the silicon-free upper carrier- selective transport layer.

In a second aspect, the present invention provides a method of fabricating a tandem photovoltaic cell, said method comprising: providing a second sub-cell, said second sub-cell comprising, in order relative to incident light: a silicon-free upper carrier- selective transport layer; and a crystalline silicon substrate; and depositing a first sub-cell on top of the second sub-cell.

In some embodiments of this aspect, the first sub-cell is deposited directly onto the silicon-free upper carrier-selective transport layer. Alternatively, in some embodiments, the method comprises, before depositing the first sub-cell, depositing an interconnecting layer onto the silicon-free upper carrier- selective transport layer.

In some embodiments, said depositing of the first sub-cell comprises: depositing a first carrier-selective transport layer. In some of these embodiments, said depositing of the first carrier-selective transport layer comprises: depositing an initial sub-layer by Atomic Layer Deposition; and depositing an upper sub-layer.

Depositing of the first sub -cell may comprise: depositing an absorber layer on top of the first carrier-selective transport layer; depositing a second carrier-selective transport layer on top of the absorber layer; fabricating a transparent conductor layer on top of the second carrier- selective transport layer; and depositing a top electrode on the transparent conductor layer. In some of these embodiments, said depositing of the first sub-cell comprises: before depositing the absorber layer, depositing a first passivating layer on the first carrier-selective transport layer so that said a first passivating layer is between the first carrier-selective transport layer and the absorber layer; and/or before depositing a second carrier-selective transport layer, depositing a second passivating layer on the absorber layer so that said a second passivating layer is between the absorber layer the second carrier-selective transport layer. Alternatively, or additionally, said depositing of the first sub-cell comprises: before fabricating the transparent conductor layer, depositing a buffer layer on the second carrier-selective transport layer so that said buffer layer is between the second carrier- selective transport layer and the transparent conductor layer.

In some embodiments, said depositing of the first sub-cell comprises: before depositing the absorber layer, annealing the first carrier- selective transport layer.

In some embodiments of the second aspect, said providing of the second sub-cell comprises: providing the crystalline silicon substrate; depositing the silicon-free upper carrier-selective transport layer on top of the crystalline silicon substrate; deposing a lower carrier-selective transport layer below the crystalline silicon substrate; and depositing a lower electrode layer on the lower carrier-selective transport layer. In some of these embodiments, the method comprises (after providing the crystalline silicon substrate) passivating the crystalline silicon substrate so that: upper and lower passivating layers are provided on each side of the crystalline silicon substrate; the upper passivating layer is between the crystalline silicon substrate and the silicon-free upper carrier-selective transport layer; and the lower passivating layer is between the crystalline silicon substrate and the lower carrier-selective transport layer. In some embodiments, providing the crystalline silicon substrate comprises: preparing the surface of a silicon wafer.

In some embodiments of the second aspect, the tandem photovoltaic cell is a tandem photovoltaic cell according to the first aspect.

In a third aspect, the present invention provides a photovoltaic system, said system comprising one or more photovoltaic modules wherein the or each photovoltaic module (or at least some of the photovoltaic modules) comprises a plurality of tandem photovoltaic cells in accordance with the first aspect. In some embodiments, some or all of the tandem photovoltaic cells in at least one module are connected in series. In some embodiments, some or all of the tandem photovoltaic cells in at least one module are connected in parallel.

DETAILED DESCRIPTION

The first aspect of the present invention provides a tandem photovoltaic cell, comprising, in order relative to incident light: a first sub-cell; and a second subcell, said second sub-cell comprising: a silicon-free upper carrier-selective transport layer; and a crystalline silicon substrate. The first, or uppermost, sub-cell is configured to absorb light from the high energy/low wavelength spectrum of sunlight. For example, the first sub-cell may be able to absorb energy from blue light (i.e. wavelengths of approximately 300 - 800 nm). Accordingly, the first sub-cell may comprise a high band gap material as the absorber, of approximately 1.5eV to 1.8eV. The first sub-cell may further be substantially transparent to low energy/high wavelength light, to allow such light to pass to the second (or lower) sub-cell of the tandem cell.

The second sub-cell can comprise a crystalline silicon substrate (which may be considered a conductive silicon substrate) that is configured to absorb light from the low energy /higher wavelength spectrum of sunlight. For example, the second sub-cell may be able to absorb energy from red/near-infrared light (i.e. wavelengths of -1200 nm). Accordingly, the second sub-cell may comprise a relatively low band gap material.

The first and second sub-cells are generally connected in series, allowing the voltage across the two sub-cells to additively combine. Thus, by stacking multiple cells on top of one another, it is possible to increase the voltage generated from the tandem (provided the absorbers in each sub-cell of the tandem are capable of being excited).

It is to be understood that, except where expressly indicated otherwise, the term ‘first sub-cell’ is intended to refer to an uppermost sub-cell (relative to incident light), while the term ‘second sub-cell’ is intended to refer to a lower sub-cell, relative to the first sub-cell. In this regard, the tandem cell may be constructed by a process including the fabrication of the second sub-cell, prior to the fabrication of the first sub-cell, above and in a stacked relationship with the first sub-cell.

The second sub-cell, or the silicon sub-cell, comprises a silicon-free carrier- selective transport layer (CSL), which is located between the first sub-cell and the crystalline silicon substrate of the silicon sub-cell in the tandem structure. As used herein, “silicon-free” means that no silicon has been intentionally added. One of ordinary skill in the art would recognize that the choice of raw materials could unintentionally include impurities, including silicon, that may be incorporated into the layer during processing. The presence of such impurities would not significantly alter the properties of the layer and, accordingly, performance of the tandem photovoltaic cell.

This upper CSL may facilitate transfer of only one type of charge carrier, while blocking the other type. For example, the CSL may allow only holes to pass through while blocking electrons. Alternatively, the CSL may allow only electrons to pass through while blocking holes. The CSL may thus function as a low resistivity pathway for the generated charge carriers to be transported away from the p-n junction of the silicon sub-cell.

A CSL will be provided, in order relative to the incident light, above and below the crystalline silicon substrate (i.e. an upper CSL and a lower CSL). One CSL will be configured as a hole transport layer, while the other will be configured as an electron-transport layer. In some embodiments, the silicon-free upper carrier- selective transport layer between the first sub-cell and the crystalline silicon substrate may be a hole-transport layer. In other embodiments, the silicon-free CSL between the first sub-cell and the crystalline silicon substrate may be an electron transport layer.

The use of a silicon-free CSL may simplify fabrication of the tandem cell. Generally, the fabrication of a tandem cell involves deposition of the second subcell followed by the first sub-cell on top of the second sub-cell. For example, during fabrication, the second sub-cell may be fabricated in an initial step and the first sub-cell may be subsequently deposited on top of the second sub-cell. Consequently, the components of the second sub-cell need to withstand the processing conditions employed during the fabrication of the first sub-cell, without sustaining significant damage. Significant damage may be damage that degrades the performance of the second sub-cell below a predetermined limit. Accordingly, the fabrication process may affect the performance of the second sub-cell, but within an acceptable range. In general, it is desirable to minimise the degree of degradation. The predetermined limited for the degree of degradation can be selected based on the total manufacturing cost and the additional energy yield achieved by the tandem design. Thus, the degree of degradation may be selected to achieve a desired mean and standard deviation of manufactured cells in relation to the ideal cell performance.

In configurations used in the prior art, the CSL for a silicon-based second sub-cell typically comprises a doped silicon-based material, such as an n-type or p-type amorphous silicon layer. The fabrication processes used for doped silicon-based layers can involve using toxic and dangerous gases for doping. Such fabrication processes may be complicated and contribute to high fabrication costs. Thus, it can be desirable to minimise the use of doped silicon-based CSLs.

Furthermore, the characteristics of such heavily doped silicon layers can be altered depending on the processing conditions employed for fabrication of the first sub-cell. For example, the temperatures employed during deposition of layers for the first sub-cell may reach levels that can result in changes to the doped structure of the CSL of the second sub-cell, effecting changes in the distribution of dopants and leading to alteration of the opto-electronic properties of the CSL. These changes may significantly affect the functionality of the tandem cell.

Production of the first sub-cell may involve one or more annealing processes. These annealing processes may be performed at temperatures in the range of about 95°C to 450°C. The temperature may be selected depending on the material composition of the first sub-cell and/or the fabrication process(es) used. For example, some materials for use as a carrier-selective transport layer for the first sub-cell may require annealing at higher temperatures. Annealing at higher temperatures may result in better crystallisation and, thus, conductivity. Materials that may be annealed at higher temperatures include transition metal oxides, such as NiOx and TiCh. It is desirable to select a material for the second sub-cell that is capable of withstanding the annealing conditions used for fabrication of the first sub-cell.

In addition, solvents are used during the fabrication of the first sub-cell. Common solvents include H2O, ethanol, Isopropyl alcohol (IP A), Dimethylformamide (DMF), Dimethyl sulfoxide. These solvents can cause damage to the components of the second sub-cell. Thus, it is important to select materials for the second subcell that are compatible with the solvents to be used. Otherwise, solvent exposure during fabrication of the first sub-cell may cause degradation of the second subcell and attendant losses in cell performance.

The silicon-free CSL of the tandem photovoltaic cell in accordance with the present invention may be fabricated in a relatively more straightforward manner compared to a doped, silicon-based CSL. In some embodiments, the silicon-free CSL is a dopant-free, silicon-free CSL. As used herein, “dopant-free” means that no dopant has been intentionally added.

In some other embodiments, the silicon-free CSL is a doped CSL. Doping may allow engineering of the material of the CSL to achieve suitable or desired energy levels and optoelectronic properties. Doping of the material for the CSL may be intrinsic (i.e. controlled by the fabrication process conditions) or extrinsic doping. For example, Al- or Li-doping of a transition metal oxide may be employed.

In contrast to the prior art, the silicon-free materials that can be utilised for the CSL of the present disclosure, may be able to withstand a wider variety of fabrication conditions employed for the first sub-cell. By avoiding the use of dopants in the CSL, it can be possible to select from a broader range of materials, which may have temperature-stability and/or solubility, diffusion and reactivity characteristics that permit their use with a wider variety of first sub-cell fabrication conditions. For example, as described in further detail below, in some embodiments the CSL may comprise a transition metal oxide layer. Transition metal oxides may have enhanced resistance to the solvents used for first sub-cell fabrication. In addition, transition metal oxides can have temperature stabilities, that permit them to withstand temperatures in excess of the annealing temperatures used for fabrication of the first sub-cell.

In some embodiments, the silicon-free CSL can withstand temperatures of up to 450°C. In some embodiments, the silicon-free CSL can withstand temperatures in excess of about 200°C, such as in excess of 250°C, or in excess of 300°C.

The second sub-cell may be located beneath the first sub-cell, relative to incident light. This arrangement can affect the range of materials that are suitable for use as the CSL. A single junction silicon solar cell for example, cannot use materials for the front contact that significantly absorb any light wavelengths in the visible spectrum, as this will result in a drop in efficiency. However, the second (or lower) sub-cell in a tandem cell arrangement relies predominantly on the red or near infra-red portion of the light spectrum to cause excitation. Such relatively long- wavelength light is able to travel through a wider range of materials without being absorbed, than is the case for shorter wavelengths. Thus, the second sub-cell can utilise materials for the silicon-free CSL, which would not be possible for use as charge transport layers in single junction silicon solar cells (i.e. cells not in a tandem configuration).

As discussed above, the CSL is selective to one type of charge carrier. In some embodiments, the CSL may be configured to be a hole transport layer (HTL). The HTL has a high mobility and selectivity for the positively charged holes generated during excitation, while blocking the movement of electrons.

The HTL may be chosen from a group of materials including but not limited to: transition metal oxides, such as MoCh, WO3, V2O5, NiOx, and Q12O; conductive polymers, such as poly(3,4-ethylenedi oxythiophene) polystyrene sulfonate (PEDOT: PSS), poly(3-hexylthiophene-2,5-diyl) (P3HT), poly (3 -alkylthiophene) (P3AT), poly (3 -octylthiophene), Poly[bis(4-phenyl)(2,5,6-trimethylphenyl)amine (PTAA) and mixtures thereof; Cui; copper phthalocyanine (CuPc); and CuSCN. The HTL may be a doped material or a composite material. In some embodiments, the HTL may be chosen from a group of materials including but not limited to: inorganic semiconductors (e.g. transition metal oxides, such as MoCh, WO3, V2O5, NiOx, and Q12O; and Cui; copper phthalocyanine (CuPc); and CuSCN) that are doped with another metal, such as Al (e.g. Al doped NiOx, or Al doped Q12O); organic HTL materials (e.g. conductive polymers, such as poly(3,4- ethylenedioxythiophene) polystyrene sulfonate (PEDOT: PSS), poly(3- hexylthiophene-2,5-diyl) (P3HT), poly (3 -alkylthiophene) (P3AT), poly (3- octylthiophene), Poly[bis(4-phenyl)(2,5,6-trimethylphenyl)amine (PTAA) and mixtures thereof) doped with small molecules, such as LiTFSI (bis(trifluoromethane)sulfonimide lithium salt)) (e.g. LiTFSI doped PTAA). In some embodiments, the doped material may be a mixture of materials, with each material being suitable for use as a HTL. That is, the doped material (or composite material) may be a HTL material doped (or combined) with one or more other HTL materials. Accordingly, in some embodiments, the doped material or composite material may be a mixture of two or more materials selected from the group of materials including but not limited to: transition metal oxides, such as MoO3, WO3, V2O5, NiOx, and Q12O; conductive polymers, such as poly(3,4- ethylenedioxythiophene) polystyrene sulfonate (PEDOT: PSS), poly(3- hexylthiophene-2,5-diyl) (P3HT), poly (3 -alkylthiophene) (P3AT), poly (3- octylthiophene), Poly[bis(4-phenyl)(2,5,6-trimethylphenyl)amine (PTAA) and mixtures thereof; Cui; copper phthalocyanine (CuPc); and CuSCN. For example, the doped material may be CuPc doped P3TH.

As noted above, for some embodiments, the use of transition metal oxides may be advantageous due to their heat-stability and/or solubility characteristics. In some embodiments, the silicon-free CSL may be MoO3 or WO3. Using MoO3 or WO3 for the CSL of the second sub-cell may provide a silicon-free CSL capable of withstanding temperatures as high as 800°C (MoOs) or 1500°C (WO3). High- temperature stable CSLs may enable the use of a wider range of materials in the first sub-cell. For example, the use of CSLs that are stable at higher temperatures may facilitate the use of transition metal oxides for one or more of the carrier- selective transport layers of the first sub-cell. The use of CSLs that are stable at higher temperatures may facilitate the use of transition metal oxides for the lower carrier-selective transport layer of the first sub-cell, such as the use of TiCh as an electron-transport layer for the first sub-cell.

The HTL can be deposited using methods known to those skilled in the art, such as methods including but not limited to solution-processed deposition (the solution method), evaporation methods (thermal or vapor), sputtering methods, and Atomic Layer Deposition (ALD) methods. ALD and sputtering methods may be advantageous for some embodiments. In some embodiments, ALD and sputtering methods may provide preferable process control and compatibility for scaling up the manufacturing process.

In other embodiments, the silicon-free upper CSL between the first sub-cell and the crystalline silicon substrate may be configured as an electron transport layer (ETL). The electron transport layer CSL may have a high mobility and selectivity for negatively charged electrons generated during excitation, while blocking the movement of holes. Suitable ETL materials may be selected from a group including but not limited to: SnCh; TiCh; Nb2Os; Ta2Os; SrTiCh; ZnO and Ceo. In some embodiments, the ETL is formed of a doped material. For example, the ETL may be a doped material such as Al-doped TiCh, Li-doped TiCh, N-doped TiCh, Li-doped SnCh or Ti-doped Ta2Os.

Deposition of the ETL can be accomplished via ALD, sputtering, solution method or electron beam (e-beam) deposition methods. ALD, sputtering and solution method are preferable due to ease of process control, compatibility for scaling up and potentially low cost, particularly for the solution method.

The CSL on the opposite side of the silicon substrate (the lower CSL) may also be a silicon-free CSL. The CSL on the opposite side of the silicon substrate (the lower CSL) may also be a dopant-free, silicon-free CSL. However, in some embodiments, the lower CSL may be a doped, silicon-free CSL. Accordingly, the CSL on the opposite side may be configured as a HTL or ETL as described above. However, in some embodiments, the lower CSL may be a silicon-based CSL. In some embodiments, the lower CSL may be an n-type doped hydrogenated amorphous silicon.

As noted above, the second sub-cell may be configured so that the lower CSL is the ETL, with the upper CSL being the HTL, or vice versa. The configuration of the second sub-cell may be selected based on the relative robustness of the layers to the fabrication conditions that will be employed for the remainder of the tandem cell. Accordingly, the most robust material may be selected for deposition first, with the less robust material being deposited subsequently. In some embodiments, it may be desirable for the most robust CSL to be the upper CSL of the second sub-cell, as it will be more directly subjected to the fabrication conditions used for the first sub-cell.

The second sub-cell may further comprise a first passivating layer located between the crystalline silicon substrate and the silicon-free upper CSL. The first passivating layer performs the critical function of preventing recombination of photogenerated charge carriers at surface defects present in the absorber. For example, the surface of a silicon substrate can have defects such as ‘dangling bonds’. These dangling bonds provide sites where the generated electron-hole pair may recombine, resulting in loss of the charge carriers before they can be separated and made to flow in an external circuit. Preventing such recombination may provide higher efficiencies from the cell. The passivation layer may also be configured such that it does not substantially interfere with the movement of the generated charge carriers to the CSL.

The first passivating layer can be selected from the group including, but not limited to: SiCh, intrinsic amorphous silicon (a-Si: H(i)), SiNx.

In some embodiments, the second sub-cell may comprise a second passivating layer between the crystalline silicon substrate and the lower carrier-selective transport layer. The second passivation layer may be selected from the group including, but not limited to: SiCh, intrinsic amorphous silicon (a-Si: H(i)), SiNx. In some embodiments, the first and second passivating layers may be fabricated from the same material. In further embodiments, the first and the second passivating layer may be formed from different materials.

Passivation layers may be deposited through a variety of techniques such as plasma enhanced chemical vapor deposition (PECVD), ALD, sputtering, spincoating with annealing, thermal oxidation or solution methods. Selection of the deposition method can be based on a variety of factors such as functional requirements, cost etc. For example, the a-Si:H (i) passivation layer can be grown by plasma enhanced chemical vapor deposition (PECVD), ALD or sputtering. Similarly, the SiCh layer may be deposited by solution methods or thermal oxidation and a SiNx passivation layer may be deposited using PECVD.

The thickness of the passivation layer may be selected based on the materials employed. For example, an a-Si:H(i) layer of approximately up to 15 nm thickness may be sufficient to substantially prevent recombination of charge carriers. A suitable SiCh passivation layer may be of approximately up to 5 nm thickness for example. A suitable SiNx layer may be of approximately up to 5 nm thickness. A person skilled in the art will readily appreciate that a range of appropriate materials and fabrication methods may be utilized for forming a suitable passivating layer.

In some embodiments, the passivation function can be performed by the CSL itself. Accordingly, in these embodiments, no discrete passivating layer may be required on the upper and/or lower side of the silicon substrate. In some embodiments, the silicon-free upper carrier-selective transport layer may directly contact the crystalline silicon substrate. In these embodiments, the second (lower) passivating layer may still be provided. In some embodiments, the lower carrier- selective transport layer may directly contact the crystalline silicon substrate. In these embodiments, the first (upper) passivating layer may still be provided. Silicon-free materials suitable for use as the CSL may have intrinsic passivation characteristics. Examples of such materials include TiCh, NbOx, TaOx, GaOx, ZnOx, and CsOx. For example, a TiCh layer used as an ETL for the second subcell can also serve as an efficient passivating contact. That is, the TiCh ETL can directly contact the crystalline silicon substrate, while providing the required passivation properties. Such an arrangement can simplify the cell fabrication, as it eliminates the need for an additional step of depositing a discrete passivating layer. Thus, the use of a passivating CSL can be advantageous, as it may result in further simplification of the fabrication process, potentially leading to associated cost savings. Other similar materials, including those noted above, can also be employed as CSL having intrinsic passivation characteristics.

The second sub-cell comprises a crystalline silicon substrate. The silicon substrate functions as the absorber on which the passivating layer (if used) and the CSL are deposited. A major function of the crystalline silicon substrate is to absorb red/near-infrared light to generate the electron-hole pairs. The generated electrons and holes diffuse/mi grate under the influence of an electric field that is present at the p-n junction, to the CSL. The silicon substrate may be a conductive silicon substrate and the conductivity of the silicon substrate can be tuned via doping. Accordingly, the crystalline silicon substrate may be fabricated from a p-type silicon wafer or an n-type silicon wafer using standard techniques for wafer fabrication. Typical Si wafers employed may have resistivity ranging from 1 ohmcm to 15 ohm cm.

The crystalline silicon substrate may be double-side polished or double side textured. The crystalline silicon substrate may alternatively be one-side polished, with the opposing side textured. Texturing may enable a cell to minimize light reflection and thereby trap a higher proportion of the incident radiation, thus resulting in improved efficiencies. Polishing may be advantageous for fabricating high quality perovskite film with good coverage. During fabrication of the second sub-cell, the upper and/or lower passivating layers may be deposited on the silicon wafer (if used). Then, the CSL layer may be deposited.

The rear or back side of the second sub-cell may include a current collector or electrode to extract the charges collected in the lower CSL and feed them to the external circuit. This electrode may thus provide a pathway for the charge carriers to flow to the external circuit located outside the tandem cell. The electrode may be: Al; Ag; Cu or stacked combinations thereof. The current collector or electrode may be deposited using techniques such as thermal evaporation, screen printing or plating.

The first sub-cell may comprise an absorber layer. As discussed above, the first sub-cell may comprise a high band-gap material that enables it to harvest high energy/low wavelength portion of sunlight. In some embodiments, the absorber layer of the first sub-cell may comprise a perovskite material. In other embodiments, the absorber layer of the first sub-cell may be selected from a group including but not limited to CIGS, quantum dots (e.g. PbS/PbSe), CZTS and organic solar cells.

Perovskites are known for their large bandgap tunability, low materials cost, and simple processing requirements. Thus, the use of perovskite may facilitate production of a cost-effective tandem cell, when used in combination with another low-cost material such as silicon (i.e. the silicon based second sub-cell).

Perovskites may be desirably cost-effective options for the upper sub-cell of tandem photovoltaic cells. A perovskite-based absorber layer may comprise a perovskite material with a formula of ABX3, wherein: A is a cation such as (but is not limited to) methyl ammonium (MA), formamidinium (FA), Cs, Rb, and mixtures thereof; B is a metal such as (but is not limited to) Pb, Sn, Sb, Bi; X is a halide such as (but is not limited to) I, Br, Cl. The composition of the cation A may be a composition in which: the molar percentage of FA ranges from 0% to 100%, MA ranges from 0% to 100%, Cs ranges from 0% to 100%, and Rb ranges from 0% to 25%.

This absorber layer can be deposited via evaporation methods or solution methods.

The first sub-cell may have a configuration of passivating and carrier-selective layers similar to the second sub-cell, although the materials selected can be different. The first sub-cell may further comprise silicon-free carrier selective charge transport layers (CSL-U), These layers may enable transfer of generated charge carriers from the absorber (e.g. perovskite) layer to the external circuit or to an interconnect layer described below. The CSL-U on the upper side of the first sub-cell may be a hole transport layer (HTL-U) or an electron transport layer (ETL-U). Complementarily, the CSL-U on the lower side of the absorber may be an ETL-U or HTL-U respectively.

The HTL-U for the first sub-cell may be (but is not limited to): Spiro-OMeTAD (2,2',7,7'-Tetrakis-9,9'-spirobifluorene); PTAA (Poly[bis(4-phenyl)(2,5,6- trimethylphenyl)amine); Spiro-TTB (2,2',7,7'-Tetra(N,N-di-p-tolyl)amino-9,9- spirobifluorene); CuSCN; NiOx; and CuMCh wherein M is Ga, Al, or Cr. The HTL can be deposited using methods including but not limited to the solution method, evaporation method, and the sputter method.

The ETL-U for the first sub-cell may further be selected from a group including, but not limited to, Nb2Os, Ta2Os, SrTiCh, SnCh, TiCh and Ceo. The ETL may be deposited via ALD, solution processing or sputtering methods.

In some embodiments, deposition of the CSL-U may comprise: depositing an initial sub-layer; and depositing an upper sub-layer. Such as deposition method may be advantageous when using solution-based deposition methods. In embodiments in which the layer underlying the CSL-U may be damaged by solvent exposure, the initial layer may be first deposited using a low-solvent method. For example, in some embodiments, the initial sub-layer may be deposited by ALD. The ALD sub-layer may be suitably dense to block permeation of the solvent used for depositing the upper sub-layer onto the underlying layer.

As described further below, in some embodiments, the silicon-free upper carrier- selective transport layer of the second sub-cell may directly contact the first subcell. In particular, the silicon-free upper CSL may directly contact the lower CSL- U of the first sub-cell. Embodiments in which deposition of the CSL-U may comprise: depositing an initial sub-layer; and depositing an upper sub-layer, may be particularly advantageous for fabricating embodiments of the tandem photovoltaic cell in which the silicon-free upper CSL directly contacts the first sub-cell. As these embodiments do not include an interconnecting layer, the silicon-free upper CSL may be more exposed to the deposition conditions used for the CSL-U. Thus, depositing the initial sub-layer of the CSL-U (e.g. by a method such as ALD) may assist in minimising or reducing damage to the silicon-free upper CSL.

In embodiments including an interconnecting layer, it may be advantageous for deposition of the CSL-U to comprise: depositing an initial sub-layer; and depositing an upper sub-layer. Even when the interconnecting layer is present, depositing the initial sub-layer of the CSL-U (e.g. by a method such as ALD) may assist in minimising or reducing damage to the silicon-free upper CSL during fabrication of the first sub-cell.

As a non-limiting example of this method of depositing the CSL-U, in some embodiments, the second sub-cell may have a silicon-free upper CSL configured as a HTL. This silicon-free upper CSL may be formed of MoCh. The use of H2O as a solvent during the fabrication of the first sub-cell may cause damage to the MoOs HTL layer. The initial sub-layer may be deposited as a protective layer that reduces or prevents contact with the solvents. In this example, the lower CSL-U of the first sub-cell is configured as an ETL and is formed of SnCh. A thin ALD SnCh layer is employed as the protective layer before another layer of SnCh is deposited using a water-based solution processing step. The ALD SnCh layer may be sufficiently dense as to block the permeation of the water to the MoCh HTL of the second sub-cell. The deposition of the SnCh layer via ALD involves the use of a limited amount of H2O to enable conversion of the Sn precursor to SnCh. However, this amount is typically insufficient to cause any significant damage to the MoOs layer.

ALD of the sub-layer, as well as other layers of the tandem photovoltaic cell can depend on the dosing sequences employed. ALD uses dosing sequences of the precursor material for the layer in question and an oxidant. In some embodiments, a dosing sequence of tl, t2, t3, and t4 may be employed, where tl and t3 refer to the times for the precursor pulse and oxidant pulse, while t2 and t4 refer to the times for purging. Optimisation of the ALD may involve adjusting or selecting the pulse time of the precursor and the oxidant.

Suitable values for tl, t2, t3, and t4 may be 0.1-lseconds (s), 12 s, 0.05-0.5 s, and 12 s, respectively. The times for tl and t2 can be varied to adjust the deposition. In some embodiments, it is particularly preferred for t2 to be about half the duration of tl. Such embodiments may be those in which SnO2 is deposited by ALD.

As noted above, the first sub-cell may be configured so that the lower CSL-U is the ETL, with the upper CSL-U being the HTL, or vice versa. The configuration of the first sub-cell may be selected based on the relative robustness of the layers to the fabrication conditions that will be employed for the remainder of the tandem cell. Accordingly, the most robust material may be selected for deposition first, with the less robust material being deposited subsequently. In some embodiments, it may be desirable for the most robust CSL to be the lower CSL, as it will be more directly subjected to the fabrication conditions used for the remainder of the first sub-cell. This first sub-cell may comprise upper and/or lower passivation layers. Similarl to the second sub-cell, the passivation layer(s) (when used) are deposited between the CSL-U and the absorber layer. The passivating layers may prevent recombination of the generated electron-hole pairs at the surface of the absorber layer.

Different passivation layers may be utilized depending on the type of carrier selective charge transport layer present at that side. For example, the passivation layer between the absorber (e.g. perovskite) layer and ETL-U may be (but is not limited to): polymethyl methacrylate (PMMA)/ Phenyl-C61 -butyric acid methyl ester (PCBM); ethylenediaminetetraacetic acid; 4-Imidazoleacetic acid hydrochloride; ammonium chloride; n-octylammonium bromide; or any combination thereof. These materials may be deposited using techniques such as spin coating and annealing.

On the other hand, the passivation layer between the absorber (e.g. perovskite) layer and HTL-U may be (but is not limited to): polymethyl methacrylate (PMMA); n-Octylammonium Bromide (OABr); octylammonium iodide (OAI); octylammonium chloride (OAC1); butylammonium iodide; butylammo-nium bromide; or phenethylammonium iodide (PEAI). These layers may be deposited by spin coating followed by thermal treatment.

The first sub-cell may also comprise a buffer layer. The buffer layer may be provided to protect the underlying layers of the first sub-cell from damage resulting from the use of a plasma during the top transparent contact deposition through sputtering. In some embodiments in which the first sub-cell is configured with a n-i-p structure, the buffer layer may be selected from a group including, but not limited to, MoOv, WOx, VOx, SnCh, and TiCh. In some embodiments in which the first sub-cell is configured with a p-i-n, the buffer layer material may be selected from a group including, but not limited to SnCh, TiCh, ZnO. The deposition of the buffer layer may be performed via ALD or thermal evaporation methods. The thickness of the buffer layer may range from about 0 to 30 nm. The first sub-cell may further comprise a top contact. The top contact is transparent to light in order for the light to reach the active components located at the bottom of the tandem cell (i.e. the silicon sub-cell). The top contact includes but is not limited to, transparent conductive oxides (such as ITO: indium doped tin oxide, IZO: indium doped zinc oxide, AZO: aluminium doped zinc oxide, ZTO: zinc tin oxide), graphene, Ag nanowire or combinations thereof.

The first sub-cell may also comprise a top electrode. The top electrode can provide a pathway through which charge carriers generated during excitation may flow to an external circuit. The electrode may comprise: Al; Ag; Cu or stacked combinations thereof. The electrode may be deposited using techniques such as thermal evaporation, screen printing or plating.

The first and second sub-cells may be connected through an interconnect layer (ICL) (also referred to herein as an interconnecting layer). The ICL may be referred to as a recombination layer. An ICL may allow electrical connection to be established between the two sub-cells in order to complete the electrical circuit. It may function as a low resistivity layer that allows recombination of charge carriers from the first and second sub-cells. The ICL may be deposited between the first and second sub-cells. Thus, the ICL may be capable of forming an interface with both the sub-cells. Charges from the silicon-free upper carrier- selective transport layer will be transferred to the ICL under the influence of electric field to promote such recombination in the ICL.

The CSL-U on the lower side of the first sub-cell may be connected to the ICL between the two sub-cells. This may allow the charges accumulated on the CSL-U to recombine with charges from the CSL of the upper side of the second sub-cell in the ICL. For example, if the CSL-U is a HTL, then the holes generated during the excitation in the absorber layer will be transferred to the CSL-U and eventually to the ICL where they will combine with electrons that have been generated and gathered by the CSL of the upper side of the second sub-cell. Alternately, if the CSL-U is an ETL-U, then the electrons generated and gathered by it will be able to recombine with holes generated and gathered from the CSL on the upper side of the second sub-cell.

The ICL may be chosen from a variety of materials including but not limited to transparent conductive oxides such as Indium tin oxide (ITO), Indium zinc oxide (IZO), zinc tin oxide (ZTO), alumina doped zinc oxide (AZO). The ICL can be deposited either via sputtering or the solution method. The ICL may, in some alternative embodiments, be in the form of a tunnelling junction layer.

In some embodiments, the first and second sub-cells may be connected directly without the ICL. Thus, in some embodiments, the silicon-free upper carrier- selective transport layer directly contacts the first sub-cell. The direct-contact interface formed between the first and second sub-cells can perform the function of the ICL (i.e. providing a low resistive layer where recombination may occur). Accordingly, the direct-contact interface ideally has low resistivity and allows for a recombination of electrons and holes from the first and second-sub cells.

The direct-contact interface is formed between complementary CSLs. This is critical to promote recombination of holes and electrons at the interface. For example, the HTL/ETL of the first and second sub-cells may be in direct contact with each other. More specifically, the ETL of the first sub-cell may be in direct contact with the HTL of the second sub-cell. Alternatively, the HTL of the first sub-cell may be in contact with the ETL of the second sub-cell to form this interface. Such an interface may not be formed between a HTL of the first sub-cell and the HTL of the second sub-cell (or an ETL of the first sub-cell and an ETL of the second sub-cell). Pairs of CSL-U/CSL that may form a direct-contact interface include, but are not limited to, SnCh/MoCh, SnCh/WCh, SnCh/ViCh, and NiOx/TiCh.

The use of a silicon-free upper CSL in the second sub-cell may be advantageous for forming the direct-contact interface. In some embodiments, the use of a silicon-free, dopant-free upper CSL in the second sub-cell may be advantageous for forming the direct-contact interface. It may also be advantageous to use a dopant-free lower CSL-U, so that in some embodiments the direct-interface is formed by a pair of dopant-free materials. In some embodiments, the upper CSL is a transition metal oxide. In some embodiments, the CSL-U is a transition metal oxide. In some embodiments, the material of the upper CSL has intrinsic passivating characteristics. In some embodiments, the material of the lower CSL- U has intrinsic passivating characteristics.

Without being bound by theory, it may be desirable to select a material for the silicon-free (optionally dopant-free) upper CSL and/or the (optionally dopant- free) lower CSL-U with an interfacial defect density that can be tuned for optimal contact resistance. Tuning may be effected by controlling: the deposition parameters, such as reactor temperature, the deposition rate, precursor species, the precursor purity, and/or film thickness; post-treatment conditions such as temperature, time, atmosphere, UV-treatment may also be controlled to effect this tuning; and/or controlling material stoichiometry. For example, raising the reactor temperature during ALD may increase the doping of the as-deposited CSL. This increase in doping may be beneficial for achieving a low contact resistivity. Additionally, or alternatively, in ALD, by tuning the deposition ratio of the precursor the stoichiometry of the as-deposited CSL may be changed. This change in stoichiometry may change the work function of the material. In some embodiments, as described above, a dosing sequence of tl, t2, t3, and t4 may be employed for ALD, where tl and t3 refer to the times for the precursor pulse and oxidant pulse, while t2 and t4 refer to the times for purging. The times for tl and t2 can be varied to adjust the deposition and it may be particularly preferred for t2 to be about half the duration of tl .

In a third aspect, the present invention provides a photovoltaic system, said system comprising one or more photovoltaic modules wherein the or each photovoltaic module (or at least some of the photovoltaic modules) comprises a plurality of tandem photovoltaic cells in accordance with the first aspect. Some or all of the tandem photovoltaic cells in at least one module are connected in series. Alternatively, or additionally, some or all of the tandem photovoltaic cells in at least one module are connected in parallel. One skilled in the art will appreciate, in view of the disclosure herein, that tandem photovoltaic cells in accordance with the first aspect may be configured into photovoltaic modules in accordance with methods utilised to configure known tandem photovoltaic cells into a photovoltaic module. Thus, in the light of the disclosure herein, known photovoltaic module configurations may be modified to replace the tandem photovoltaic cells therein with tandem photovoltaic cells in accordance with the first aspect of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments will now be described by way of example only, with reference to the accompanying drawings in which:

Figure l is a schematic view of a first variation of the tandem cell according to the present invention.

Figure 2 is a schematic of one embodiment of the first variation of the tandem cell according to the present invention.

Figure 3 is a graph of bias (V) and current density (mAcm ^-2 ) (a current density (J) - voltage (V) curve (a J-V curve)) for an embodiment of the tandem cell in accordance with Figure 2.

Figure 4 is a schematic view of a second variation of the tandem cell according to the present invention.

Figure 5 is a schematic of one embodiment of the second variation of the tandem cell according to the present invention.

Figure 6 is a graph of bias (V) and current density (mAcm' ² ) (a J-V curve) for an embodiment of the tandem cell in accordance with Figure 5. Figures 7a and 7b illustrates the characterization of the SnCb/MoOs interface employed in a tandem cell according to a second variation of the tandem cell according to the present invention.

DESCRIPTION OF ILLUSTRATED EMBODIMENTS

In the following detailed description, reference is made to accompanying drawings which form a part of the detailed description. The illustrative embodiments described in the detailed description, depicted in the drawings and defined in the claims, are not intended to be limiting. Other embodiments may be utilised and other changes may be made without departing from the spirit or scope of the subject matter presented. It will be readily understood that the aspects of the present disclosure, as generally described herein and illustrated in the drawings can be arranged, substituted, combined, separated and designed in a wide variety of different configurations, all of which are contemplated in this disclosure.

Embodiments of the invention according to the first aspect will now be described with reference to Figures 1 and 2.

Disclosed in Figure 1 is a schematic of the tandem solar cell 10 according to a first aspect of the present invention. Figure 2 shows the schematic of a specific embodiment according to the first aspect. The tandem cell 10 comprises a first sub-cell 12 and a second sub-cell 14. The tandem cell 10 may further comprise an interconnecting layer 26 that is located between the two sub-cells. Each sub-cell 12, 14 is able to trap light of different wavelength ranges, thereby enabling higher generation of charge carriers in the tandem cell 10 as a whole.

First and second sub-cells (12,14)

In this example, the first sub-cell 12 comprises an absorber in the form of a perovskite-based material 16. However, it will be appreciated by the person skilled in the art that the principles disclosed herein can be applied to other types of sub-cells, and that the present invention is not limited to the use of a perovskite-based absorber in the first sub-cell. For example, the first sub-cell may include CIGS, quantum dots (e.g. PbS/PbSe), CZTS solar cells or organic solar cells.

The second sub-cell 14 comprises an absorber in the form of a silicon substrate 18.

The second sub-cell 14 is located below the first sub-cell 12. The second sub-cell 14 further comprises a first passivation layer 20a deposited on the upper side of the silicon substrate 18 and a silicon-free upper carrier selective charge transport layer (CSL) 22 deposited above the passivation layer 20a.

During operation of the tandem cell 10, light (such as sunlight) that is incident on the first sub-cell 12 passes through it before reaching the second sub-cell 14. As light passes through the first sub-cell 10, the high energy /low wavelength portion of the light (blue light) is substantially absorbed by the perovskite-based material 16. The portion of light that is not significantly absorbed (i.e. red/near-infrared light) passes through the first sub-cell 12 and reaches the second sub-cell 14. In this manner, the tandem cell 10 utilizes a larger portion of the incident light to enable generation of more charge carriers that can be separated.

Silicon substrate 18

In the illustrated embodiment, the silicon substrate 18 utilized as part of the second sub-cell 14 comprises crystalline silicon (c-Si). There are two types of c-Si available - monocrystalline and polycrystalline silicon. In some embodiments, monocrystalline silicon may be utilized. In some other embodiments, polycrystalline silicon may also be utilized.

The silicon substrate 18 is also conductive. The conductivity is imparted through doping with elements that create either n-type or p-type free charge carriers. By controlling the level of doping, it is possible to tune the level of conductivity in the silicon substrate 18. Such conductive silicon wafers are available commercially. In the illustrated embodiment, the c-Si comprises n-type free charge carriers.

The thickness of the silicon wafers may be in the range of 150 pm - 400 pm. The resistivity of the wafers ranges from 1 - 15 ohmcm.

The silicon substrate 18 may be subjected to a surface preparation treatment, such as a polishing or texturing process. The silicon substrate may be subjected to a surface preparation process to make it double-side polished, double-side textured, or one-side polished and the other side textured. In the illustrated embodiment, the silicon substrate 18 comprises a polished front surface adjacent a first passivation layer 20a and textured rear surface adjacent a second passivation layer 20b (i.e. one-side polished and the other side textured surface).

The silicon substrate 18 is fabricated from high quality silicon wafers which may be obtained from suppliers such as Silchem, Longi etc.

The silicone substrate 18 is thoroughly cleaned to substantially remove any impurities. Impurities can have a significant effect on the performance, especially if they diffuse into the wafer during high temperature processing, or diffuse outwardly into the equipment used for handling the wafers, causing significant issues in a production line. An RCA process may be employed to clean the silicon substrates 18. In some embodiments, the RCA cleaning process may comprise the following protocol: RCAl=10 minutes, 80° C. dip in 5:1 : 1 NH4OH: H2O2: H2O; 1% wt HF dip for 1 min; RCA2=10 minutes, 80° C. dip in 5: 1 :1 HC1: H2O2: H2O; 1% wt HF dip for 1 min. After each step, the wafers may be dipped in deionized water for thorough cleaning before the next step. The cleaned wafers may then be dried with N2.

Carrier selective charge transport layer 22

The silicon-free upper carrier selective charge transport layer (CSL) 22 can be either a HTL or an ETL. In the illustrated embodiment, a HTL composed of MoOs or WO3 is utilized as the CSL. Such a HTL layer will allow holes to be transported through, while blocking out electrons.

The thickness of the HTL can have a significant effect on the function of the layer and thus the performance of the tandem cell. Accordingly, the thickness of this layer may be controlled. This is typically conducted by controlling the conditions during deposition of the layer. For example, the thickness is directly dependent upon deposition time and rate. The deposition temperature also affects the deposition rate. Generally, the higher deposition temperature, the thinner the film with the other conditions kept the same. Thus, by choosing longer deposition times and/or higher deposition rates (e.g. by lowering deposition temperature), a thicker, denser layer may be deposited. In some embodiments, HTL thicknesses in the range of 5 to 100 nm are utilized. The thickness may be selected depending on the material being deposited. For MoO3 and WO3 layers, a deposition rate of 0.1 A/s to 0.5 A/s may be desirable for achieving the selected thickness during deposition using the thermal evaporation technique.

The illustrated embodiment includes a first passivation layer 20a. The deposited HTL layer completely covers the surface area of the passivation layer 20a it is deposited over.

In other embodiments, the CSL 22 may be an ETL.

Passivation layers 20a, 20b

The second sub-cell 14 comprises a first passivation layer 20a that is in contact with the front side of the silicon substrate 18. The first passivation layer 20a prevents recombination of the generated electron-hole pair at the surface of the silicon substrate 18. The passivation layer is intrinsic in nature (i.e. nonconducting). Thus, the thickness of the layer may be controlled such that it permits movement of electrons/holes through to the CSL 22, while sufficiently covering the front surface of the silicon substrate 18 to prevent recombination. In embodiments of the present invention, the passivation layer can be chosen from a variety of materials and the layer thickness can be controlled within a specific range by controlling the deposition conditions. For example, to fabricate an a- Si:H(i) passivation layer, a temperature range of 150°C to 200°C is utilized in the process, using a PECVD method. Similarly, SiCh that is made via a chemical method requires a temperature of 75°C to 90°C and a time of 15 to 60 minutes to grow an oxide layer of desired thickness (0.5 - 5 nm). On the other hand, SiO2 deposited by thermal oxidation requires a temperature of 550°C to 1100°C and a deposition time ranging from 5 mins to 120 mins.

Other factors may also be important in ensuring a good quality layer is deposited. For example, the as-deposited passivation layer is usually amorphous and pinhole- free. Typically, the passivation layer is amorphous as it is ultrathin. It can be difficult to provide a crystallised ultrathin layer. It can be desirable to provide a pinhole-free passivation layer. Pinholes are defects, enabling the direct contact of the CSL and the substrate, thus resulting in high recombination.

In the illustrated embodiment, an a-Si:H (i) layer is utilized as the first passivation layer 20a for the silicon substrate 18.

In the illustrated embodiment, the second sub-cell 14 comprises a second passivation layer 20b that is deposited on the rear side of the silicon substrate 18. This layer, like layer 20a, prevents loss of charge carriers through surface recombination at the rear side of the silicon substrate 18. Similar considerations apply while forming the layer 20b on the rear side of the silicon substrate 18 as for forming layer 20a.

In the illustrated embodiments, both the passivation layers 20a and 20b are formed simultaneously on both sides of the silicon substrate 18, in a single process.

When a-Si:H(i) layers are used as the passivation layers 20a and 20b (as in the illustrated embodiment), the a-Si:H(i) layers can be grown by Plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD) or sputtering. The a-Si:H(i) layer may be deposited with a temperature in the range of 150°C to 250°C when using the PECVD method. The thickness of each layer may be up to 15nm.

In some other embodiments, SiCh passivation layer(s) may be employed. The SiCh can be deposited using known chemical or thermal oxidation methods. The thickness of suitable SiCh passivation layers may be up to 5nm.

For SiCh made with the chemical method, the oxide is fabricated by immersing silicon sub-cell in 68 wt% nitric acid solution at ~90 °C for 30 minutes, to produce an approximately 1.4 nm-thick SiCh passivation layer. The duration of the immersion may be in the range of 15 mins to 60 mins, to achieve varying passivation layer thicknesses.

For SiCh passivation layers fabricated via thermal oxidation, the layer is deposited at a temperature ranging from 550°C to 1100°C. The duration of the deposition may be in the range of 5 mins to 120 mins.

In some other embodiments, SiNx passivation layer(s) may be employed. The SiNx layer can be grown by means of PECVD or ALD. The SiNx thickness may be in the range of 1-5 nm.

It can be ensured that the desired passivation layer is formed on both sides of the silicon sub-cell by exposing both sides of the silicon substrate 18 to the deposition chamber during the preparation of the passivation layer. In other words, the process is optimized such that simple exposure of both sides will result in the formation of a substantially identical passivation layer on both sides.

Interconnect layer 26

As described earlier, the first and second sub-cells 12, 14 are connected together via an interconnecting layer (ICL) 26 as shown in Figuresl and 2. ICL 26 may be a transparent, conducting layer with low resistivity that enables recombination of holes and electrons from the first and second sub-cells. ICL 26 can be selected from a variety of Transparent Conducting Oxides (TCO) such as Indium tin oxide (ITO, as for Figure2), indium zinc oxide (IZO), Zinc Tin Oxide (ZTO), Alumina doped zinc oxide (AZO).

In alternative arrangements, the ICL may be in the form of a tunnelling junction layer.

Deposition parameters for the ICL 26 may be controlled to control the thickness, conductivity and optical properties of the layer. For example, the thickness of the ICL is preferably kept low to ensure high transparency (whilst still maintaining full coverage of the interface between the sub-cells). If the ICL 26 is not transparent to red/near-infra-red light, then the underlying second sub-cell may not receive enough light to cause sufficient excitation of charge carriers. This will directly impact the efficiency of the tandem cell 10. Similarly, if the thickness of the ICL 26 is insufficient, then it may place a limit on the efficiency of charge carrier recombination, thereby potentially affecting the overall performance of the tandem cell 10. The thickness can be adjusted as required by controlling the deposition parameters and any subsequent post treatment conditions. For example, in RF sputtering, it is possible to control the power from 20 W to 100 W and subsequent heat treatment can be performed at 100 to 200°C for a time of 5 to 30 minutes. Deposition time can be controlled to control the ICL thickness. The ICL 26 also needs to have high conductivity for enabling efficient charge carrier recombination. Conductivity of the ICL 26 can be controlled by controlling the target composition and the deposition environment (e.g. deposition atmosphere). The deposition conditions of the ICL 26 can also cause damage to the passivation of the second sub-cell, particularly where sputtering processes are employed for the ICL. Such damage can be avoided or minimized by reducing the deposition power. Any such damage may also be repaired through post-treatment procedures such as heat-treatment.

In the illustrated embodiment of Figure 2, the ICL 26 is fabricated from a TCO.

The TCO layer thickness may range from 2 nm to 80 nm. The TCO may be deposited with a sputter method or a solution method. For the sputter method, the TCO can be deposited using RF or DC mode. After sputtering, the second sub-cell will receive heat treatment for 5 mins to 15 mins at temperature in the range of 100 to 200 °C. The power of the sputtering may range from 20 W to 100 W.

For solution processed TCO, the nanoparticles of the TCO range from 20 nm to 100 nm. The TCO nanoparticle solution is spin-coated on the substrate at a rate in the range of 1000 rpm/s to 6000 rpm/s. The substrate is then heated to a temperature in the range of from 50 °C to 150 °C.

Electron transport layer 24

The second sub-cell 14 also includes a lower carrier selective charge transport layer 24. In the illustrated embodiments, the layer 24 in the form of an electron transport layer (ETL). This layer 24 extracts the charges of opposite polarity to those extracted by the upper CSL 22. For example, when the CSL 22 is a HTL that is selective to holes, the lower carrier selective layer 24 is selective to electrons. If the upper CSL 22 were an ETL, then the lower carrier selective layer 24 would be a HTL that is selective only to holes.

The lower CSL layer 24 may be a silicon-free (optionally dopant-free) charge transport layer.

In the illustrated embodiment of Figure 2, the ETL 24 is fabricated from TiCh. In some embodiments, including the illustrated embodiment, the thickness of the electron transport layer may be in the range of 1 nm to 100 nm.

The electron transport material 24 can be deposited with e-beam deposition, ALD, or sputter methods. For ALD of TiCh, precursors include, but are not limited to TiCh, Titanium isopropoxide (TTIP), tetrakis-dimethyl-amido titanium (TDMAT). The reactor temperature ranges from 50°C to 250°C. Oxidants may include H2O and oxygen. For ALD TiCh, the TiCh pulse time ranges from 0.05 s to 3 s. The H2O pulse time ranges from 0.05 to 3 s. Between each precursor pulse, the purge time ranges from 0.5 s to 20 s, with a N2 gas flow rate in the range of 100 seem to 500 seem.

In another embodiment, the ETL 24 may be fabricated from a-Si:H(n) layers.

Electrode layer 34

The second sub-cell 14 also comprises an electrode layer 34 that is connected to the ETL 24 described above. In particular, in the illustrated embodiment of Figure 2, between the TiCh layer 24 and an electrode of the electrode layer 34, an ultrathin LiF layer is deposited, whichmay have a thickness of l-5nm.

This ultrathin layer enables electrons (or holes) to be transferred away from the tandem cell 10 to an external circuit (not shown) more efficiently, through better energy alignment. The electrons travelling in the external circuit will eventually reach the electrode layer and associated charge transport layer in the first sub-cell 12, where they recombine with the holes generated in the first sub-cell 12.

The tandem cell 10 is also provided with an electrode as part of the electrode layer 34, on the rear side (i.e. the bottom of the second sub-cell 14). The electrode is provided to extract the current to the circuit. The electrode may comprise Al (as shown in Figure 2), Ag, Cu or a stack of one or more of these metals. The thickness of the electrode may range from 100 nm to 3000 nm.

The electrode deposition method includes but is not limited to thermal evaporation, screen printing, plating, etc.

First sub-cell 12

The first sub-cell 12 of the tandem cell 10 is designed to absorb the high energy/low wavelength portion of the incident light and is thus located on top of the second sub-cell 14. The structure of the first sub-cell 12 is similar to that of the second sub-cell 14, as described above. The first sub-cell 12 in the illustrated embodiments utilizes a perovskite-based absorber 16 to absorb the high energy /low wavelength portion of incident light. This layer is conductive, and the conductivity can be adjusted by composition adjustment, process control to modify crystallization parameters, material doping, film morphology and post-treatment conditions, for example.

The first sub-cell 12 has passivation layers (not shown) and carrier selective charge transport layers 28 and 30 deposited on the passivation layers to extract charge carriers generated during excitation. The layers 28 and 30 perform a function similar to layers 22 and 24 of the second sub-cell 14. However, the nature of materials used for layers 28 and 30 may be different from that for layers 22 and 24. For example, in the illustrated embodiment of Figure 2, the layer 28 which is an ETL, is fabricated from SnCh while layer 30, which is an HTL, is fabricated from PTAA. The SnCb layer of the illustrated embodiment is a dopant free layer.

For the ETL 28, the layer material may be selected from the group consisting of SnCh, TiCh, Nb2Os, Ta2Os, SrTiCh, ZnO and Ceo. The electron transport layer 28 can be deposited via ALD, the solution method, or the sputtered method for example. Prior to fabrication of the first sub-cell 12, the second sub-cell 14 and the interconnect layer 26, which is the substrate for the ETL 28 of the first subcell, receives UV-Ozone treatment for a duration in the range of 1 min to 120 mins.

To deposit SnCh as the ETL 28 of the first sub-cell 12, with the ALD method, the deposition temperature ranges from 80 °C to 180 °C. The TDMASn pulse ranges from 50 ms to 15 s, and the H2O pulse ranges 50 ms to 15 s. The purge between each pulse ranges from 1 s to 25 s. The number of deposition cycles ranges from 10 to 400. The N2 flow ranges from 100 seem to 500 seem. The SnCh may receive post-treatment annealing in the range from 50 °C to 180 °C for 1 min to 60 mins.

For SnCh made from SnCh nanoparticles, the SnCh solution may be spin-coated on the substrate. The spinning speed ranges from 1000 rpm to 8000 rpm. The film may be annealed at the temperature ranges from 50 °C to 200 °C. The annealing may be for 10 mins to 120 mins.

As an alternative embodiment, for TiCh deposited with ALD, the TiCh pulse ranges from 10 ms to 15s, and the H2O pulse ranges 10 ms to 1 5s. The purge between each pulse ranges from 1 s to 25 s. The deposition cycles range from 10 to 400. The N2 flow ranges from 100 seem to 500 seem. The TiCh receives posttreatment in the range from 50 °C to 180 °C for 1 min to 120 mins.

The passivation layers for the first sub-cell 12 (not illustrated) may comprise different materials in order to achieve passivation on both sides of the perovskite layer 16. The passivation layer may be fabricated on both sides of the perovskite layer outlined below.

The passivation layer between the perovskite and the ETL 28 may include PMMA/PCBM, ethylenediaminetetraacetic acid, 4-Imidazoleacetic acid hydrochloride, ammonium chloride, n-octylammonium bromide or combinations thereof. The passivation solution concentration may range from 0.01 mg ml ^-1 to 10 mg ml ^-1 , and may be spin-coated on the substrate with the speed in the range from 500 rpm/s to 8000 rpm/s. The substrate may then be annealed at a temperature in the range from 80 °C to 180 °C for 3 mins to 60 mins.

The perovskite film (the absorber layer 16) is deposited after the lower substrate is fully cooled. The thickness of the perovskite layer can be adjusted by controlling the deposition conditions. For example, thickness in the range of 100 nm to 1500 nm may be achieved. The perovskite layer can be prepared by the evaporation method or the solution method.

For solution-processed perovskite, the precursor concentration may range from 0.5 M to 1.5 M. The perovskite solution is spin-coated on to a substrate with one- step or two steps. For the one step method, the perovskite may be spin-coated at a rate in the range of 1000 rpm/s to 8000 rpm/s. For the two-step spin-coating process, the first step may have a spin-coating speed of 1000 rpm/s to 3000 rpm/s with ramping of 100 rpm/s to 500 rpm/s for the time range of 5 s to 20 s. The second step has a spin-coating speed in the range from 1000 rpm/s to 8000 rpm/s, with the ramping of 100 rpm/s to 2000 rpm/s for 5-40 s. A chlorobenzene dripping process occurs 2-30 s before the spin-coating process ends. Chlorobenzene dripping volume may be in the range of 50 pl to 300 pl for a substrate size of 1.2cm x 1.5cm.

The perovskite film may be annealed at a temperature in the range of 95 °C to 180 °C, for 10 min to 120 min.

Next, the passivation layer between the perovskite layer 16 and the carrier selective charge transport layer 30 (the hole transport material) is deposited. The passivation layer may be polymethyl methacrylate (PMMA), n-Octylammonium Bromide (OABr), octylammonium iodide (OAI), octylammonium chloride (OAC1), butylammonium iodide, butylammo-nium bromide, phenethylammonium iodide (PEAI). The passivation layer may be spin-coated on the perovskite substrate with a film thickness from 0.1 nm to 20 nm. The passivation layer is annealed at a temperature in the range from 80 °C to 160 °C for 10 min to 60 mins.

The carrier selective charge transport layer 30 (the hole transport material) of the perovskite-based first sub-cell 12, may include Spiro-OMeTAD (2, 2', 7,7'- Tetrakis-9,9'-spirobifluorene), PTAA (Poly[bis(4-phenyl)(2,5,6- trimethylphenyl)amine), Spiro-TTB (2,2',7,7'-Tetra(N,N-di-p-tolyl)amino-9,9- spirobifluorene), CuSCN, NiOx, CuM02 (M: Ga, Al, Cr). The HTL 30 may be deposited with methods including but not limited to the solution method, evaporation method, and the sputter method.

For solution processed PTAA, the precursor concentration ranges from 2 mg ml ^-1 to 20 mg ml ^-1 , with dopants, by adding 0.5 pl to 15 pl LiTFSI (concentration in the range of 100 mg ml ^-1 to 300 mg ml ^-1 in acetonitrile) and 2 pl to 15 pl 4-TBP in 1 ml of toluene. The thickness of the PTAA is around 30nm. For Spiro-TTB deposited with thermal evaporation, the thickness ranges from 1 nm to 30 nm. The deposition rate ranges from 0.1 A/s to 15 A/s.

For NiOx deposited by sputtering, 10 nm-50 nm NiOx is deposited at a power in the range from 120W to 220W. The film then receives post-treatment at a temperature in the range from 220 °C to 400 °C for 10 mins to 100 mins with an O2 flow rate in the range of 0.1 L/min to 10 L/min.

The first sub-cell 12 also comprises a buffer layer, a top transparent contact and a top electrode, sequentially deposited onto the charge transport layer 30 (collectively referenced as part of the electrode layer 32).

The buffer layer functions to avoid or minimize damage to the underlying components, for example from plasma damage during sputtering. In the illustrated embodiment of Figure 2, this buffer layer is made up of MoOs and protects the underlying PTAA or Spiro-TTB HTL 30 from the resulting plasma damage.

The buffer layer needs to be transparent to visible as well as near-infra red light as it is located at the top of the tandem cell 10 (i.e. above the first and second subcells 12, 14). Its thickness can range from 1 to 30 nm. As above, this can be controlled by controlling the deposition conditions.

The top transparent contact functions to collect the charge at the electrode, with high conductivity. It is vital that this top contact is optically transparent in order to allow incident light to reach the absorbers located in both sub-cells. The top transparent contact may be formed of a TCO such as Indium tin oxide (ITO), indium zinc oxide (IZO), Zinc Tin Oxide (ZTO), Alumina doped zinc oxide (AZO). The TCO layer thickness may range from 5 nm to 150 nm. The TCO may be deposited with sputter method or the solution method. For sputter method, the TCO can be deposited with RF or DC mode. The power of the sputtering ranges from 20 W to 60 W.

For solution processed TCO, the nanoparticles of the TCO ranges from 20 nm to 100 nm. The TCO nanoparticle solution is spin-coated on the substrate at a rate in the range of 1000 rpm/s to 6000 rpm/s. The substrate is then heated to a temperature in the range of 50 °C to 150 °C.

The top electrode 32 functions in a similar manner to the electrode 34 at the rear side of the silicon substrate 18, in providing a pathway for charge carriers to exit the tandem cell 10 and flow through to an external circuit in order to recombine with oppositely charged carriers generated from the second sub-cell 14.

The performance of tandem cells fabricated according to the embodiment illustrated by Figure 2 is shown in Figure 3. The open circuit voltage (Voc) of around 1.63 V illustrates the feasibility of a high efficiency tandem device using the configuration.

Interconnect free structure

Illustrated in Figures 4 and 5 are embodiments of a second aspect according to the present disclosure and represent a variation of the tandem cell 10. Like reference numbers have been used to denote like parts. The common components may be as described above with reference to Figures 1 and 2. Thus, these components will not be redescribed, and the above description can be taken to apply equally to the embodiment of Figures 4 and 5.

In the embodiments illustrated in Figures 4 and 5, which show a second variation of the tandem cell 10, the cell 10 lacks an interconnect layer 26 (as illustrated in Figures 1 and 2). Thus, in this embodiment, sub-cells 12 and 14 are in direct contact with each other. More specifically, the HTL 22 of the second sub-cell 14 is in direct contact with the ETL 28 of the first sub-cell 12. In other words, the interface formed between the two silicon-free (and dopant-free) carrier selective charge transport layers 22 and 28 now performs the function of the ICL 26 of Figures 1 and 2. Thus, it provides a low resistivity region where recombination of electrons and holes from the first and second sub-cells 12 and 14 may take place.

Such a configuration may lead to simplification of the processing steps required in fabrication of the tandem cell (as the step for deposition of the ICL 26 is no longer required). The elimination of the ICL 26 may also eliminates associated parasitic/absorption losses, thereby improving the efficiency even further.

In the illustrated embodiment of Figure 5, the ETL employed is SnCh and the HTL is MoCh or WO3. The interface formed between these two silicon-free (and dopant-free) layers is controlled by controlling the SnCh deposition process. Without being bound by any particular theory, it is believed that the particular doping density, work function and presence of defects contribute to enabling the direct contact, without a separate interconnect layer. For example, the work functions of the HTL 22 and ETL 28 may be sufficiently similar, such that charges are able to recombine at this interface with the aid of defects existing at the interface.

The performance of tandem cells fabricated according to the embodiment illustrated by Figure 5 is shown in Figure 6. Again, as discussed above, the open circuit voltage (Voc) of around 1.59V indicates the feasibility of a high efficiency tandem device using dopant-free layers in a tandem configuration without an ICL.

Examples

Example Tandem Cells

Tandem cells having a silicon-free upper carrier-selective transport layer were constructed according to the following examples, with two main architectures. The first tandem architecture comprised an interconnect layer for connecting the sub-cells, while the second architecture relied upon surface engineering at the interface of the sub-cells to obviate the need for the interconnect layer.

Example 1 - Silicon/perovskite Tandem cell with Interconnect Layer

Tandem silicon/perovskite cells according to the schematic illustrated in Figure 1 were prepared, having silicon sub-cells with silicon-free (and dopant-free) upper carrier-selective transport layers on the emitter-side of the silicon sub-cell or on both sides of the silicon sub-cell. It will be appreciated by a person of skill in the art that, while Figure 1 illustrates an arrangement where the hole transport layer acts as the emitter, arrangements where the electron transport layer acts as the emitter are also possible.

In particular, tandem cells as shown in the schematic of Figure 1 were produced by the following methods.

Silicon Sub-cell

The silicon sub-cell was prepared using high quality silicon wafers with polished front surface and textured rear surface, having a thickness of 270 pm and a resistivity of 1 - 5 ohmcm. The silicon wafers received RCA cleaning before further processing (RCAl=10 minutes, 80° C. dip in 5: 1 : 1 NFUOH: H2O2: H2O; 1% wt HF dip for 1 min; RCA2=10 minutes, 80° C. dip in 5: 1 :1 HC1: H2O2: H2O; 1% wt HF dip for 1 min.). After each step, the wafers were dipped in deionized water for thorough cleaning before the next step. The cleaned wafers are dried with nitrogen gas.

The cleaned silicon wafers were then passivated by means of a plasma-enhanced chemical vapor deposition (PECVD) process using SiHi and argon Ar gas at 200°C, producing an approximately 6 nm-thick passivation layer of intrinsic, hydrogenated amorphous silicon (a-Si:H).

The emitter for the silicon sub-cell was then deposited by thermal evaporation of either a molybdenum or tungsten oxide using an Angstrom evaporator at a deposition rate of 0.1 A/s under a vacuum of 8 * 10 ^-7 torr, producing an approximately 7.5 nm-thick layer on an upper side of the sub-cell. This was followed by preparation of an electron transport layer over the passivation layer of the opposing side of the silicon sub-cell. The electron transport layer was prepared by an initial deposition of a 5nm TiCh layer by the ALD method (TFS200, BENEQ), using a titanium tetra-isopropoxide (TTIP) precursor. An ~1 nm LiF and~100 nm Al stack was then evaporated on top of the TiCh layer using LiF powder and Al pellets respectively, without breaking vacuum, using an Angstrom evaporator.

In an alternative arrangement, n-type doped hydrogenated amorphous silicon layers may be deposited in a PECVD reactor at 200 °C with phosphine gas added to the silane/hydrogen mixture. ITO (150 nm thickness) and silver (100 nm thickness) are then sputtered over the full back side area of the silicon sub-cell.

Interconnect Layer

Indium tin oxide (ITO) was sputtered using a radio frequency (RF) source maintained at 30 W under an Argon plasma. The chamber pressure was maintained at 1.5 mtorr during deposition. By depositing for 1 hour, the resultant ITO thickness was ~40 nm.

Perovskite Sub-cell

The electron transport layer for the perovskite sub-cell was deposited onto the interconnect layer by thermal ALD (TFS200, BENEQ) of Tetrakis(dimethylamido)tin(IV) precursor (TDMASn) using nitrogen purge gas (N2), to deposit a 15 nm thick SnO2 film. The precursor temperature was set to 60 °C, while the reactor temperature was set to 100°C, with H2O used as the oxidant. The chamber nitrogen flow was set to 200 standard cubic centimeters per minute (seem). Each ALD cycle consisted of a 500 ms pulse of TDMASn, followed by purge for 13s, and then a 200 ms pulse of H2O followed by 13s purge. The purge was under a constant flow (300 seem) of research-grade nitrogen gas.

On top of the ALD SnO2 layer, another SnO2 thin film based on a diluted SnO2 nanoparticle solution (SnO2 stock colloidal dispersion: deionized (DI) water = 1 :5) was deposited. The ALD SnO2 coated Si sub-cell was treated with Ultraviolet-Ozone Surface Treatment (20 pW/cm ² at distance of 100 cm) for 20 min. The SnO2 colloidal dispersion was purchased from Alfa Aesar, with pH 10.5-12.0, viscosity 5-10cps. For a 1.2cm* 1.4cm substrate, 60 uL SnO2 nanoparticle solution was used. The SnO2 nanoparticles were spin-coated onto the substrate at a speed of 4000 rpm for 30s, followed by annealing at 60 °C for 20 min in ambient air.

The perovskite sub-cell was prepared with a stoichiometry of Cso.o5Rbo.o5FAo.765MAo.135PbI2.55Bro.45, from a precursor solution containing 1.2 M Pbh, 1.1 M formamidinium iodide (FAI), 0.20 M PbBn, 0.20 M MABr, 0.091 M CsI, and 0.039 M Rbl in 1 ml of anhydrous N,N'-dimethylformamide (DMF)/dimethyl sulfoxide (DMSO) (8:2, v/v). Prior to perovskite film deposition, the Si sub-cell received 20 min UVO treatment after the SnCh layer deposition. The multiple-cation perovskite precursor solution was then deposited by spin coating at 2000 rpm with a ramp rate of 200 rpm s ^-1 for 10 s, followed by 4000 rpm with a ramp of 1000 rpm s ^-1 for 25 s. During the second step, -100 pl of chlorobenzene was poured on the spinning substrate 5 s before the end of the program. The film was then heated on a hot plate at 100 °C for 30 mins.

The hole transport material (emitter) for the perovskite sub-cell was fabricated by spin-coating a poly(triaryl amine) (PTAA) solution at 3000 rpm for 30 s with an acceleration rate of 3000 rpm s ^-1 . The PTAA solution consisted of PTAA (10 mg ml ^-1 ) with an additive of 7.5 pl of Lithium bis(trifluoromethanesulfonyl)imide (LiTFSI) in acetonitrile (170 mg ml ^-1 ) and 4 pl of 4-tert-Butylpyridine (4-TBP) in 1 ml of toluene.

A buffer layer was then applied over the hole transport material, consisting of an approximately 10 nm thick layer of MoOx deposited by thermal evaporation, at a rate of 0.05 nm s ^-1 under a high vacuum of 8 * 10-7 torr. The buffer layer serves to protect the hole transport material from damage resulting subsequent sputtering processes.

The front contact for the tandem cell was then fabricated by sputtering an -40 nm thick layer of IZO onto the MoOx. The sputtering was performed for 60 min with 30 W of RF power under an Ar plasma, with a chamber pressure of 1.5 mtorr. To complete the electrode layer of the tandem device, gold (Au) fingers and busbars were deposited onto the front contact using thermal evaporation through a shadow mask. The Au was deposited to a thickness of approximately 200 nm in a grid pattern. The spacing between the fingers was 1mm. The width of the gold grids was around 35-55 nm.

Example 2 - Silicon/perovskite Tandem cell without Interconnect Layer

Tandem silicon/perovskite cells according to the schematic illustrated in Figure 4, without an interconnect layer between the silicon and perovskite sub-cells were also prepared. As for Example 1, the silicon sub-cells were again prepared with silicon-free (and dopant-free) upper carrier- selective transport layers on the emitter-side of the silicon sub-cell, or on both sides of the silicon sub-cell. It will be appreciated by a person of skill in the art that, while Figure 4 illustrates an arrangement where the hole transport layer acts as the emitter, arrangements where the electron transport layer acts as the emitter are also possible.

In particular, tandem cells as shown in the schematic of Figure 4 were produced using the methods outlined for Example 1 above, but without the step of depositing the interconnect layer onto the hole transport material of the silicon sub-cell.

Silicon Sub-cell

The silicon sub-cell was again prepared using high quality silicon wafers, followed by passivation of both major faces of the cell. Passivation was achieved by means of a plasma-enhanced chemical vapor deposition (PECVD) process at 200°C, producing an approximately 6 nm-thick passivation layer of hydrogenated amorphous silicon (a-Si:H).

The emitter for the silicon sub-cell was then deposited by thermal evaporation of a molybdenum oxide (MoCh powder with a purity of 99.999%) using an Angstrom evaporator at a deposition rate of 0.1 A/s under a vacuum of 8 - 10 ^-7 torr, producing an approximately 10 nm-thick layer on an upper side of the sub-cell. This was followed by preparation of an electron transport layer over the passivation layer of the opposing side of the silicon sub-cell. The electron transport layer was prepared by an initial deposition of a thin TiCh layer by the atomic layer deposition (ALD) method (TFS200, BENEQ), using a titanium tetra- isopropoxide (TTIP) precursor. An ~1 nm LiF and ~100 nm Al stack was then evaporated on top of the TiCb layer, without breaking vacuum, using an Angstrom evaporator.

In an alternative arrangement, n-type doped hydrogenated amorphous silicon layers may be deposited in a PECVD reactor at low temperatures (i.e. <200 °C) with phosphine gas added to the silane/hydrogen mixture. Indium tin oxide (ITO) (150 nm thickness) and silver (100 nm thickness) are then sputtered over the full back side area of the silicon sub-cell.

Interconnect-free Contact

In order to optimise the contact behaviour between the silicon and perovskite subcells without employing an ITO interconnect layer, tests were conducted on the contact behaviour between WO3/SnO2 and MoO3/SnO2 layers (i.e. the silicon subcell hole transport layer and the perovskite electron transport material). Initial testing including studying the behaviour with highly-doped p-type-Si sub-cells, where MoO3 or WO3 was first deposited on the highly-doped p-type-Si wafer (resistivity of <0.001 ohmcm), and then covered with a SnO2 layer by atomic layer deposition. Silver electrodes were then deposited for the contact measurement.

To achieve low-resistivity contacts for interconnect-free tandem cells, based on silicon substrate sub-cells, with a silicon-free upper carrier-selective transport layer, modifications were made to the SnCb layer (the perovskite electron transport material), by modifying the ALD process.

Tetrakis(dimethylamino)tin(iv) at 55 °C and H2O at 25 °C were used as precursors for SnO2-x fabrication. The temperature of the ALD chamber was set to 100 °C. Dosing sequences tl, t2, t3, and t4 where employed, where tl and t3 refer to the times for precursor pulse and oxidant pulse, while t2 and t4 refer to the times for purging. Suitable values for tl, t2, t3, and t4 were found to be 0.5 s, 12 s, 0.1-0.5 s, and 12 s, respectively. The deposition rate was estimated to be 0.12 nm per cycle. A suitable layer of ALD SnCh-x was deposited in 150 cycles.

In arrangements where a WCh/SnCh contact was employed, three conditions were tested with t3 of 0.1s (condition 1), 0.2s (condition 2) and 0.5s (condition 3). Testing results are shown in Figure 7a. All three conditions lead to relatively low contact resistivity values, which were measured to be 0.106 0hmcm2, 0.107 Ohmcm ² and 0.115 Ohmcm ² respectively. It was found that such low resistivity will be beneficial for high efficiency tandem cells, and would allow the removal of the interconnect layer from the tandem structure.

For arrangements having the MoCh/SnCh contact, t3 of 0.2s was tested and resulted in low resistivity of 0.122 Ohmcm ² , as shown in Figure 7b. Such low resistivity values were found to allow removal of the ITO interconnect layer between the silicon and perovskite sub-cells.

Photovoltaic performance of Si/perovskite tandem solar cell

Tandem devices were fabricated according to processes shown for Examples 1 and 2, and measured for their photovoltaic performance. High V _oc of -1.63 V and -1.59V were achieved for the interconnect and interconnect-free tandem respectively, which is significantly higher than that obtained for either a singlejunction silicon solar cell (-0.7V) or perovskite solar cell (~1.1V).

High Voc may be a significant metric for evaluating the efficient operation of tandem photovoltaic cells.

Variations and modifications may be made to the parts previously described without departing from the spirit or ambit of the disclosure. In the claims which follow and in the preceding description of the invention, except where the context requires otherwise due to express language or necessary implication, the word “comprise” or variations such as “comprises” or “comprising” is used in an inclusive sense, i.e. to specify the presence of the stated features but not to preclude the presence or addition of further features in various embodiments of the invention.

It is to be understood that, if any prior art is referred to herein, such reference does not constitute an admission that the prior art forms a part of the common general knowledge in the art, in Australia or any other country.