TEST DEVICE AND TEST METHOD

Title:

TEST DEVICE AND TEST METHOD

Document Type and Number:

WIPO Patent Application WO/2007/129386

Kind Code:

A1

Abstract:

There is provided a test device for accurately judging the state of an electronic device employed for source synchronous clocking. A first variable delay circuit (210) of the test device delays a data signal outputted from a device (100) under test by a specified time and outputs it as a delayed data signal. A second variable delay circuit (220) delays a clock signal indicating the timing for acquiring the data signal by a specified time and outputs it as a first delayed clock signal. The delay amounts of these variable delay circuits are set by a first delay adjustment unit (300). A third variable delay circuit (270) delays a clock signal outputted from the device (100) under test by a specified time and outputs it as a second delayed clock signal. A fourth variable delay circuit (285) delays a reference clock by a specified delay amount and supplies it to a first selection unit (280).

Inventors:

AWAJI TOSHIAKI (JP)
SEKINO TAKASHI (JP)
NAKAMURA TAKAYUKI (JP)

Application Number:

PCT/JP2006/309097

Publication Date:

November 15, 2007

Filing Date:

May 01, 2006

Export Citation:

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Assignee:

ADVANTEST CORP (JP)
AWAJI TOSHIAKI (JP)
SEKINO TAKASHI (JP)
NAKAMURA TAKAYUKI (JP)

International Classes:

G11C29/00; G01R31/26; H01L21/66; H03K5/13

Foreign References:

JP2001201532A	2001-07-27
JP2001356153A	2001-12-26
JP2002025294A	2002-01-25
JP2003121501A	2003-04-23
JP2005285160A	2005-10-13
JP2002251317A	2002-09-06

Other References: