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Title:
TESTING DEVICE AND TESTING METHOD
Document Type and Number:
WIPO Patent Application WO/2012/004834
Kind Code:
A1
Abstract:
A synchronization-pattern generation unit (12) generates a synchronization pattern (SYNC_PAT) that a clock reproduction unit (54) in a DUT needs in order to maintain an external link. A gate-signal generation unit (16) generates a gate signal (FGATE) that is asserted during a period during which a vector pattern (VECT_PAT) should be supplied to the DUT. In a first mode, a pattern selection unit (18) outputs the vector pattern (VECT_PAT) while the gate signal (FGATE) is asserted and fixes the output level while the gate signal is negated. In a second mode, the pattern selection unit (18) outputs the vector pattern (VECT_PAT) while the gate signal (FGATE) is asserted and outputs the synchronization pattern (SYNC_PAT) while the gate signal is negated.

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Inventors:
TSUTO MASARU (JP)
Application Number:
PCT/JP2010/004444
Publication Date:
January 12, 2012
Filing Date:
July 07, 2010
Export Citation:
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Assignee:
ADVANTEST CORP (JP)
TSUTO MASARU (JP)
International Classes:
G01R31/28
Foreign References:
JPH11264857A1999-09-28
JP2008028628A2008-02-07
Attorney, Agent or Firm:
MORISHITA, SAKAKI (JP)
Sakaki Morishita (JP)
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