FIELD OF THE INVENTION:

The invention relates to integrated circuit manufacturing technology and more particularly to methods for fabricating readout chips for use in sensor chip assemblies (SCA's).

BACKGROUND OF THE INVENTION:

Sensor Chip Assemblies are key components in Infrared (IR) detection systems. However, a significant problem exists for the current sensor chip assemblies that include silicon readout chips which are mated to, or hybridized with, Group II-VI material IR detectors, such as those comprised of HgCdTe. Due to the significant difference in the coefficient of thermal expansion of Si and HgCdTe, it has been found that these assemblies are unable to survive a large number («1000) of thermal cycles between room temperature and operating temperature («77K) . One typical failure mode results in a deterioration of the electrical conductors, such as indium bumps, that are used to hybridize the readout chip to the detector chip.

The failure of SCAs as a result of thermal cycling has heretofore impeded the use of HgCdTe direct hybrid SCAs in production programs.

it is known to make three-dimensional circuits in bulk silicon and thin layers of silicon bonded thereto as described, for example, by Hayashi et. al. in a paper entitled "Cumulatively Bonded IC Devices Stacking Thin Film DUAL-CMOS Functional Blocks" presented at the 1990 Symposium on VLSI Technology.

As was noted above, it has been found that the SCA's tend to fail because the silicon readout chips and the detector

chips have different thermal expansion coefficients. Thus, the use of three-dimensional, same material circuits a known from Hayashi et.al. is not helpful because of th mismatch in thermal expansion coefficients between th silicon of the readout chip and the detector material.

It is therefore an object of the invention to provide a integrated circuit assembly which overcomes the problem o failure due to thermal cycling.

It is another object of this invention to provide practical, inexpensive method for adjusting the effectiv thermal expansion coefficient of a readout integrate circuit assembly.

SUMMARY OF THE INVENTION

The foregoing and other problems are overcome and th objects of the invention are realized by a chip assembl for hybridization, or bump bonding, with another devic having a determined thermal expansion characteristic, th assembly comprising a silicon thin film circuit bonded t a substrate of a material selected so as to match th thermal expansion characteristic of the readout chi assembly to the thermal expansion characteristic of th other device.

In the preferred embodiment, the device is a radiatio detector comprised of a Group II-VI material, such a HgCdTe.

In another aspect of the invention there are provided methods for manufacturing a chip assembly. A first method, referred to herein as a thin film transfer method, includes the steps of providing a bonded silicon wafer whic includes a thin layer of silicon on a silicon substrate; forming a circuit in the thin silicon layer; forming a least one electrical feedthrough in the thin silicon layer;

bonding the thin silicon layer, including the circuit, to a selected substrate comprising a material selected for thermally matching the chip assembly to another material to be hybridized therewith; and thereafter removing the silicon substrate.

A second method, referred to herein as a double transfer method, includes the steps of providing a bonded silicon wafer which includes a thin layer of silicon on a silicon substrate; forming a circuit in the thin silicon layer; bonding the thin silicon layer, including the circuit, to a selected temporary carrier substrate; removing the silicon substrate; bonding the thin silicon layer to a final substrate that is comprised of a material selected for thermally matching the readout chip assembly to another material to be hybridized therewith; and thereafter removing the temporary carrier substrate.

It will be appreciated that this invention also allows processing (e.g. depositing and patterning thin films) on both sides of the active silicon film. This improves layout density, makes possible new and novel transistor structures and provides superior RF shielding.

In accordance with this invention, it is possible to process the active circuits in thin silicon (0.2-4 microns thick) films, as well as performing low temperature (below 450 ) processing steps (e.g. deposit and pattern metal, low temperature insulating film, etc.) on the backside of the thin silicon film. This technique provides the advantage of higher device density because of an extra layer of interconnection available on the back surface, fabricating novel devices such as a dual gate MOS transistor, and superior RF shielding by providing shielding layers on both sides of the active circuitry.

As brought out above, the silicon film thickness for active devices may be very thin (»0.2 micron). These very thin

films provide superior radiation hardness and facilitate operation of the MOS transistors in a fully depleted mode to provide higher performance.

It will also be understood that this invention also has the advantage of being applicable to any detector material, and is not limited for use with Group III-V material, such as HgCdTe.

BRIEF DESCRIPTION OF THE DRAWING

The above set forth and other features of the invention are made more apparent in the ensuing Detailed Description of the Invention when read in conjunction with the attached Drawing, wherein:

Figs, la through Id are cross-sectional views (not t scale) that illustrate processing steps of a first metho of the invention, specifically a thin film transfer method, wherein,

Fig. la is a cross section of a wafer illustrating the initial stage of fabrication of a chip assembly i accordance with the invention;

Fig. lb is a cross section illustrating an example of a feedthrough;

Fig. lc is a cross sectional view with the circuits fabricated and the wafer attached to the chosen substrate in accordance with the invention;

Fig. Id is a simplified cross section of the assembly in accordance with the invention; and

Figs. 2a through 2e are cross-sectional views, not to scale, that illustrate a second method of the invention, specifically a double transfer method.

DETAILED DESCRIPTION OF THE INVENTION

The method for making an assembly in accordance with the first or second methods of the invention begins with a bonded silicon wafer as illustrated in cross-section at 10 in Fig. la. The wafer 10 comprises a thin, preferably 0.2- 10 micrometers thick, film 12 made of single crystal silicon of bulk silicon quality on top of a layer of thermal SiO_, as shown at 14. It will be understood that the thickness of the SiO- layer is not critical and would typically be in the range 0.1 - 1.5 microns. The films 12 and 14 are disposed on top of a normal bulk silicon wafer illustrated at 16.

The wafer 10 may be purchased commercially, or may be fabricated by providing two silicon wafers, depositing the silicon dioxide layer on a surface of one, and then fusion bonding (~1200 degrees C) the two wafers together with the layer of silicon dioxide interposed between the two wafers. One of the wafers is then thinned to a desired thickness in the range of a fraction of a micrometer to 50 micrometers. Thinning can be accomplished by a mechanical grinding process that is optionally followed by a plasma etching process.

Conventional readout circuits (not seen in Fig. lb) are processed in the thin film 12 using conventional methods disclosed, for example, by Hayashi, et al. previously cited. Conventional readout circuits can include transimpedance amplifiers, signal multiplexers, and the like of a type conventionally used for interfacing to an array of IR radiation detectors. Processing continues through the step of depositing an overglass layer (shown in Fig. lc at 18), and includes the addition of electrical feedthroughs illustrated in Fig. lb at 20.

It will be understood that the electrical feedthroughs illustrated at 20 can be incorporated at any convenient

part of the process, though preferably at an early stage in the process. In the preferred approach as illustrated in Fig. lb, the feedthroughs 20 are made by etching trenches through the thin silicon layer 12 to the oxide layer 14 below.

It will be appreciated by those skilled in the art that because of the arrangement of the layers that the etching step is readily accomplished because the oxide acts as an etch stop. The trench walls indicated at 22 are then oxidized using a conventional thermal oxidation process. The trench hole is then filled with a conductive material. Doped polycrystalline silicon (polysilicon) is used as the conductive material, but other materials, such as, for example, tungsten, may also be used if desired. An alternative feedthrough arrangement may be fabricated by using the doped single crystal silicon layer itself and isolating a portion with a trench.

Fig. lc shows illustrative examples of devices fabricated in the thin film 12. As seen in Fig. lc, the structure formed thus far has been processed to form N-type and P- type regions, as required for the particular circuit application, within the silicon film 12. These regions may be delineated through a photolithographic process and are formed through a diffusion or an implantation step. Subsequent to doping the silicon film 12 both p+ and n+ regions are also photolithographically defined and diffused or implanted. One or more polysilicon gate electrodes 17 may be also deposited, as required. A further layer of SiO- shown at 14' may be formed to bury the gate electrodes 17. An electrically insulating overglass layer 18 may also be deposited in a conventional manner.

The bonded wafer 10 with the circuits fabricated (Fig. lc) is next attached as seen in Fig. Id to a substrate 24 which is chosen to have a coefficient of thermal expansion that is selected for providing the resultant readout chip

assembly with an effective coefficient of thermal expansion that is approximately the same as the coefficient of thermal expansion of the intended detector chip. For example, in the case of HgCdTe detectors, suitable substrate materials have been found to include GaAs, CdTe, Ge, and a-plane sapphire. Preferably, the effective coefficient of thermal expansion of the readout integrated circuit assembly is within approximately 20% of the coefficient of thermal expansion of the detector material so as to avoid deleterious effects due to thermal cycling.

The attachment at 26 of the ^' substrate 24 to the thin film silicon side of the bonded silicon wafer can be made with an epoxy adhesive, glass frit (either conducting or non- conducting) , a low temperature diffusion bond, or an alloy (eutectic) bond.

The thick silicon substrate 16 portion of the bonded wafer is next removed. This is accomplished using an etching process (or a lapping process followed by etching) . The etch is chosen so it will stop at the oxide layer 14 which separates the silicon substrate 16 from the thin film silicon 12 containing the circuitry. It will be understood that many etching methods are possible, for example, a hot KOH solution, plasma etch, or the like. The edge of the thin film 12 is preferably protected from the etch by providing an oxide 28 around the thin film wafer edge 30, the protective oxide being suitably formed during the process of fabricating the circuits.

As best seen in the simplified cross section shown in Fig. Id, the wafers are next processed through the conventional steps for forming Al bonding pads 34a and Indium bumps 34b for interconnection to the detector, shown generally as 36. The Al bonding pads 34a and the In bumps 34b contact the feedthroughs 20 which contact appropriate portions of the circuit within the thin film layer 12. The In bumps 34b are mated with and cold welded to corresponding In bumps 36a of

the detector 36 in a conventional and well known bump bonding procedure.

During use, IR radiation is incident upon the detector 36 and is converted therein into detectable charge carriers. The charge carriers are collected under the influence of a bias voltage and are provided, via the In bump interconnects, to the circuits fabricated within the thin film layer 12 for amplification and readout.

Reference is now made to Figs. 2a-2e which illustrate a double transfer method of the invention. Processing begins with a bonded silicon wafer 40. The wafer 40 includes a silicon substrate 42, a layer of silicon dioxide 44, and a thinned silicon layer 46. In Fig. 2a the thinned silicon layer 46 has been processed to form the required readout circuitry and contact pads 46'.

In Fig. 2b the bonded silicon wafer 40 is attached to a temporary carrier substrate 50 with a layer of adhesive or wax 48.

In Fig. 2c the silicon substrate 42 is removed by a suitable process, such as by etching with KOH. During the etching process the temporary carrier substrate 50 provides mechanical support for the thinned silicon layer 46. The silicon dioxide layer 44 functions as an etch stop to terminate the etching process after the silicon substrate 40 has been removed.

In Fig. 2d the structure fabricated thus far, including the temporary carrier substrate 50, is bonded to a final carrier substrate 54 with a layer 52 of, by example, epoxy adhesive that is applied between the silicon dioxide layer 44 and the carrier substrate 54.

In Fig. 2e the bonding layer 48 is removed, which also removes the temporary carrier substrate 50. By example, if

a wax is used for the layer 48 then a heating process is employed to melt the wax, thereby releasing the temporary substrate 50. This leaves the thinned silicon layer 46, having the readout circuitry, bonded to the substrate 54 which is comprised of a material that is selected so as to cause the effective coefficient of thermal expansion of the readout chip assembly to match (within approximately 20%) the coefficient of thermal expansion of the material of the radiation detector. As was described previously, for a radiation detector comprised of HgCdTe suitable substrate 54 materials include GaAs, CdTe, Ge, and a-plane sapphire. Processing continues as described above to form indium bump interconnects 34b for eventual hybridization of the readout integrated circuit assembly with a detector array (not shown) .

By example, for a HgCdTe detector assembly that is operated within the range of approximately 65K to approximately 85K, the readout chip assembly combination comprised of the Si layer 12 or 46, the epoxy adhesive layer 26 or 52, and the substrate 24 or 54, has an effective coefficient of thermal expansion that is selected to approximately match the coefficient of thermal expansion of the detector material. As a result, the readout chip and the detector will each shrink at approximately the same rate during cooling, and ui.due bowing and stress upon the assemblies and interconnects (indium bumps) is avoided at the desired operating temperature.

In general, epoxy adhesives have a coefficient of thermal expansion in the range of 30-50 X 10 ^*6 m/mK, HgCdTe has a coefficient of thermal expansion in the range of 3.8-4.5 X 10 ^*6 m/mK, Si has a coefficient of thermal expansion of approximately 1.2 X 10 ^* * m/mK, GaAs has a coefficient of thermal expansion in the range of 4.5-5.9 X 10 ^*6 m/mK, Ge has a coefficient of thermal expansion in the range of 5.5- 6.4 X 10 ^*6 m/mK, and a-plane sapphire has a coefficient of thermal expansion in the range of 3.5-7.5 X 10 ^'6 m/mK. If

an epoxy adhesive is employed, the adhesive layer 26 preferably has a thickness that is approximately equal to the thickness of the Si layer 12, and the epoxy adhesive is selected to be one having low outgasεing at approximately 77K under vacuum conditions.

In an exemplary embodiment the detector assembly 36 is comprised of HgCdTe, and the readout chip assembly is a multilayered structure comprised of a 10 micrometer thick layer of Si, a 10 micrometer thick layer of epoxy adhesive, and a 525 micrometer thick layer of GaAs. The effective coefficient of thermal expansion and contraction of the readout chip assembly is within 20% of the coefficient of thermal expansion and contraction of the HgCdTe material of the detector assembly, which is the desired result.

It will be appreciated that the assembly that results from the execution of either the first or second methods features silicon-based readout circuitry bonded to a non- silicon substrate, wherein the non-silicon substrate is comprised of a material that is selected, in combination with the Si circuit layer and the bonding material, to approximately match the thermal expansion characteristics of the detector material. The assembly is suitable for mating with a radiation detector comprised of a Group II-VI material, such as HgCdTe. The material of the substrate is selected from the group consisting of a Group III-V material, such as GaAs; a Group II-VI material, such as CdTe; a Group IV material, such as Ge; and a-plane sapphire.

While the invention has been particularly shown and described with respect to preferred embodiments thereof,, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the scope and spirit of the invention.