THIN-FILM TRANSISTOR AND PREPARATION METHOD THEREFOR, AND MEMORY AND DISPLAY

WIPO Patent Application WO/2023/236373

A1

Disclosed herein are a thin-film transistor and a preparation method therefor, and a memory and a display. The thin-film transistor comprises a first source/drain layer (1); a second source/drain layer (3); an insulating layer (2), which is located between the first source/drain layer (1) and the second source/drain layer (3); a channel layer (4), which is embedded in the first source/drain layer (1) and the insulating layer (2); and a gate electrode (5), which is embedded in the channel layer (4), wherein an embedded end of the channel layer (4) is in contact with the second source/drain layer (3), and a top end of the channel layer (4) and a top end of the gate electrode (5) are both flush with the first source/drain layer (1). The thin-film transistor provided in the present disclosure is a CAA architecture in which an annular channel is arranged surrounding the gate electrode (5), such that the performance of the transistor can be improved, and the power consumption can be reduced; moreover, there is no gate electrode (5) in the horizontal direction covering the first source/drain layer (1), such that the parasitic capacitance and current leakage of the gate electrode can be reduced.

DUAN XINLV (CN)
LI LING (CN)
LIU MING (CN)
GENG DI (CN)
LU CONGYAN (CN)

PCT/CN2022/116070

December 14, 2023

August 31, 2022

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INST OF MICROELECTRONICS OF THE CHINESE ACADEMY OF SCIENCES (CN)

H01L29/06; H01L21/34; H01L21/44; H01L27/105; H01L29/08; H01L29/10; H01L29/423; H01L29/786

CN1790735A	2006-06-21
JP2003152182A	2003-05-23
CN113764514A	2021-12-07
CN103855004A	2014-06-11

BEIJING BRIGHT & RIGHT LAW FIRM (CN)

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