TECHNICAL FIELD

The present disclosure relates to buffer circuits and more precisely to a three- state buffer circuit having a reset, a track, and a hold state.

BACKGROUND

People and devices around the globe are becoming more and more connected. These connections are based on certain communication protocols and are nowadays generally digital. As the need for communication increases, the bitrate of the digital communication increases. Many communication paths comprise one or more analog portions, generally in the form of a wireless interface. Wireless interfaces are available in substantially any frequency band from a few kHz (the Grimeton radio station) to several THz (Beyond 5G telecommunication).

Analog interfaces require the transformation of a digital signal into a corresponding analog signal upon transmission across the analog interface. At the receiving end, the reception of the analog signal generally requires transformation back to a digital representation for further processing or transmission. As the bitrate increase, the devices communicating across the analog interface are posed with stringent requirements. Devices configured to directly convert the analog signal directly to a digital representation without introducing any down-conversion mixer are researched also for the higher frequency bands. Such devices are required to provide a certain instantaneous bandwidth (IBW), or real-time bandwidth, increasing the required sampling rate of analog to digital converters (ADCs) of the devices. The required sampling rate has to be provided with high accuracy and the linearity of the ADC is preferably not compromised with the increased sampling rate.

One component affecting the linearity of ADCs is the track-and-hold (T/H) circuit. An ADC may comprise a plurality of T/H circuits triggered at different clock phases in a time-interleaving manner. Generally, a T/H is designed to be power efficient, small, linear and have limited memory effects (residual charge on parasitic or intentional capacitors) between two consecutive samples. These requirements are generally contradicting and conventional bootstrap switches at the input may be introduced to increase linearity, however bootstrap switches require significant area and consumes considerable amounts of power.

From the above it is understood that there is room for improvements.

SUMMARY

It is in view of the above considerations and others that the various embodiments of this disclosure have been made. The present disclosure therefor recognizes the fact that there is a need for alternatives to (e.g. improvement of) the existing art described above.

It is an object of some embodiments to solve, mitigate, alleviate, or eliminate at least some of the above or other disadvantages.

An object of the present disclosure is to provide a new type of buffer circuit which is improved over prior art and which eliminates or at least mitigates the drawbacks discussed above. More specifically, an object of the invention is to provide a three-state buffer circuit that is usable in a track-and-hold circuit. These objects are achieved by the technique set forth in the appended independent claims with preferred embodiments defined in the dependent claims related thereto.

In a first aspect, a three-state buffer circuit comprising a voltage follower for directly driving a sampling capacitor at an output terminal of the three-state buffer circuit is presented. The three-state buffer circuit further comprises a switched capacitor circuit connected at an input of the voltage follower and configured to control the voltage follower to operate in one of a tracking state, a hold state and a reset state. At the tracking state, the voltage follower is configured to provide an output voltage at the output terminal at a level corresponding to an input voltage at an input terminal of the three-state buffer circuit. At the hold state, the voltage follower is configured not to provide any output voltage at the output terminal. And at the reset state, the voltage follower is configured to provide an output voltage at the output terminal at a reset voltage.

In some variants, the voltage follower is a source follower arrangement comprising a first source follower and a second source follower operating as a complementary source follower. The switched capacitor circuit further comprises a first DC shift device arranged between the first source follower and the input terminal of the three-state buffer circuit, and a second DC shift device arranged between the second source follower and the input terminal of the three-state buffer circuit. The output terminal of the three-state buffer circuit is provided at the source terminals of the first source follower and the second source follower.

In some variants, the switched capacitor circuit comprises a first switch arrangement configured to be controlled by a reset control signal and thereby operable to bias the input of the voltage follower to an active state.

In some variants, the first switch arrangement comprises a first high side reset switch controlled by the reset control signal and thereby operable to connect a gate of the first source follower to a first voltage, and a first low side reset switch controlled by the reset control signal and thereby operable to connect a gate of the second source follower to a second voltage.

In some variants, the three-state buffer circuit further comprises a second switch arrangement configured to be controlled by the reset control signal. The second switch arrangement comprises a second high side reset switch operable to connect a first offset voltage between the first DC-shift device and the input terminal of the three-state buffer circuit and a second low side reset switch operable to connect a second offset voltage between the second DC-shift device and the input terminal of the three-state buffer circuit.

In some variants, the first offset voltage and the second offset voltage are equal.

In some variants, the three-state buffer circuit is configured to operate in the reset state responsive to a state of the reset control signal.

In some variants, wherein the switched capacitor circuit comprises a first switch arrangement configured to be controlled by a hold control signal and thereby operable to connect the input of the voltage follower to a hold voltage configured to disable the voltage follower.

In some variants, the first switch arrangement comprises a high side hold switch controlled by the hold control signal and thereby operable to connect the gate of the first source follower to the second voltage, and a low side hold switch controlled by the hold control signal and operable to connect the gate of the second source follower to the first voltage.

In some variants, the three-state buffer circuit is configured to operate in the hold state responsive to a state of the hold control signal.

In some variants, the switched capacitor circuit further comprises a tracking switch arrangement controlled by a tracking control signal and operable to control a connection between the input terminal of the three-state buffer circuit and the input of the voltage follower.

In some variants, the tracking switch arrangement comprises a high side tracking switch controlled by the tracking control signal and operable to connect the first DC shift device to the input terminal of the three-state buffer circuit, and a low side tracking switch controlled by the tracking control signal and operable to connect the second DC shift device to the input terminal of the three-state buffer circuit.

In some variants, the three-state buffer circuit is configured to operate in the tracking state responsive to a state of a tracking control signal.

In some variants, the first source follower is an NMOS source follower and the second source follower is a PMOS source follower.

In some variants, at least one of the first DC shift device and the second DC shift device is a capacitor.

In a second aspect, a controller operatively connected to the three-state buffer circuit of first aspect is presented. The controller is configured to control a reset control signal, a hold control signal and a tracking control signal between respective active and non-active states for predefined or configurable periods of time. The controller is configured to only control one of the control signals into an active state at a time.

In some variants, the controller is further configured to control each of the control signals into an active state with a duty cycle of 1/3.

In a third aspect, a resettable track and hold circuit is presented. The resettable track and hold circuit comprises the three-state buffer circuit of the first aspect and a sampling capacitor connected in parallel between the output terminal of the three-state buffer circuit and an output terminal of the resettable track and hold circuit. This provides the output voltage of the three-state buffer circuit across the sampling capacitor.

In some variants, the resettable track and hold circuit further comprises the controller the second aspect.

In a fourth aspect, an analog to digital converter (ADC) comprising the resettable track and hold circuit of the third aspect is presented.

In some variants, the analog to digital converter is a successive-approximation ADC, (SAR ADC).

In some variants, the sampling capacitors of the resettable track and hold circuits are binary-weighted capacitors.

In some variants, the sampling capacitors of the resettable track and hold circuits are unary-weighted capacitors.

In a fifth aspect, an integrated circuit comprising the ADC of the fourth aspect is presented.

In a sixth aspect, an apparatus comprising the ADC of the fourth aspect is presented.

In some variants, the apparatus is a network node.

In some variants, the apparatus is a wireless device.

An advantage of some variants is that a settling and charging time of a load, e.g. the sampling capacitor is reduced. This is an effect of series resistance present in e.g. prior art sampling switches.

An advantage of some variants is that they are compatible solution with complementary source-followers, i.e. an NMOS and PMOS source follower working in parallel.

An advantage of some variants is that the biasing of a complementary source follower is simplified. Only a pair of switches connected to the supply rails provide sufficient biasing.

An advantage of some variants is that all states, also the reset functionality, are provided with corresponding settling times of the voltage follower without introducing extra parasitic capacitance in the charging path of sampling capacitor. An advantage of some variants is that control logic allows for customization of the duration of each state. This enables matching of transfer functions between several three-state buffer circuits.

An advantage of some variants is that they provide comparable or better linearity and noise compared to a prior art buffer utilizing a bootstrapped switch solution. This is provided with a simplified design and an area effective implementation.

An advantage of some variants is that a bias T network is implemented without large resistors or capacitors thereby significantly reducing memory effects of the circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other aspects, features and advantages will be apparent and elucidated from the following description of various embodiments; references being made to the appended diagrammatical drawings which illustrate non-limiting examples of how the concept can be reduced into practice.

Figs, la-b are schematic views of three-state buffer circuits according to some embodiments;

Fig. 2 is a schematic view of a three-state buffer circuit according to some embodiments;

Fig. 3a is a schematic view of a three-state buffer circuit according to some embodiments;

Fig. 3b is a signal graph associated with the three-state buffer circuit of Fig. 3a;

Fig. 4a is a schematic view of a three-state buffer circuit according to some embodiments;

Fig. 4b is a signal graph associated with the three-state buffer circuit of Fig. 4a;

Fig. 5a is a schematic view of a three-state buffer circuit according to some embodiments;

Fig. 5b is a signal graph associated with the three-state buffer circuit of Fig. 5a;

Fig. 6 is a signal graph according to some embodiments;

Fig. 7a-b are schematic views of track and hold circuits according to some embodiments; Figs. 8a-b are schematic views of controllers according to some embodiments;

Figs. 9a-c are schematic views of analog to digital converters according to some embodiments;

Fig. 10 is a schematic view of an integrated circuit according to some embodiments; and

Figs. 1 la-c are schematic views of apparatuses according to some embodiments.

DETAILED DESCRIPTION

Hereinafter, certain embodiments will be described more fully with reference to the accompanying drawings. The invention described throughout this disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided by way of example so that this disclosure will be thorough and complete, and will fully convey the scope of the invention, such as it is defined in the appended claims, to those skilled in the art.

The term "coupled" is defined as connected, although not necessarily directly, and not necessarily mechanically. Two or more items that are "coupled" may be integral with each other. The terms "a" and "an" are defined as one or more unless this disclosure explicitly requires otherwise. The terms "substantially," "approximately," and "about" are defined as largely, but not necessarily wholly what is specified, as understood by a person of ordinary skill in the art. The terms "comprise" (and any form of comprise, such as "comprises" and "comprising"), "have" (and any form of have, such as "has" and "having"), "include" (and any form of include, such as "includes" and "including") and "contain" (and any form of contain, such as "contains" and "containing") are open-ended linking verbs. As a result, a method that "comprises," "has," "includes" or "contains" one or more steps possesses those one or more steps, but is not limited to possessing only those one or more steps.

In Fig. la, a schematic view of a three-state buffer circuit 100 according to embodiments of the present disclosure is shown. The three-state buffer circuit 100 is provided with an input terminal 101 configured to receive an input voltage Vin from sources external to the three-state buffer circuit 100. The input voltage Vin will commonly be described as comprising an analogue radio frequency (RF) signal but may be any signal usable with the three-state buffer circuit 100. In some embodiments, the input voltage Vin further comprises a DC component. The three-state buffer circuit 100 comprises at least one switched capacitor circuit 120 and at least one voltage follower 110. The switched capacitor circuit 120 is connected between the input terminal 101 of the three-state buffer circuit 100 and an input 111 of the voltage follower 110. The three-state buffer circuit 100 is further provided with an output terminal 102. The voltage follower 110 is configured to provide an output voltage v _ou t at the output terminal. The output v _ou t voltage is determined by the switched capacitor circuit 120. The switched capacitor circuit 120 is operable in at least three states T, H, R (see Figs. 3a, 4a and 5a). The three-state buffer circuit 100 is configured for driving a sampling capacitor 210 when connected at the output terminal 102 of the three-state buffer circuit 100. In other words, the voltage follower 110 of the three-state buffer circuit 100 may be directly connected to the sampling capacitor 210. In the following, a brief introduction to the three states T, H, R will be given, but further details and embodiments will be presented in other parts of the disclosure.

At a first state, a tracking state T, the voltage follower 110 is preferably configured to provide an output voltage v _ou t at the output terminal 102 at a level corresponding to an input voltage Vin at the input terminal 101 of the three-state buffer circuit 100. As the naming implies, at the tracking state T, the output voltage v _ou t of the three-state buffer circuit 100 will track the input voltage Vin of the three-state buffer circuit 100.

At a second state, a hold state H, the voltage follower 110 is preferably configured not to provide any output voltage v _ou t at the output terminal 102. If a sampling capacitor 210 is provided at the output terminal 102 of the three-state buffer circuit, the sampling capacitor 210 will maintain (hold) the latest output voltage v _ou t provided at the output terminal 102. At the hold state H, the output terminal 102 of the three-state buffer is preferably at a high impedance state. At a third state, a reset state R, the voltage follower 110 is preferably configured to provide an output voltage v _ou t at the output terminal 102 at a reset voltage Vres-

With reference to Fig. lb, the conceptual workings of the three-state buffer circuit 100 according to embodiments of the present disclosure will be explained. In Fig. lb, the voltage follower 110 may be configured as an operational amplifier (OP- amp) arranged as a buffer circuit. That is to say, the output of the OP-amp is fed back to a negative input and the input voltage Vin is operatively connected to a positive input of the OP-amp. In the conceptual three-state buffer circuit 100 of Fig. lb, the switched capacitor circuit 120 comprises two switch arrangements 121, 127.

A first switch arrangement 121 is arranged configured to be controlled by a reset control signal S121 and/or a hold control signal S125. The first switch arrangement 121 is operable to bias the input 111 of the voltage follower between a first voltage Vi and a second voltage V2 depending on the configuration of the reset control signal S121 and the hold control signal S125. A tracking switch arrangement 127 may be arranged between the input 111 of the voltage follower 110 and the input terminal 101 of the three-state buffer circuit 100 and controlled by a tracking control signal S127. The tracking switch arrangement 127 is operable to control a connection between the input terminal 101 of the three-state buffer circuit 100 and the input 111 of the voltage follower 110.

In embodiments wherein the voltage follower 110 is configured as an OP-amp, the skilled person will appreciate that the first switch arrangement 127 will be arranged to control a bias voltage of the OP-amp rather than the input port. Based on the full disclosure herein, the skilled person will understand how to arrange the first switch arrangement 127 to arrive at the technical effects and benefits presented herein.

In some embodiments, as will be explained in other parts of the disclosure, it may be beneficial to arrange a DC shift arrangement 129 between the input 111 of the voltage follower 110 and the input terminal 101 of the three-state buffer circuit 100. The first switch arrangement 121 is preferably arranged to control a voltage between the DC shift arrangement 129 and the input 111 of the voltage follower 110. A second switch arrangement 123 may be arranged to control a voltage between the DC shift arrangement 129 and the tracking switch arrangement 127. The second switch arrangement 123 may be configured to be controlled by the reset control signal S121.

Note that all switch arrangements are provided between the voltage follower

110 and the input terminal 101, i.e. no switch arrangements are needed between the voltage follower 110 and the output terminal 102. This allows the three-state buffer circuit 100 to operate in all three states without any bootstrap switches feeding the output terminal 102 of the three-state buffer circuit 100. The three-state buffer circuit 100 may directly drive a load such as the sampling capacitor, thereby greatly reducing the complexity, power and area of a track and hold circuit 200 (see Fig. 7a).

In Fig. 2, a three-state buffer circuit 100 according to some embodiments of the present disclosure is shown. In this embodiment, the voltage follower 110 is configured as a source follower arrangement 110. The source follower arrangement 110 may comprise a first source follower 112 and a second source follower 114 arranged to operate as a complementary source follower. In Fig. 2, the first source follower 112 is exemplified as an NMOS device and the second source follower 114 is exemplified as a PMOS device. However, other topologies and architectures may very well be utilized and the voltage follower 110 is not limited to this particular configuration. The input

111 of the source follower 110 is provided at the gate 11 la of the first source follower

112 and at the gate 11 lb of the second source follower 114. In other words, the input 111 of the source follower 110 may be described as provided with a high side input

11 la at the gate of the first source follower 112 and a low side input 11 lb at the gate of the second source follower 114. The output terminal 102 of the three-state buffer circuit 100 is provided at the source terminals of the first source follower 112 and the second source follower 114. This arrangement of the source follower 110 allows the source follower 110 to directly provide high currents (compared to bootstrap configurations) in either direction to a load, the sampling capacitor 210, connected at the output terminal 102 of the three-state buffer circuit 100, i.e. at the source terminals of the first source follower 112 and the second source follower 114.

In order to explain the switched capacitor circuit 120, a brief functional introduction of the operations of the voltage follower 110 in Fig. 2 will be offered. As previously mentioned, at the tracking state T, the voltage follower 110 is configured to provide an output voltage v _ou t at the output terminal 102 at a level corresponding to the input voltage Vin. This may be accomplished by simply connecting the input voltage Vin to the gates I l la, 111b of the source followers 112, 114.

When switching to the hold state H, the output voltage v _ou t should preferably freeze (hold, maintain) the output voltage v _ou t at a level corresponding to the input voltage Vin that was provided when the three-state buffer circuit was switched to the hold state H. This may be provided by turning off the voltage follower 110. In some embodiments, thus may be accomplished by disconnecting (turning off, placing in high impedance) the input voltage Vin from the gates I l la, 111b of the source followers 112, 114 and proving a deactivating voltage at the gates I l la, 111b of the source followers 112, 114. This implies connecting a positive supply rail Vi to the gate 11 lb of the second source follower 114 and a negative supply rail V2 to the gate 11 la of the first source follower 112. Throughout the present disclosure, the positive supply rail Vi may be referred to as a first voltage Vi. Correspondingly, the negative supply rail V2 may be referred to as a second voltage V2.

The reset state R is intended to control a voltage at the output terminal 102 of the three-state buffer circuit 100 to the reset voltage V _re s. The reset voltage V _re s may be provided by disconnecting (turning off, placing in high impedance) the input voltage Vin from the gates I l la, 111b of the source followers 112, 114 and providing an activating voltage at the gates I l la, 111b of the source followers 112, 114. This implies connecting a positive supply rail Vi to the gate 11 la of the first source follower 112 and a negative supply rail V2 to the gate 11 lb of the second source follower 114.

The switched capacitor circuit 120 shown in Fig. 2 comprises a first high side reset switch 121a and a first low side reset switch 121b. The first high side reset switch 121a is connected between the gate 11 la of the first source follower 112 and the positive supply rail Vi. The first low side reset switch 121b is connected between the gate 11 lb of the second source follower 114 and the negative supply rail V2. The first high side reset switch 121a and the first low side reset switch 121b are both controlled by the reset control signal S121. In other words, when the reset control signal S121 is set (active), the gate 11 la of the first source follower 112 is connected to the positive supply rail Vi and the gate 11 lb of the second source follower 114 is connected to the negative supply rail V2. The first high side reset switch 121a and the first low side reset switch 121b may be described as comprised in the first switch arrangement 121 presented with reference to Fig. lb.

As shown in Fig. lb, the switched capacitor circuit 120 may comprise the tracking switch arrangement 127. The tracking switch arrangement 127 may comprise a high side tracking switch 127a and a low side tracking switch 127b. The high side tracking switch 127a is arranged between the input terminal 101 of the three-state buffer circuit 100 and the gate 11 la of the first source follower 112. The low side tracking switch 127b is arranged between the input terminal 101 of the three-state buffer circuit 100 and the gate 11 lb of the second source follower 114. The high side tracking switch 127a and the low side tracking switch 127b are both controlled by the tracking control signal S127. In other words, when the tracking control signal S127 is set (active), the gate 11 la of the first source follower 112 is (operatively) connected to the input terminal 101 of the three-state buffer circuit 100 and the gate 11 lb of the second source follower 114 is also (operatively) connected to the input terminal 101 of the three-state buffer circuit 100.

In order to isolate the gates I l la, 111b of the source followers 112, 114, a first DC-shift device 129a (high side DC-shift device) may be arranged between the gate 11 la of the first source follower 112 and the high side tracking switch 127a. Correspondingly, a second DC-shift device 129b (low side DC-shift device) may be arranged between the gate 11 lb of the second source follower 114 and the low side tracking switch 127b. The first DC-shift device 129a and the second DC-shift device 129b may be comprised in the DC shift arrangement 129 introduced in reference to Fig. lb. The DC-shift devices 129a, 129b enable a DC level of each of the gates I l la, 111b of the source followers 112, 114 to be controlled independently. In some embodiments, the first DC-shift device 129a and/or the second DC-shift device 129b are provided as capacitors.

The second switch arrangement 123 (not shown in Fig. 2) may, in some embodiments, comprise a second high side reset switch 123a and a second low side reset switch 123b. The second high side reset switch 123a is connected, at one end, between the first DC-shift device 129a and the high side tracking switch 127a, and, at the other end, to a first offset voltage V _os ,i. The second low side reset switch 123b is connected, at one end, between the second DC-shift device 129b and the low side tracking switch 127b, and, at the other end, to a second offset voltage V _os ,2. The second switch arrangement 123, as will be explained elsewhere in the present disclosure, allows for control of an offset voltage provided across each of the first DC-shift device 129a and the second DC-shift device 129b.

The switched capacitor circuit 120 may further comprise a high side hold switch 125a and low side hold switch 125b. The high side hold switch 125a is connected between the gate 11 la of the first source follower 112 and the negative supply rail V2. The low side hold switch 125b is connected between the gate 11 lb of the second source follower 114 and the positive supply rail V2. The high side hold switch 125a and the low side hold switch 125b are both controlled by the hold control signal S125. In other words, when the hold control signal S125 is set (active), the gate 11 la of the first source follower 112 is connected to the negative supply rail V2 and the gate 11 lb of the second source follower 114 is connected to the positive supply rail Vi. The high side hold switch 125a and the low side hold switch 125b may be described as comprised in the first switch arrangement 121 presented with reference to Fig. lb.

The switches mentioned with reference to Fig. 2 and in other context of the present discourse are generally transistor-based switches but illustrated as electromechanical switches in the Figs, to simplify explanation.

With reference to Figs. 3a and 3b, the reset state R of the three-state buffer circuit 100 according to some embodiments of the present disclosure will be explained. The explanation will be based in the circuitry of Fig. 2, but as the skilled person will appreciate after digesting the teachings herein, that this is but one example and the circuitry may be configured in various different ways and still provide the corresponding functionality. In Fig. 3a, the corresponding circuit as illustrated in Fig. 2 is shown, but with the control signals S121, S125, S127 configured to control the three-state buffer circuit 100 to operate at the reset state R. This is illustrated in Fig. 3b, wherein, assuming all control signals S121, S125, S127 are active high, the reset control signal S121 is high, the hold control signal S125 is low and the tracking control signal S127 is low. Fig. 3b further illustrates the input voltage Vin (top-most solid line in Fig. 3b) and the output voltage v _ou t (dotted line in Fig. 3b) overlaid. All signals in Fig. 3b are shown at a common horizontal time-axis. This is reflected in Fig. 3a wherein the switches controlled by the reset control signal S121 are closed (conducting) and the remaining switches are open (not conducting).

Specifically in Fig. 3a, the first high side reset switch 121a, the first low side reset switch 121b, the second high side reset switch 123a and the second low side reset switch 123b are all closed. At the reset state R, the input terminal 101 is disconnected from the voltage follower 110 and the positive voltage rail Vi is connected to the gate 11 la of the first source follower 112 and the negative voltage rail V2 is connected to the gate 11 lb of the second source follower 114. This means that the output voltage v _ou t is determined by a gate-source voltages v _gs ,ii2 of the first source followers 112 and the positive voltage rail Vi together with a gate-source voltages v _gs ,ii4 of the second source followers 114 and the negative voltage rail V2 such that v _out = V ₁ — v _{gs /112} = V2 + ^s,ii4- This voltage, V ₄ — v _{gs 112} = V ₂ + v _gSfll4 , is referred to as a reset voltage V _re s. Assuming that the first source follower 112 and the second source follower 114 are matched with regards to their respective gate-source voltages v _gs ,ii2, v _gs ,ii4 the reset voltage Vres may be described as V _res = V ₂ + (1 — V ₂ )/2 = (1 + V ₂ )/2 . The output voltage Vout illustrated in Fig. 3b is at the reset voltage Vres and is actively driven at this level by the voltage follower 110.

In addition to the above, at the reset state R, the DC shift arrangement 129 is charged. Across the first DC shift device 129a, a first DC shift voltage VDC,I is provided. The first DC shift voltage VDC,I is defined with a positive node towards the gate 11 la of the first source follower such that V _{DC 1} = V ₁ — V _{os l} . Correspondingly, across the second DC shift device 129b, a second DC shift voltage VDC,2 is provided. The second DC shift voltage VDC,2 is defined with a positive node towards the gate 111b of the second source follower 114 such that V _{DC 2} = V ₂ — V _O s,2-

With reference to Figs. 4a and 4b, the tracking state T of the three-state buffer circuit 100 according to some embodiments of the present disclosure will be explained. The explanation will be based in the circuitry of Fig. 2, but as the skilled person will appreciate after digesting the teachings herein, that this is but one example and the circuitry may be configured in various different ways and still provide the corresponding functionality. In Fig. 4a, the corresponding circuit as illustrated in Fig. 2 is shown, but with the control signals S121, S125, S127 configured to control the three-state buffer circuit 100 to operate at the tracking state T. This is illustrated in Fig. 4b, wherein, assuming all control signals S121, S125, S127 are active high, the reset control signal S121 is low, the hold control signal S125 is low and the tracking control signal S127 is high. Fig. 4b further illustrates the input voltage Vin (top-most solid line in Fig. 4b) and the output voltage v _ou t (dotted line in Fig. 4b). All signals in Fig. 4b are shown at a common horizontal time-axis. This is reflected in Fig. 4a wherein the switches controlled by the tracking control signal S127 are closed (conducting) and the remaining switches are open (not conducting).

Specifically in Fig. 4b, the high side tracking switch 127a is closed connecting the input port 101 of the three-state buffer circuit 100 to the first DC shift device 129a and the low side tracking switch 127b is closed connecting the input port 101 of the three-state buffer circuit 100 also to the second DC shift device 129b. As all other switches are open, the input voltage Vin is provided at the gates I l la, 11 lb of the source followers 112, 114 via the DC shift devices 129a, 129b. Consequently, the output voltage Vout will track the input voltage Vin as shown in Fig. 4b. As explained with reference to Fig. 3a, the DC shift arrangement 129 was charged during the reset state R which, assuming it was not charged to 0 V, provides a voltage shift across the DC shift devices 129a, 129b. This is generally beneficial as any DC component of the input voltage Vin would have to charge the DC shift arrangement 129 increasing a load of a source and decreasing the settling time of the three-state buffer circuit 100. However, by controlling the offset voltages v _os ,i, v _os ,2, it is possible to ensure that the DC shift voltages VDC,I, VDC,2 correspond to any DC component at the input terminal 101 of the three-state buffer circuit 100.

It should be mentioned that although the input voltage Vin is provided through the high side tracking switch 127a and the low side tracking switch 127b, one further benefit of the present disclosure is that the linearity performance of these switches 127a, 127b is non-critical. Or rather, it is good enough even without bootstrapping. This is related to the impedance they drive, the gates I l la, 111b of the source followers 112, 114, which is comparably high, i.e. a gate capacitance C _gg is small. This reduces a signal current flowing into the switches 127a, 127b and consequently a voltage modulation of on-resistance of the switches 127a, 127b.

Generally, in order to provide tracking of the input voltage Vin without introducing significant loss to the input voltage Vin, a capacitance of the first DC-shift device 129a and the second DC-shift device 129b is preferably larger than the gate capacitance C _gg of the gates I l la, 111b of the source followers 112, 114. By providing such configuration, a source providing the input voltage Vin will be loaded via an equivalent capacitance which may, as the capacitance of the DC-shift devices 129a, 129b is (much) larger than the gate capacitances C _gg of the source followers 112, 114, be approximated by a sum of the gate capacitances C _gg of the source followers 112, 114. In addition to this, in order to increase a settling time at the gates I l la, 11 lb of the source followers 112, 114, the sizes of the source followers 112, 114 (i.e. transistor sizes) may be selected in such a way that bandwidth and/or linearity requirements of the three-state buffer circuit 100 are not limited by a time constant determined by a resistance of the source providing the input voltage Vin, the on-resistance of the switches 127a, 127b and the gate capacitances C _gg of the source followers 112, 114. This design strategy is likely to result in a further reduced size of the source follower. A reduced size will further increase low noise performance and increase an ability to drive large sampling capacitors 210. A plurality of three-state buffer circuits 100 may be connected in parallel resulting in maintained bandwidth and linearity as the time constants of each of the three-state buffer circuits 100 are preserved. This is assuming that the resistance of the source providing the input voltage Vin is also parallelized (or tethered).

With reference to Figs. 5a and ab, the hold state H of the three-state buffer circuit 100 according to some embodiments of the present disclosure will be explained. The explanation will be based in the circuitry of Fig. 2, but as the skilled person will appreciate after digesting the teachings herein, that this is but one example and the circuitry may be configured in various different ways and still provide the corresponding functionality. In Fig. 5a, the corresponding circuit as illustrated in Fig. 2 is shown, but with the control signals S121, S125, S127 configured to control the three-state buffer circuit 100 to operate at the hold state H. This is illustrated in Fig. 5b, wherein, assuming all control signals S121, S125, S127 are active high, the reset control signal S121 is low, the hold control signal S125 is high and the tracking control signal S127 is low. Fig. 5b further illustrates the input voltage Vin (top-most solid line in Fig. 5b) and the output voltage v _ou t (dotted line in Fig. 5b) overlaid. All signals in Fig. 5b are shown at a common horizontal time-axis. This is reflected in Fig. 5a wherein the switches controlled by the hold control signal S125 are closed (conducting) and the remaining switches are open (not conducting).

Specifically in Fig. 5b, the high side hold switch 125a is closed connecting the gate 11 la of the first source follower 112 to the negative voltage rail V2. Also the low side hold switch 125b is closed connecting the gate 11 lb of the second source follower 114 to the positive voltage rail Vi. As a result, both source followers 112, 114 are turned off, effectively leaving the output terminal 102 of the three-state buffer circuit floating (undefined, high impedance) state. This means that substantially no current will flow through either of the source followers 112, 114 and any load, e.g. the sampling capacitor 210, will be maintained at the voltage level provided at the output terminal 102 of the three-state buffer circuit prior to entering the hold state H, this is assuming that no external devices are discharging the load. This is visualized in Fig. 5b wherein the output voltage v _ou t is constant at a level that was provided at the output terminal 102 when the hold state H was entered, assumed to be at the leftmost data point of the graph in Fig. 5b.

In Fig. 6, the corresponding graphs of Figs. 3b, 4b and 5b are shown but in the same graph, illustrating the output voltage v _ou t provided by the three-state buffer 100 at the different operating states T, H, R. In Fig. 6, the three-state buffer 100 is operating at each of the three states T, H, R wherein each operation is roughly indicated at the top of the graph. At the left most portion of the graph in Fig. 6, the three-state buffer 100 is operating at the tracking state T. At this state, the output voltage v _ou t tracks the input voltage Vin (with a slight phase shift for illustrative purposes). As previously presented, the tracking state T is controlled by (assuming active high control) placing the reset control signal S121 at a low state, the hold control signal S125 at a low state and the tracking control signal S127 at a high state. Following the tracking state T in Fig. 6 is the hold state H which is entered by changing the tracking control signal S127 to a low state and the hold control signal S125 to a high state. At the hold state H, the output voltage Vout is kept at the level it was at when the hold control signal S125 was shifted to a high state. Following the hold state H in Fig. 6 is the reset state R which is entered by changing the hold control signal S125 to a low state and the reset control signal S121 to a high state. At the reset state R, the output voltage v _ou t is driven to the reset voltage V _re s which in Fig. 6 is substantially the same as any DC-offset of the input voltage Vi _n .

With reference to Fig. 7a, a resettable track and hold circuit 200 according to some embodiments of the present disclosure will be presented. The resettable track and hold circuit 200 comprises the three-state buffer circuit 100 according to any of the embodiments or examples presented herein. The output terminal 102 of the three-state buffer circuit 100 is operatively connected to an output terminal 202 of the resettable track and hold circuit 200. Correspondingly, the input terminal 101 of the three-state buffer circuit 100 is operatively connected to an input terminal 201 of the resettable track and hold circuit 200. The resettable track and hold circuit 200 further comprises the sampling capacitor 210 connected in parallel between the output terminal 102 of the three-state buffer circuit 100 and the output terminal 202 of the resettable track and hold circuit 200. In other words, the sampling capacitor 210 is arranged such that the output voltage Vout provided at the output terminal 102 of the three-state buffer circuit 100 is across the sampling capacitor 210.

In Fig. 7b, a corresponding resettable track and hold circuit 200 as the one illustrated in Fig. 7a is shown with one difference. The resettable track and hold circuit 200 in Fig. 7b comprises more than one three-state buffer circuit 100 according to any of the embodiments or examples presented herein. In Fig. 7b, the track and hold circuit 200 is illustrated as comprising three three-state buffer circuits 100, but the skilled person will appreciate that any number of three-state buffer circuit 100 may be comprised in the resettable track and hold circuit 200. Having more than one three-state buffer circuit 100 in the resettable track and hold circuit 200 may be beneficial as the drive strength of the resettable track and hold circuit 200 may be increased. I.e. the sampling capacitor 120 may have an increased capacitance. This is made possible by the three-state buffer circuit 100 of the present disclosure as no bandwidth or linearity limitation will be introduced by parallelizing the three-state buffer circuit 100. In Fig. 6, the time at which the three-state buffer circuit 100 operates in each state T, H, R is substantially equal, i.e. each state T, H, R has a duty cycle of 1/3. However, in some embodiments, the states T, H, R may have different duty cycles. With reference to Fig. 8a, one benefit of the three-state buffer circuit 100 is that an associated controller 10 controlling the control signals S121, S125, S127 may be configured to customize the duration of each state T, H, R. This allows for matching of transfer functions between three-state buffer circuits 100 when e.g. more than one three-state buffer circuit 100 is utilized. Preferably, control signals S121, S125, S127 are provided non-overlapping, i.e. only one active at a time, to ensure that no short circuits or unwanted charging/discharging of the sampling capacitor 210 occurs. In some embodiments, a guard interval may be introduced between one or more of the states T, H, R. The guard interval may be defined as a, compared to the active time, short time period at which none of the control signals S121, S125, S127 are active. In embodiments where a guard interval is utilized, the duty cycle of one or more of the states T, H, R is reduced from the exemplified duty cycle of 1/3. Preferably, the duty cycles of each of the states T, H, R are the same. In some embodiments wherein a guard interval is utilized, the duty cycle of each state T, H, R is 1/4. The controller 10 may, as illustrated in Fig. 8a, be comprised in or operatively connected to the three-state buffer circuit 100 according to any of the embodiments or examples presented herein. In Fig. 8b, an alternative configuration of the controller 10 is shown wherein it is comprised in, or operatively connected to, the resettable track and hold circuit 200 according to any of the embodiments or examples presented herein.

In Fig. 9a, an analog to digital converter (ADC) 300 is shown. The ADC 300 comprises the resettable track and hold circuits 200 according to any of the embodiments or examples presented herein. As is known by the skilled person, a general ADC may be provided in a number of different architectures such as Direct- conversion ADCs, Successive approximation ADCs, Ramp-compare ADCs, Wilkinson ADCs, Integrating ADCs, Delta-encoded ADCs, Pipelined ADCs, Sigma-delta ADCs, Time-interleaved ADCs, Intermediate FM stage ADCs, Time-stretch ADCs etc. Depending on the architecture chosen, a connection between the resettable track and hold circuits 200 and an ADC unit block 310. As illustrated in Fig. 9a, the ADC 300 comprises one resettable track and hold circuits 200 connected to a plurality of ADC unit blocks 310. Correspondingly, In Fig. 9b, the ADC 300 is illustrated comprising a plurality of resettable track and hold circuits 200 connected in parallel, each connected to one ADC unit block 310. The intention is to illustrate the versatility of the resettable track and hold circuits 200 comprising the three-state buffer circuit 100 according to any of the embodiments or examples presented herein. In particular, in Fig. 9c, the ADC 300 is not required to comprise the full resettable track and hold circuits 200 but may be configured with three-state buffer circuits 100 in place of the resettable track and hold circuits 200, i.e. the sampling capacitor is not comprised in the resettable track and hold circuits 200. The latter example illustrated in Fig. 9c may be a charge redistribution ADC (C-DAC). Such C-DACs are commonly configured with a plurality of ADC unit blocks 310 each comprising capacitive unit elements. In this embodiment, the capacitive unit elements will function as sampling capacitor 210 as presented herein.

In Fig. 10, an integrated circuit (IC) 400 according to the present disclosure is shown. The IC is illustrated as comprising the ADC 300 according to any of the embodiments or examples presented herein. In some embodiments (not shown), the IC 300 does not comprise the full ADC 300 but rather the resettable track and hold circuits 200 according to any of the embodiments or examples presented herein. In some embodiments (not shown), the IC 300 does not comprise the full resettable track and hold circuits 200 but rather the three-state buffer circuits 100 according to any of the embodiments or examples presented herein.

In Fig. 1 la, an apparatus 500 according to some embodiments of the present disclosure is shown. The apparatus is shown comprising the ADC 300 according to any of the embodiments or examples presented herein. In some embodiments (not shown), the apparatus 500 does not comprise the full ADC 300 but rather the resettable track and hold circuits 200 according to any of the embodiments or examples presented herein. In some embodiments (not shown), apparatus 500 does not comprise the full resettable track and hold circuits 200 but rather the three-state buffer circuits 100 according to any of the embodiments or examples presented herein. In some embodiments, see Fig. 1 lb, the apparatus 500 is a network node 500. In some embodiments, see Fig. 11c, the apparatus 500 is a wireless device 500. Modifications and other variants of the described embodiments will come to mind to one skilled in the art having benefit of the teachings presented in the foregoing description and associated drawings. Therefore, it is to be understood that the embodiments are not limited to the specific example embodiments described in this disclosure and that modifications and other variants are intended to be included within the scope of this disclosure. For example, while embodiments of the invention have been described with reference to analog to digital conversion, persons skilled in the art will appreciate that the embodiments of the invention can equivalently be applied to any other application wherein high linearity, low footprint and high bandwidth sampling circuitry are required. Furthermore, although specific terms may be employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation. Therefore, a person skilled in the art would recognize numerous variations to the described embodiments that would still fall within the scope of the appended claims. Furthermore, although individual features may be included in different claims (or embodiments), these may possibly advantageously be combined, and the inclusion of different claims (or embodiments) does not imply that a combination of features is not feasible and/or advantageous. In addition, singular references do not exclude a plurality. Finally, reference signs in the claims are provided merely as a clarifying example and should not be construed as limiting the scope of the claims in any way.