Title:
THROUGH SILICON VIA CRACK DETECTION CIRCUIT, DETECTION METHOD, AND MEMORY
Document Type and Number:
WIPO Patent Application WO/2023/040072
Kind Code:
A1
Abstract:
Disclosed in embodiments of the present disclosure are a through silicon via crack detection circuit, a detection method, and a memory. The through silicon via crack detection circuit comprises: crack detection lines, which are arranged surrounding a through silicon via; the through silicon via passes through M interconnected metal layers, there are M-1 crack detection lines, and the M-1 crack detection lines are respectively arranged on each layer among the M metal layers excluding a top metal layer, where M is a positive integer greater than one; a first contact, which is located at a first position at the top metal layer and connected to at least one crack detection line among the M-1 crack detection lines by means of the M interconnected metal layers; and a second contact, which is located at a second position at the top metal layer and connected to the M-1 crack detection lines; wherein whether a crack is present around the through silicon via is determined according to a resistance between the first contact and the second contact.
Inventors:
WU XIAOFEI (CN)
Application Number:
PCT/CN2021/135747
Publication Date:
March 23, 2023
Filing Date:
December 06, 2021
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
H01L21/66; H01L23/544
Foreign References:
| US20130161827A1 | 2013-06-27 | |||
| US20150115993A1 | 2015-04-30 | |||
| US20140191410A1 | 2014-07-10 | |||
| US20130221353A1 | 2013-08-29 | |||
| CN102867812A | 2013-01-09 |
Attorney, Agent or Firm:
CHINA PAT INTELLECTUAL PROPERTY OFFICE (CN)
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