MANUFACTURING METHOD

TECHNICAL FIELD

The present disclosure generally pertains to a time-of-flight portion and a time-of-flight portion manufacturing method.

TECHNICAL BACKGROUND

Generally, time-of-flight (ToF) image sensors are known. For example, in the field of indirect time- of-flight (iToF), a depth may be measured indirectly by measuring a phase-shift of modulated light which is reflected at a scene (e.g. an object) and which is then incident on the image sensor.

The modulated light is typically in the infrared range, such that an interference with visible light is minimized.

On a material-level, iToF sensors are typically based on silicon technology and may be read out with CAPDs (current-assisted photonic demodulators), which modulate taps storing photoelectric charges in response to the incident light.

Although there exist techniques for performing iToF, it is generally desirable to provide a time-of- flight portion and a time-of-flight portion manufacturing method.

SUMMARY

According to a first aspect, the disclosure provides time-of-flight portion, comprising: a substrate; a ridge for generating electric carriers in response to light being incident on the ridge, wherein the ridge is based on a III-V semiconductor material, wherein the ridge extends from a surface of the substrate, and wherein the ridge has a predetermined height and a predetermined width; a tap which is in contact with the ridge; and a gate electrode which is in contact with the ridge, wherein the tap and the gate electrode are provided for reading out the generated electric carriers.

According to a second aspect, the disclosure provides a time-of-flight portion manufacturing method, comprising: epitaxially growing a III-V semiconductor material on a substrate for providing a ridge; providing a tap to be in contact with the ridge; and providing a gate electrode to be in con tact with the ridge.

Further aspects are set forth in the dependent claims, the following description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments are explained by way of example with respect to the accompanying drawings, in which:

Fig. 1 depicts a schemativ view of a ridge which is confined by two STIs;

Fig. 2 depicts an embodiment a ToF portion according to the present disclosure as a lateral mixer; Fig. 3 is a sectional view of the lateral mixer of Fig. 2;

Fig. 4 depicts a lateral mixer array;

Fig. 5 depicts the lateral mixer array of Fig. 4 in different perspectives;

Fig. 6 depicts the lateral mixer array of Figs. 4 and 5 in different perspectives at different stages of manufacturing;

Fig. 7 depicts a further embodiment of a lateral mixer array according to the present disclosure;

Fig. 8 depicts a cross-sectional view of a lateral mixer sensor including the lateral mixer array of Fig.

7;

Fig. 9 depicts a further embodiment of a ToF portion according to the present disclosure as a longi tudinal mixer;

Fig. 10 depicts a cross-sectional view of the longitudinal mixer of Fig. 9;

Fig. 11 depicts a longitudinal mixer array including two longitudinal mixers according to the present disclosure;

Fig. 12 depicts different perspectives of the longitudinal mixer array of Fig. 11;

Fig. 13 depicts the longitudinal mixer array of Figs. 11 and 12 at different stages of manufacturing;

Fig. 14 depicts a further cross-sectional view of the longitudinal mixer array of Figs 11 to 13 show ing three pixel elements;

Fig. 15 depicts a cross-sectional view of a longitudinal mixer sensor including the longitudinal mixer array of Figs. 11 to 14;

Fig. 16 illustrates ToF image sensor circuitry according to the present disclosure in a block diagram;

Fig. 17 shows readout circuitry according to the present disclosure for reading out charges in taps of a ToF portion according to the present disclosure;

Fig. 18 depicts a general ToF portion manufacturing method according to the present disclosure in a block diagram; Fig. 19 depicts, in a block diagram a further embodiment of a ToF manufacturing method according to the present disclosure for manufacturing a lateral mixer;

Fig. 20 depicts, in a block diagram, a further embodiment of a ToF portion manufacturing method according to the present disclosure including multiple (at least two) taps and gate electrodes which are provided in an alternating order on the predetermined axis;

Fig. 21 depicts a further embodiment of a ToF portion manufacturing method according to the pre sent disclosure in a block diagram in which taps are provided in between gate electrodes in a longitu dinal direction of the ridge

Fig. 22 depicts a further embodiment of a ToF portion manufacturing method according to the pre sent disclosure in a block diagram in which gate electrodes are provided in between taps on an axis which is orthogonal to the longitudinal direction of the ridge;

Fig. 23 depicts a further embodiment of a method for manufacturing a ToF portion according to the present disclosure in a block diagram in which further STIs are provided; and

Fig. 24 illustrates an embodiment of a ToF imaging apparatus according to the present disclosure.

DETAILED DESCRIPTION OF EMBODIMENTS

Before a detailed description of the embodiments starting with Fig. 1 is given, general explanations are made.

As mentioned in the outset, known time-of-flight (ToF) sensors are based on silicon technology.

However, it has been recognized that silicon-based semiconductors may only be suitable for optical sensing when light with a wavelength up to roughly a thousand nanometers is used since the mate rial may become transparent for higher wavelengths.

As also mentioned in the outset, ToF measurements are typically carried out in the infrared wave length range, such that it is desirable to provide ToF for higher wavelengths since a measurement accuracy may increase due to less ambient light (or radiation) in such wavelength ranges.

It has been recognized that III-V materials, such as InGaAs, may have light absorption properties which make them suitable to be used for imaging (or optical sensing) with a wavelength of up to roughly one-thousand seven-hundred nanometers (or more).

However, monolithic III-V technology may be expensive to manufacture and to combine with logic circuitry. Hence, it has been recognized that it is desirable to provide cost-efficient ToF sensing cir cuitry based on III-V materials. Therefore, some embodiments pertain to a time-of-flight portion, including: a substrate; a ridge for generating electric carriers in response to light being incident on the ridge, wherein the ridge is based on a III-V semiconductor material, wherein the ridge extends from a surface of the substrate, and wherein the ridge has a predetermined height and a predetermined width; a tap which is in contact with the ridge; and a gate electrode which is in contact with the ridge, wherein the tap and the gate electrode are provided for reading out the generated electric carriers.

The substrate may include any single-layered or multi-layered substrate, as it is generally known, such as an oxide-based substrate (e.g. silicon oxide) or a non-oxide-based substrate (e.g. (roughly) pure silicon), or the like.

Extending from a surface of the substrate (e.g. an upper/ top or a lower/bottom surface), a ridge may be provided. The ridge may generally be of any shape and to a ridge it may also be referred to as an elevation, a crest, a strip, or the like.

In some embodiments, the ridge may have a (roughly) rectangular top surface. In some embodi ments, the ridge may have a lengthy shape, i.e. one side of the rectangular top surface is at least a predetermined amount of times (wherein the amount is not limited to a natural or whole number) the longer than the other side.

In some embodiments, the ridge may have a chock or wedge-shaped bottom surface without limit ing the present disclosure in that regard (e.g. the bottom surface may have the same shape as the top surface or any other bottom surface-shape than a chock or a wedge may be envisaged).

Hence, in some embodiments, the ridge may include or may correspond to a wedge.

In some embodiments, the ridge may have a wedge-shaped bottom surface which extends from the surface of the substrate, wherein the wedge-shaped bottom surface transitions/ junctions (e.g. gradu ally or abrupt) to a cuboid, hence the ridge may be dividable into a wedge and a cuboid. However, in such embodiment, the ridge may be integral and not really be assembled of a wedge and a cuboid (however, this is also possible according to some embodiments).

The ridge may be adapted to generate electric carriers in response to light being incident on the ridge. That is, the ridge may be based on a conductive material in which electric carriers (e.g. elec trons, positrons, electron-hole-pairs or any other negatively or positively charged carriers) or the like are generated when a photon of at least a predetermined frequency is incident and/ or absorbed by the conductive material (e.g. based on photoelectric effect).

In particular, the ridge is based, in some embodiments, on a III-V semiconductor material. A III-V semiconductor material according to the present disclosure includes (but is not limited to) elements of the third and fifth main group of the periodic table. The present disclosure is not limited to any element or any number of different elements which are used in a III-V semiconductor material. For example, the semiconductor material may include or be based on Indium (In), Gallium (Ga), and Ar senic (As). For example, a III-V semiconductor may be based on the compound InGaAs (indium gallium arsenide).

However, as mentioned above, the present disclosure is not limited to any specific III-V semicon ductor material. Hence, other materials which may be used may be based on any phosphide, arse nide, antimonide, or the like, such as GaN (gallium nitride), AIN (aluminum nitride), InN (indium nitride), BN (boron nitride), GaP (gallium phosphide), A1P (aluminum phosphide), InP (indium phosphide), InGaP (indium gallium phosphide), BP (boron phosphide), GaAs (gallium arsenide), AlAs (aluminum arsenide), InAs (indium arsenide), Bas (boron arsenide), GaSb (gallium anti monide), AlSb (aluminum antimonide), InSb (indium antimonide), or the like.

As discussed above, the ridge may extend from a surface of the substrate.

Furthermore, the ridge may have a predetermined height and a predetermined width.

For example, the ridge may be grown, such as for example with epitaxial growth on the substrate, for example along a predetermined line on the substrate, such that at first, the epitaxial growth may lead to a wedge-shaped structure since the growth surface may increase with every grown layer.

The width of the epitaxial growth may be limited, e.g. with shallow trench isolations (STI) at a pre determined distance to the predetermined line and provided in parallel to the predetermined line (without limiting the present disclosure in that regard: for example the shape of the STIs may deter mine the shape of the top surface of the ridge such that any shape may be achieved by providing dif ferent heights within each STI and by providing non-straight side-walls of each STI, for example).

Hence, the width may be determined by the distance between the STIs. After the growing ridge has reached the STIs, it may only further grow vertically, such that the height may be adjustable by inter rupting/ aborting the epitaxial growth.

As generally known in time-of-flight, taps may be used for sampling/ demodulating a time-of-flight signal, such as modulated light returning from a scene, or the like. Hence, a tap may be region de signed for applying a respective sampling/ demodulating voltage and it might be designed for captur ing carriers (e.g. electrons or holes) which are generated in the ridge in response to incident photons.

A tap (i.e. at least one tap) according to the present disclosure may be in contact with the ridge ei ther in that conductive material (which may also be adapted to store charges) serving as a tap is pro vided on top and/ or on at least one side of the ridge or in that a predetermined doping is provided in the ridge at a predetermined position (such as on top or at the sides). Hence, in contact may also refer to as being included in the ridge, but the ridge may be divided into different regions (e.g. tap- and non-tap regions).

Furthermore, a gate electrode (i.e. at least one gate electrode) may be in contact with the ridge, e.g. may be provided on top and/ or on at least one side wall of the ridge, e.g. as a further conductor (or as a predetermined doping).

As generally known in ToF, such as gated ToF or iToF, the tap(s) and the gate electrode(s) are pro vided for reading out the generated electric carriers, i.e. in that a demodulation signal (i.e. at least one demodulation signal) is applied, or the like. In other words: an application of a voltage to a gate elec trode may result in electric charges being pulled towards the tap from which the charges can be read out.

According to the present disclosure, a ToF portion may provide a basis for a photodetector chip which is sensitive to a large waveband (from visible to SWIR (super wide infrared)). Such a photode tector may be combined with a logic readout chip (e.g. a ROIC (readout integrated circuit)) using 3D stacking technologies to produce a NIR (near-infrared) / SWIR stacked sensor.

For example, in a case of an SWIR sensitive pixel, the readout circuitry could be implemented in an ROIC chip only, without limiting the present disclosure in that regard.

As discussed herein, in some embodiments, the III-V semiconductor material includes InGaAs.

In some embodiments, the tap and the gate electrode are provided on a predetermined axis with re spect to the ridge.

For example, if the ridge is (roughly) straight, e.g. by having a rectangular lengthy surface parallel to the substrate, as discussed herein, it may be defined according to an axis along which it extends (e.g. the predetermined (imaginary) line, as discussed above). Then, for example, the axis of the gate elec trode and the tap (i.e. an imaginary line between the tap and the gate electrode) may have a predeter mined alignment with respect to the axis of extension of the ridge, such as for example, parallel, orthogonal or any angle between zero and three-hundred and sixty degrees, such that a signal flow direction between the gate electrode and the tap may be defined with respect to the ridge.

Hence, different architectures may emerge at different axes.

For example, the predetermined axis may be parallel to a longitudinal direction of the ridge.

In such embodiments, a plurality of ToF (sub-)portions (e.g. single demodulation elements) may be provided on one ridge, as will be discussed further below. In some embodiments, the predetermined axis is orthogonal (perpendicular) to a longitudinal direc tion of the ridge.

In such embodiments, a plurality of ToF sub-portions may be provided on multiple (parallel) ridges.

Hence, in some embodiments, the time-of-flight portion further includes a further ridge (i.e. at least one further ridge) parallel to the first ridge, wherein the gate electrode is connected with the further ridge (to the ridge and the further ridge may also be referred to as first and second ridge, in some embodiments).

The second ridge may have a similar shape or (roughly) the same shape as the first ridge, such that it may extend from the substrate with a predefined distance to and, e.g. in parallel to the first ridge.

The gate electrode may be connected with both the first ridge and the second ridge, such that the gate electrode is shared between the first and the second ridge. Furthermore, the first ridge as well as the second ridge may both have doping regions corresponding to two taps each. As generally known in ToF, two taps (e.g. tap A and tap B) may be present.

For example, tap A may be provided at a side in proximity to the gate and tap B may be provided on another side of the ridge.

In some embodiments, the time-of-flight portion further includes: a further gate electrode which is in contact with the ridge; and a further tap which is in contact with the ridge, wherein the taps and the gate electrodes are provided in an alternating order on the predetermined axis.

To the tap and the further tap as well as the gate electrode and the further gate electrode, it may also be referred to as first and second tap/gate electrode.

The taps and the gate electrodes (i.e. the first and second taps and first and second gate electrodes) may be provided in an alternating order on the predetermined axis, such as after a gate electrode, a tap may be provided (or vice versa) or that the taps lie between the gate electrodes or vice versa. In the case that there are more than two gate electrodes and/ or taps, any ordering may be envisaged such that a ToF signal can be demodulated.

For example, in the case that the predetermined axis is parallel to the longitudinal direction of the ridge, the two gate electrodes may be provided between the two taps.

In such embodiments, multiple ToF (sub-)portions may be provided on one ridge, as indicated above. For example, an ordering may be as follows (in the direction of the predetermined axis): tap A, gate one, gate two, tap B, gate one, gate two, tap A. In this embodiment, tap B may be shared by two sub-portions (since only two gates and two taps are needed for one readout process).

In the case that the predetermined axis is orthogonal to the longitudinal direction of the ridge, the two taps may be provided between the two gate electrodes. In such embodiments, at least a second ridge may be envisaged, wherein a first gate electrode may be connected to the two ridges. Further more, both ridges may have two taps (tap A and tap B). On the opposite sides of the connection of the first gate electrodes, respective second gate electrodes may be connected to the ridges.

Hence, in such embodiments, the first gate electrode may be shared between the two ridges.

In some embodiments, the time-of-flight portion further includes: a shallow trench isolation confin ing the ridge at a predetermined height, such that the ridge has the predetermined width, as dis cussed herein.

However, the predetermined height for confining the ridge is not limited to be the same as the pre determined height of the ridge. As indicated above, after confining the ridge, the ridge may still grow higher than the height of the STIs. Hence, it may be referred to a ridge height for the height of the ridge and to a confinement height for defining the height at which the ridge is confined.

Some embodiments pertain to a time-of-flight portion manufacturing method, including: epitaxially growing a III-V semiconductor material on a substrate for providing a ridge; providing a tap to be in contact with the ridge; and providing a gate electrode to be in contact with the ridge.

With a time-of-flight portion manufacturing method, a time-of-flight portion according to the pre sent disclosure may be produced.

The present disclosure is not limited to the case that the manufacturing method is carried out by hand, hence it should not be stuck to the original meaning of manufacturing, since also any auto mated or machine-based process may be envisaged according to the present disclosure.

The ridge may be provided by epitaxially growing a III-V semiconductor material on a substrate (such as silicon, as discussed herein). Generally, any method of epitaxial growth may be envisaged.

The tap may be provided by doping the ridge or by contacting a conductive material with the ridge, as discussed herein.

The gate electrode may be brought into contact with the ridge with any known contacting method, such as laminating, depositing, or the like.

In some embodiments the III-V semiconductor includes InGaAs, as discussed herein. In some em bodiments, the time-of-flight portion manufacturing method further includes: providing the tap and the gate electrode on a predetermined axis with respect to the ridge, as discussed herein. In some embodiments, the predetermined axis is parallel to a longitudinal direction of the ridge, as discussed herein. In some embodiments, the predetermined axis is orthogonal to a longitudinal direction of the ridge, as discussed herein. In some embodiments, the time-of-flight portion manufacturing method further includes: epitaxially growing a further ridge parallel to the first ridge; and providing the gate electrode to be in contact with the further ridge, as discussed herein. In some embodiments, the time-of-flight portion manufacturing method further includes: providing a further gate electrode to be in contact with the ridge; providing a further tap to be in contact with the ridge; and providing the taps and the gate electrodes in an alternating order on the predetermined axis, as discussed herein. In some embodiments, wherein the predetermined axis is parallel to a longitudinal direction of the ridge, the method further includes: providing the two gate electrodes between the two taps, as discussed herein. In some embodiments, wherein the predetermined axis is parallel to a longitudinal direction of the ridge, the method further includes: providing the two taps between the two gate electrodes, as discussed herein. In some embodiments, the time-of-flight portion manufacturing method further includes: providing a shallow trench isolation having a predetermined height on the substrate for confining the epitaxial growth of the ridge to a predetermined width, as discussed herein.

Returning to Fig. 1 , there is depicted a schematic view of a ridge 1 which is confined by two STIs 2, such that the ridge 1 has a width 3 which corresponds to the distance of the STIs 2, as described herein. Furthermore, a length 4 of the ridge 1 is depicted. For illustrational purposes only, a coordi nate system 5 is displayed.

As discussed herein, the ridge 1 is based on a III-V material and is grown based on epitaxial growth using an aspect ratio trapping technique. Aspect ratio trapping is generally known as a technique to grow material when there is a significant lattice mismatch between a substrate (e.g. silicon) and the grown material. Due to a narrow trench used to grow the material, defects caused by the lattice mis match may remain in the narrow trench and may not propagate to a bulk of the grown structure.

Furthermore, the ridge 1 is grown on a silicon substrate (not shown) and the STIs 2 are based on an metal oxide, such that a majority of defects (if there are any defects) of the ridge 1 (which may occur due to the growth) are located at the bottom (i.e. close to the silicon substrate).

As discussed herein, taps and gate electrodes may be provided to at least one ridge according to a predetermined axis with respect to a longitudinal direction of the ridge.

To ToF portions of which the predetermined axis is orthogonal to the longitudinal direction of the ridge, it may also be referred to as lateral III-V ridge photonic mixer (pixel). To ToF portions of which the predetermined axis is parallel to the longitudinal direction of the ridge, it may also be referred to as longitudinal III-V ridge photonic mixer pixel.

Starting with Fig. 2, an embodiment of a lateral III-V ridge photonic mixer pixel 10 (short: lateral mixer) is described (which is an embodiment of a ToF portion according to the present disclosure).

The lateral mixer 10 includes a first gate 11 and a second gate 12 which both are in contact with side walls of a ridge 15. Furthermore, the ridge has two doping regions 13 and 14 each along a longitudi nal axis of the ridge, each doping region serving as a tap (i.e. electric carriers are saved therein and are read out therefrom). In particular, the doping region 13 is called Tap A and the doping region 14 is called Tap B.

Hence, applying a voltage to one or both of the gates 11 and 12, electric carriers are pulled towards Tap A or Tap B, which is shown in Fig. 3.

Fig. 3 is a sectional view of the lateral mixer 10 including the ridge 15, the gates 11 and 12, and the doping regions 13 and 14.

Furthermore, an electric carrier 16 (which can be generated in the ridge 15 in response to light being incident on the ridge 15) is shown. The electric carrier 16 is an electron, thus has a negative charge (in other embodiments it could be a “hole” having a positive charge).

In this embodiment, a positive voltage is applied to the second gate 12 and a negative voltage is ap plied to the first gate 11. Hence, the electric carrier 16 is pulled towards Tap B (i.e. the doping region 14). However, when applying a negative voltage to the first gate 11 and a positive voltage to the sec ond gate 12, negative charges are pulled towards Tap A.

Hence, a time-of-flight demodulation scheme may be applied with alternating voltages in the two gates, as it is generally known.

The lateral mixer 10 may be a standalone ToF portion or may be provided in an array as shown in Fig. 4.

Fig. 4 depicts (a part of) an array 20 including multiple ToF portions (or lateral mixers) according to the present disclosure.

Each ridge of the array 20 is connected to another ridge with a respective gate electrode, such that two the two ridges can be driven simultaneously.

A more detailed view of the array 20 is shown in Fig. 5. Fig. 5 includes a top view 21 of the array 20 including a plurality of ridges 22 and gates 23 (first and second gates) being arranged in an alternating order, i.e. a ridge follows a gate, and so on. For illus- trational purposes, doping regions serving as taps are not displayed, but are provided in the ridges, as discussed above.

Furthermore, a plurality of connectors 24 and 25 are shown. Tap connectors 24 are provided on the ridges 22 and gate connectors 24 are provided on the gates 23.

The connectors 24 and 25 are further in contact with metal connectors 26 which are provided on top of the array 20 and which electrically connect the taps with each other and the gates with each other.

Fig. 5 further depicts a side view 27 of the array 20, showing the ridges 22 between STIs on a silicon substrate and gates between the ridges, as discussed above. Fig. 5 depicts further that the gate con nectors 25 are brought into contact with one of the metal connectors 26, thereby contacting respec tive first or second gates with each other.

In a further side view 28, it is shown how the tap connectors 24 are brought into contact with one of the metal connectors 26, thereby contacting respective Taps A or B with each other. Two ridges 22 share one tap connector 24, in this embodiment.

Fig. 6 depicts, on the top, a top view of the lateral mixer array 20 during manufacturing after which ridges 31 are grown. For simplicity, only the ridges are shown. For illustrational purposes, pixel boundaries 32 are shown which emerge based on the growth structure (the pixel boundaries 32 are indicated with dashed lines).

On the bottom of Fig. 6, a further top view of lateral mixer array 20 is shown at a later point of manufacturing at which taps and tap connectors are provided. The ridges are provided in an alter nating order with the gates, such that each ridge is surrounded by two gates (and each gate is sur rounded by two ridges).

Flowever, not each ridge is provided with a tap connector. Flence, no signal can be read out at such ridges, to which it is referred to as dummy ridges 33, which define a pixel boundary. Additionally to the dummy ridges 33, which provide isolation of the pixels in horizontal direction, the isolation of the pixels in vertical direction is secured by a removal of ridges.

For reading out, pixels are connected to read-out circuitry (not shown) based on 3D stacking.

Fig. 7 depicts a further embodiment of a lateral mixer array 40, in which dummy ridges 41 are pro vided, which define pixel boundaries 42 (depicted as a dashed line). The general principle of func tionality of the lateral mixer array 40 corresponds to the functionality of the previous embodiment, such that a repetitive description thereof is omitted. However, in this embodiment, ridges do not share tap connectors, but each tap, which should be connected to the metal conductor is connected separately with an own tap connector.

Fig. 8 depicts a cross-sectional view of a lateral mixer sensor 50 including the lateral mixer array 40.

In the lateral mixer sensor 50, the lateral mixer array is connected to a silicon CMOS circuitry by means of 3D IC stacking, wherein all transistors required for a pixel readout are produced within a logic circuit (as an ROIC (readout integrated circuit)).

For this reason, the lateral mixer sensor 50 further includes a plurality of micro-lenses 51 on top of each pixel unit of the lateral mixer array 40.

Furthermore, connectors 52 are provided on the metal connectors on the pixel units, such that in total a photodetector chip 53 is provided.

Based on 3D stacking technology, the photo detector chip 53 is stacked on a read-out integrated cir cuit 54 (ROIC), which is generally known, such that a description thereof is omitted. Symbolically, a stacking interface of the two chips is shown under the reference numeral 55

Starting with Fig. 9, an embodiment of a longitudinal III-V ridge photonic mixer pixel 60 (short: longitudinal mixer) is described (which is an embodiment of a ToF portion according to the present disclosure).

In this embodiment, gates 61 (first gate) and 62 (second gate) and taps 63 (tap A) and 64 (tap B) are provided on a predetermined axis which is parallel to a longitudinal direction of a ridge 65.

The ridge 65 is confined with two STIs, as discussed herein. On top of the ridge, the gates 61, 62 and the taps 63, 64 are provided in an alternating order, i.e. Tap A 63, first gate 61, second gate 62, Tap B 64, first gate 61.

Fig. 10 depicts a cross-sectional view of the longitudinal mixer 60 including the gates 61 and 61 as well as the taps 63 and 64. Furthermore, a charge 66 is depicted which is pulled towards the tap 64 (Tap B) since a positive voltage is applied to the second gate 62 and a negative voltage is applied to the first gate 61. Depending on the voltages of the gates, charges which are generated in the ridge are pulled towards the respective tap. Accordingly, if a positive voltage is applied to the first gate 61 and a negative voltage is applied to the second gate 62, charges are pulled towards the tap 63 (Tap A).

Fig. 11 depicts a longitudinal mixer array 70 according to the present disclosure, wherein two longi tudinal mixers 60 as discussed under reference of Fig. 9 are shown. The longitudinal mixers 60 are connected via the gates, i.e. the respective gates are connected with each other, such that one gate can drive taps of two ridges. Hence, the gate connectors are provided orthogonal to a longitudinal axes of the ridges, wherein the gates and the taps are provided in parallel to the longitudinal axes of the ridges, as discussed herein.

Figs. 12 a to c depict a layout of the longitudinal mixer array 70 in different perspectives.

A top view of the longitudinal mixer array 70 is shown in Fig. 12a. Apart from the first and second gates 61 and 62 as well as the taps 63 (Tap A) and 64 (Tab B), a plurality of gate contacts 71 and tap contacts 72 are shown for connecting the mixer array 70 to a readout circuit.

A plurality of first and second gates 61 are provided on a plurality of ridges, wherein the gates are provided orthogonal to a plurality of ridges, such that a mesh-like structure emerges. Furthermore, the first and second gates are provided in pairs, wherein between the pairs of first and second gates, taps 63 and 64 are provided, which can be connected to each other. Hence, with respect to a longi tudinal direction of the ridges, the ordering is as follows: Tap A 63, first gate 61, second gate 62,

Tap B 64, first gate 61, second gate 62 (which is then repeated).

On the gates 61 and 62 and the taps 63 and 64, gate contacts 72 and tap contacts 71 are provided, such that the gates 61 can be interconnected as well as the gates 62, the taps 63 and the taps 64, wherein the interconnections are indicated with straight lines around the respective taps.

Furthermore, charge flow directions between the taps (depicted with capital As and Bs) are symbol ized with corresponding arrow.

A ToF portion 73 according to the present disclosure is further marked with a rectangle in Fig. 12a.

Fig. 12b shows a cross-sectional view of the longitudinal mixer array 70. It is depicted a ridge 65 as in Figs. 9 and 10, which is based on a III-V material and which is embedded in an STI 74 on a sili con substrate 75.

The ridge 65 is surrounded by the gate 61 including a respective gate dielectric 76. On top of the gate 61, a gate contact 71 is provided.

Fig. 12c shows a further cross-sectional view of the longitudinal mixer array 70 further depicting the tap contacts 72, wherein the remaining elements correspond to the elements as described under ref erence of Figs. 12a and b.

Fig. 13 depicts, on the top, a top view of the longitudinal mixer array 70 during manufacturing after which ridges 65 are grown. For simplicity, only the ridges are shown. For illustrational purposes, pixel boundaries 77 are shown which emerge based on the growth structure (the pixel boundaries 32 are indicated with dashed lines). On the bottom of Fig. 13, a further top view of longitudinal mixer array 70 is shown at a later point of manufacturing at which taps 63 and 64 (indicated with dashed ellipses) and tap connectors 72 are provided. Furthermore, first and second gates 61 and 62 are shown. The general structure of the longitudinal mixer array shown here corresponds to the one described under reference of Fig. 12a.

Fig. 14 depicts a further cross-sectional view of the longitudinal mixer array 70, wherein three pixel elements 80 are shown. Each pixel element 80 includes four ridges 65, wherein taps of each ridge is connected to metal connectors 81, which are used for stacking, as will be discussed under reference of Fig. 15. Furthermore, gate electrodes 61 are provided on the ridges, thereby partly surrounding the ridges, as discussed herein.

For illustrational purposes, pixel boundaries 82 are displayed. In this embodiment, no dummy ridges are provided, however, dummy ridges may be present as well (or may not be present in the previous embodiment) and whether dummy ridges are needed may lie in the discretion of the person skilled in the art.

Fig. 15 depicts a cross-sectional view of a longitudinal mixer sensor 90 including the longitudinal mixer array 70. The lateral mixer sensor 90 further includes a plurality of micro-lenses 91 on top of each pixel unit of the lateral mixer array 70.

In the longitudinal mixer sensor 90, the lateral mixer array is connected to a silicon CMOS circuitry by means of 3D IC stacking, wherein all transistors required for a pixel readout are produced within a logic circuit (as an ROIC (readout integrated circuit)).

For this reason, connectors 92 are provided each of the pixels, such that in total a photodetector chip 93 is provided.

Based on 3D stacking technology, the photo detector chip 93 is stacked on a read-out integrated cir cuit 94 (ROIC), which is generally known, such that a description thereof is omitted. Symbolically, a stacking interface of the two chips is shown under the reference numeral 95.

Generally, the stacking principle is similar to the one described under reference of Fig. 8, such that a repetitive description thereof is omitted.

In Fig. 16, there is depicted, on a high level, ToF image sensor circuitry 100 according to the present disclosure.

The ToF image sensor circuitry 100 includes a pixel array 101 including a plurality of pixels 102, wherein the pixels 102 are established by ToF portions according to the present disclosure. In par ticular, in this embodiment, a pixel 102 includes a longitudinal mixer, as discussed herein. Furthermore, the pixels are driven by a row selector unit 103 and a column selector unit 104, as gen erally known, which are in turn controlled by a controller 105, which further controls a processing unit 106.

The pixel array 102 is further driven by a modulation signal driver 107, which is configured to apply a modulation signal to respective pixels, thereby driving the gates and thereby pulling electric carriers towards the taps, as discussed herein.

Based on the readout of the taps, which is carried out by the processing unit 106, an output is gener ated based on which a depth or a confidence (which is generally known) can be determined.

Under reference of Fig. 17, readout circuitry 110 for reading out charges in taps is shown. The readout circuitry 110 is implemented as a photonic demodulator on a silicon CMOS wafer. The sym bols as well as the abbreviations used therein are generally known to the skilled person, such that an unnecessary description thereof is omitted. Flowever, it should be pointed out that the readout cir cuitry 110 includes a die to die interface 111 for flexibly reading out the charges in the respective taps, wherein the interface 111 is based on a photonic demodulator circuit.

Fig. 18 depicts a general ToF portion manufacturing method 120 according to the present disclosure in a block diagram.

At 121 a ridge is grown, which is based on a III-V semiconductor material, as discussed herein. The growth of the ridge is based on epitaxial growth and, in this embodiment, on aspect ratio trapping, as discussed herein.

At 122, a tap is provided on the ridge in that a doping region is included in the ridge, as discussed herein.

At 123, a gate electrode is provided on the ridge, as discussed herein.

The tap and the gate electrode are provided on a predetermined axis with respect to the ridge, as dis cussed herein.

Fig. 19 depicts, in a block diagram, a further embodiment of a ToF portion manufacturing method 130, wherein in this embodiment, the predetermined axis is orthogonal to the longitudinal direction of the ridge, i.e. a lateral mixer is described in this embodiment.

At 131, a ridge and a further ridge (first and second ridge) are epitaxially grown.

At 132, a tap is provided on the first ridge (wherein at a later point or at the same point, further taps may be provided on the first and the second ridge, as discussed herein). At 133, a gate electrode is provided which is in contact with the first and the second ridge, as dis cussed herein.

Fig. 20 depicts, in a block diagram, a further embodiment of a ToF portion manufacturing method 140 according to the present disclosure including multiple (at least two) taps and gate electrodes which are provided in an alternating order on the predetermined axis.

At 141, a ridge is grown epitaxially.

At 142, a tap and a further tap (i.e. a first and a second tap) are provided to be in contact with the ridge on a predetermined axis with respect to the ridge.

At 143, gate electrodes are provided (i.e. at least a first and a second gate electrode) on the predeter mined axis.

Furthermore, the taps and the gate electrodes are provided in an alternating order on the predeter mined axis.

Fig. 21 depicts a further embodiment of a ToF portion manufacturing method 150 according to the present disclosure in a block diagram in which taps are provided in between gate electrodes in a lon gitudinal direction of the ridge (i.e. a longitudinal mixer is provided).

At 151, a ridge is epitaxially grown, as discussed herein.

At 152, two gate electrodes are provided on the ridge, as discussed herein.

At 153, taps are provided between the gate electrodes, such that the taps and the gate electrodes are provided in an alternating order on the predetermined axis.

Fig. 22 depicts a further embodiment of a ToF portion manufacturing method 160 according to the present disclosure in a block diagram in which gate electrodes are provided in between taps on an axis which is orthogonal to the longitudinal direction of the ridge (i.e. a lateral mixer is provided).

At 161, a ridge is epitaxially grown, as discussed herein.

At 152, two taps are provided on the ridge, as discussed herein.

At 153, two gate electrodes are provided between the taps, such that the taps and the gate electrodes are provided in an alternating order on the predetermined axis.

Fig. 23 depicts a further general embodiment of a method 170 for manufacturing a ToF portion ac cording to the present disclosure in a block diagram.

At 171, a ridge is epitaxially grown, as discussed herein, wherein the ridge is confined by an STI, which is provided at 172. At 173, a gate electrode is provided on the ridge, and at 174, a tap is provided on the ridge, as dis cussed herein.

Referring to Fig. 24, there is illustrated an embodiment of a time-of-flight (ToF) imaging apparatus 180, which can be used for depth sensing or providing a distance measurement, in particular for the technology as discussed herein, wherein the ToF imaging apparatus 180 is configured as an iToF camera. The ToF imaging apparatus 180 has image sensor circuitry 187, which is configured to carry out a iToF depth measurement and which forms a control of the ToF imaging apparatus 180 (and it includes, not shown, corresponding processors, memory and storage, as it is generally known to the skilled person).

The ToF imaging apparatus 180 has a modulated light source 181 and it includes light emitting ele ments (based on laser diodes), wherein in the present embodiment, the light emitting elements are narrow band laser elements.

The light source 181 emits light, i.e. modulated light, as discussed herein, to a scene 182 (region of interest or object), which reflects the light. The reflected light is focused by an optical stack 183 to a light detector 184.

The light detector 184 is implemented based on multiple ToF portions according to the present dis closure, wherein in this embodiment, the ToF portions correspond to lateral mixers, as discussed herein, and based on a micro lens array 186 which focuses the light reflected from the scene 182 to an imaging portion 185 (to each pixel of the image sensor circuitry 187).

The light emission time and modulation information is fed to the image sensor circuitry or control 187 including a time-of-flight measurement unit 188, which also receives respective information from the imaging portion 185, when the light is detected which is reflected from the scene 182. On the basis of the modulated light received from the light source 181, the time-of-flight measurement unit 188 computes a phase shift of the received modulated light which has been emitted from the light source 181 and reflected by the scene 182 and on the basis thereon it computes a distance d (depth information) between the imaging portion 185 and the scene 182.

The depth information is fed from the time-of-flight measurement unit 188 to a 3D image recon struction unit 189 of the image sensor circuitry 187, which reconstructs (generates) a 3D image of the scene 182.

It should be recognized that the embodiments describe methods with an exemplary ordering of method steps. The specific ordering of method steps is however given for illustrative purposes only and should not be construed as binding. For example, the ordering of 171 and 172 in the embodi ment of Fig. 23 may be exchanged or may occur at the same time. Also, the ordering of 152 and 153 or 162 and 163 of the embodiments of Figs. 21 and 22 may occur at the same time. Further, also the ordering of 122 and 123 in the embodiment of Fig. 18 may be exchanged or may occur at the same time. Other changes of the ordering of method steps may be apparent to the skilled person.

Please note that the division of the control 187 into units 188 and 189 is only made for illustration purposes and that the present disclosure is not limited to any specific division of functions in spe cific units. For instance, the control 187 could be implemented by a respective programmed proces sor, field programmable gate array (FPGA) and the like.

All units and entities described in this specification and claimed in the appended claims can, if not stated otherwise, be implemented as integrated circuit logic, for example on a chip, and functionality provided by such units and entities can, if not stated otherwise, be implemented by software.

Note that the present technology can also be configured as described below.

(1) A time-of-flight portion, including: a substrate; a ridge for generating electric carriers in response to light being incident on the ridge, wherein the ridge is based on a III-V semiconductor material, wherein the ridge extends from a surface of the substrate, and wherein the ridge has a predetermined height and a predetermined width; a tap which is in contact with the ridge; and a gate electrode which is in contact with the ridge, wherein the tap and the gate electrode are provided for reading out the generated electric carriers.

(2) The time-of-flight portion of (1), wherein the III-V semiconductor material includes In- GaAs.

(3) The time-of-flight portion of (1) or (2), wherein the tap and the gate electrode are provided on a predetermined axis with respect to the ridge.

(4) The time-of-flight portion of (3), wherein the predetermined axis is parallel to a longitudinal direction of the ridge.

(5) The time-of-flight portion of (3), wherein the predetermined axis is orthogonal to a longitu dinal direction of the ridge. (6) The time-of-flight portion of (5), further including a further ridge parallel to the first ridge, wherein the gate electrode is connected with the further ridge.

(7) The time-of-flight portion of anyone of (3) to (6), further including: a further gate electrode which is in contact with the ridge; and a further tap which is in contact with the ridge, wherein the taps and the gate electrodes are provided in an alternating order on the predetermined axis.

(8) The time-of-flight portion of (7), wherein the predetermined axis is parallel to a longitudinal direction of the ridge, and wherein the two gate electrodes are provided between the two taps. (9) The time-of-flight portion of (7), wherein the predetermined axis is orthogonal to a longitu dinal direction of the ridge, and wherein the two taps are provided between the two gate electrodes.

(10) The time-of-flight portion of anyone of (1) to (9), further including: a shallow trench isolation confining the ridge at a predetermined height, such that the ridge has the predetermined width. (11) A time-of-flight portion manufacturing method, including: epitaxially growing a III-V semiconductor material on a substrate for providing a ridge; providing a tap to be in contact with the ridge; and providing a gate electrode to be in contact with the ridge.

(12) The time-of-flight portion manufacturing method of (11), wherein the III-V semiconductor includes InGaAs.

(13) The time-of-flight portion manufacturing method of (11) or (12), further comprising: providing the tap and the gate electrode on a predetermined axis with respect to the ridge.

(14) The time-of-flight portion manufacturing method of (13), wherein the predetermined axis is parallel to a longitudinal direction of the ridge. (15) The time-of-flight portion manufacturing method of (13), wherein the predetermined axis is orthogonal to a longitudinal direction of the ridge.

(16) The time-of-flight portion manufacturing method of (15), further including: epitaxially growing a further ridge parallel to the first ridge; and providing the gate electrode to be in contact with the further ridge. (17) The time-of-flight portion manufacturing method of anyone of (13) to (16), further includ ing: providing a further gate electrode to be in contact with the ridge; providing a further tap to be in contact with the ridge; and providing the taps and the gate electrodes in an alternating order on the predetermined axis.

(18) The time-of- flight portion manufacturing method of (17), wherein the predetermined axis is parallel to a longitudinal direction of the ridge, the method further including: providing the two gate electrodes between the two taps.

(19) The time-of-flight portion manufacturing method of (17), wherein the predetermined axis is parallel to a longitudinal direction of the ridge, the method further including: providing the two taps between the two gate electrodes. (20) The time-of-flight portion manufacturing method of anyone of (11) to (19), further includ ing: providing a shallow trench isolation having a predetermined height on the substrate for con fining the epitaxial growth of the ridge to a predetermined width.