FIELD OF THE INVENTION [0001] This invention relates to analog computational circuits, more specifically to computation circuits, which utilize time as both input and output quantities (operating in time-mode).

BACKGROUND OF THE INVENTION [0002] Conventional VLSI circuits typically perform computational procedures using voltages and currents for both input and output signals. With technology scaling, the degrees of freedom for using voltages and currents for computations are generally more restricted. This can result in computational circuits that exhibit a poor signal-to-noise ratio (SNR), very limited Dynamic Range (DR), and/or high power consumption. [0003] These factors are likely to be significant impediments to the development of more efficient and more effective analog computation circuits in the future, especially in light of the problems posed by technology scaling. Complementary metal-oxide semiconductor (CMOS) process technology, in particular, has lead to scaling that requires significant reductions in the chip "real estate" consumed by analog circuitry. Moreover, as CMOS process technology continues to shrink the usable voltage swing in such circuits, traditional analog circuit designs have been rendered less practicable. Thus there is a need for an alternative to conventional voltage-based and current based computations.

SUMMARY OF THE INVENTION [0004] The present invention provides the circuit building blocks and techniques for computations using analog temporal signal function representations for both inputs and outputs. The invention enables computations using the timing of asynchronous events, for example. The computations performed with the circuits and methods of the invention produce results that can be expressed as time. For example, the result of a computation with the invention can be a time-based parameter corresponding to the timing of a signal output. This obviates the need for translation of temporal signals to an analog or digital form. The invention further overcomes limitations to scaling inherent in voltage-based and current- based computation circuits. [0005] One embodiment of the invention is a time-mode analog computation circuit. The time-mode analog computation circuit can include one or more inputs for receiving one or more temporal input signals. The time-mode analog computation circuit further can include circuitry for performing a mathematical operation based on the one or more temporal input signals. A result of the mathematical operation can be expressed in the timing of an output signal generated by the circuit. [0006] Another embodiment of the present invention is a signal processing method. The method can include providing one or more temporal input signals and performing a mathematical operation based on the one or more temporal input signals. The method, moreover, further includes expressing a result of the mathematical operation in a timing of an output signal. BRIEF DESCRIPTION OF THE DRAWINGS [0007] A fuller understanding of the present invention and the features and benefits thereof will be accomplished upon review of the following detailed description together with the accompanying drawings, in which: [0008] FIG. 1 is a schematic diagram of a time-mode computation circuit that computes the average or weighted average of two temporal signals, according to one embodiment of the invention. [0009] FIG. 2 is a schematic diagram of a time-mode computation circuit that computes the weighted or unweighted sum of two temporal signals, according to another embodiment of the invention. [00010] FIG. 3 is a schematic diagram of a time-mode computation circuit that computes the weighted difference of two temporal signals, according to yet another embodiment of the invention. [00011] FIG. 4 is a schematic diagram of a time-mode computation circuit that computes the thresholded difference between two temporal signals, according to still another embodiment of the invention. [00012] FIG. 5 is a schematic diagram of a time-mode computation circuit that computes the scalar multiplication of a temporal signal, according to another embodiment of the invention. [00013] FIG. 6 is a schematic diagram of a time-mode computation circuit that computes the maximum of two temporal signals, according to yet another embodiment of the invention. [00014] FIG. 7 is a schematic diagram of a time-mode computation circuit that computes the minimum of two temporal signals, according to still another embodiment of the invention. [00015] FIG. 8 shows Cadence-Spectre simulation results for arithmetic mean of two input steps using circuit 100 shown in FIG. 1 occurring at ti = 200 μs and t2=400 μs. [00016] FIG. 9 shows touτ measured data from circuit 100 when one step input was provided to circuit 100 and the current source Ii was varied. [00017] FIG. 10 shows touτ measured data from circuit 100 when ti was varied externally. [00018] FIG. 11 shows touτ measured data from circuit 100 where the first input (ti) entering circuit 100 was fixed as 1 μs, 8.5 μs and 32.5 μs for three different sets of measurements. The transition time (t2) of the second input was varied externally and C=20pF, I =1.552 uA, and Vref=2.5V. [00019] FIG. 12 touτ measured data from circuit 100 where t2 was varied and C=20pF, II =1.46 uA, I2 = 0.29 uA, Vref=2.5V with ti fixed at 1 μs, 8.5 μs and 32.5 μs. DETAILED DESCRIPTION OF THE INVENTION [00020] A time-mode analog computation circuit according to the invention includes at least one input for receiving a temporal input signal and circuitry for performing a mathematical operation on the temporal input signal, a result of the mathematical operation being expressed in a timing of an output signal generated by the computation circuit. The invention thus provides analog computation using the timing of asynchronous events. Although described herein mainly with respect to MOS designs, one of ordinary skill in the art having the benefit of the description will appreciate that the invention can be practiced using bipolar, Bi-MOS, and other transistor-based devices and processes. [00021] With conventional devices and processes that use time-based signal representations, such as pulse-width modulation (PWM) and sigma-delta converters, temporal codes are used only as temporary representations; computation is only performed after their translation to a traditional analog or digital form. Computation according to the invention, by contrast, represents a computed output quantity as a time, or more precisely, a time-based parameter. Translation from a temporal representation to an analog or digital form is not required, therefore, with the invention because computation is not based upon voltage or current levels but rather on the timing of changes in voltage or current levels. The invention thus overcomes the limitations imposed with conventional voltage-based and current-based computation circuits as the scaling process proceeds. Significantly, therefore, time-based computation circuits according to the invention are not substantially impacted by the scaling of technology. [00022] The input to the time-mode computation circuits can be supplied from a variety of sources. For instance, the inputs could be from time-based sensors whose outputs encode measured real -world quantities in the timing of the signals. Another possibility is that the inputs to the time-mode computation circuit are the outputs from other time-mode circuits, since several layers of time-mode blocks can be cascaded. The outputs from the computation circuits according to the invention, moreover, can be stored in a digital memory after an appropriate analog-to-digital conversion of the time-mode signal. [00023] As demonstrated herein, time-mode computation according to the invention can in many instances provide both a high signal-to-noise ratio (SNR) and an expansive dynamic range (DR). Moreover, power consumption in many instances can be reduced as compared to conventional voltage-based and current-based computation circuits. Therefore, VLSI circuits, which require some type of computation circuitry can be improved by representing signals in time, performing time-based computation, and representing computed output quantities as a time and/or a plurality of times (i.e., time-based parameters) according to the invention. [00024] Exemplary circuitry for performing time-mode computations are described operationally herein for step inputs, where a step input corresponds to a time-varying voltage signal, v(t), or time-varying current signal, i(t), represented by the following step waveforms or functions, respectively:

and

W ≥ 'o *(0H O,t < to [00025] Using such an analog temporal step function representation for the inputs,

computation outputs, represented as time-based parameters, are described for the following

computations:

1) Weighed Averaging;

2) Addition;

3) Weighed Subtraction;

4) Scalar Multiplication;

5) Maximum Value Determination;

6) Minimum Value Determination; and

7) Thresholded Difference Determination.

[00026] These time-based computation circuits can be classified based on their

output style:

[00027] FIG. 1 illustrates a time-mode analog computation circuit 100, according to

one embodiment of the invention. The computation circuit 100 illustratively includes two

inputs, a first input 102a and a second input 102b, for receiving two distinct temporal input

signals and circuitry 104 for performing a mathematical operation based on the temporal

input signals. The mathematical operation performed by the circuitry 104, more particularly,

is the computation of an average or weighted average of the two temporal signals. The result of the mathematical operation, as explained below, is expressed in a timing of an output signal generated by the circuitry. [00028] The two distinct temporal input signals are illustratively step inputs, the waveforms or functions of which are shown adjacent the two inputs 102a, 102b where the step inputs are respectively received. The use of signals that can be represented as step functions not only simplifies somewhat the discussion of the operation of the computation circuit 100, but has the added advantage that such signal representation closely approximates "fast-rise" time signals that typically hold particular interest for modern circuit designers. [00029] The circuitry 104, more particularly, illustratively includes a first current source 106a and a second current source 106b. A first transistor 108a is electrically connected to the first current source 106a, and a second transistor 108b is connected to the second current source 106b. Illustratively, each of the transistors 108a, 108b is a p-channel metal oxide semiconductor (PMOS) transistor comprising a source, drain, and gate. A first signal inverter 110a is illustratively connected between the first input 102a and the gate of the first transistor 108a, and a second signal inverter 110b is illustratively connected between the second input 102b and the gate of the second transistor 108b. [00030] As further shown, the drain of each of the transistors 108a, 108b connects to a capacitor 112, having capacitance C. The drain of each of the transistors 108a, 108b also connects to a first input of a comparator 114, the second input of the comparator receiving a threshold voltage, VTH- [00031] Operatively, the computation circuit 100 performs a weighted average of temporal signals, illustratively provided by the two step inputs. The rising edge of a step input at the first input 102a occurs at time t/. The rising edge of the step input at the second input 102b occurs at time t2. Each of the transistors 108a, 108b acts as a switch. Accordingly, at tι, the increase in voltage at the gate of the first transistor 108a opens a path for the first current source 106a connected to the first transistor. The first current source 106a provides a current //. The resulting current, //, reaches the capacitor 112 connected to the first transistor 108a, and the capacitor begins to charge. If ^ > t/, then the increase in voltage at the gate of the second transistor occurs subsequently. When it does, the increase in voltage at the gate of second transistor 108b opens a path for the second current source 106b that is also connected to the capacitor 112. With the path open, the second current source 106b provides a current, I 2, to the capacitor 112, and the rate that the capacitor charges increases correspondingly. [00032] Initially, a voltage across the capacitor 1 12 can be reset to Ov. The voltage remains at zero until t/ when the step in voltage at the gate of the first transistor 108a occurs, turning on the first transistor. The charge across the capacitor 112 continues to increase until t2 when the step in voltage at the gate of the second transistor 108b occurs, turning on the second transistor and causing the voltage across the capacitor to increase faster. The comparator 114 senses the voltage across the capacitor 112, and when the voltage reaches the threshold, Vm, the comparator responds by generating a step output. The time at which the step output occurs is designated tour- [00033] During the period between t\ and t2, the voltage, Vlemp, across the capacitor 112 is:

/ ,

where // is the current provided by the first current source 106a and C is the capacitance of the capacitor 112. [00034] Similarly, during the period ^ to tour, the voltage across the capacitor is:

wherein, // is again the current provided by the first current source 106a, I2 is the current provided by the first current source 106b, and C is again the capacitance of the capacitor 112. [00035] The preceding equations can be used to solve for an equation describing the output of the circuit in terms of time; that is in terms of a time-based parameter as opposed to one based on either voltage or current:

where, as described above, tour is the time at which the output step occurs; that is, when the output of the circuitry transitions from a low voltage to a high voltage. [00036] Thus, the two current sources 106a, 106b connected to a respective source of each of the transistors 108a, 108b charge the capacitor 112 according to the particular timing of the respective step inputs, with the result being that the output of the computation circuit 100 is a time-based parameter. The time-based parameter, more particularly, corresponds to a time at which the comparator 114, sensing the voltage across the capacitor 112, generates a step output when the voltage across the capacitor reaches the threshold voltage VTH of the comparator. [00037] From the above equation, it is observed that the computation circuit 100 computes the weighted average of two input time steps occurring at t2 and t/ when the condition | I2I1 - //, |< CVTH is met. [00038] When I1 =I2=I, the following is obtained:

[00039] This output corresponds to an unweighted (simple) averaging of the two input

time steps occurring at is met, offset by the time interval represented by CVTH/2I. By varying the amount of current provided by the current sources // and I 2, so that // and h are not equal, circuit 100 could compute the weighted average of two input signals. For example, if/; = 2/2, input t/ would be given twice the weight given to tj. [00040] It should be noted at this point that although the operation of a computation circuit according to the invention is herein described primarily in terms of voltage step inputs, the invention can readily be adapted to process other types of signals and other signal forms corresponding to discrete timing events. For instance, the computation circuits can perform computations based upon current-based step inputs, provided that the circuit uses this input to open or close an appropriate switch provided by a PMOS or other type of transistor. For example, if current-based inputs are used in place of voltage-based inputs, when a transistor is off, no current flows through its drain to charge the capacitor. However, as soon as a non¬ zero current input is provided, the transistor turns on and starts to conduct current from the current source to charge the capacitor as already described. [00041] Moreover, although only two step inputs are provided to the computation circuit 100 shown in FIG. 1, with an appropriate number of inputs added, an arbitrary number of input steps, such as 3, 4, 5, or more step inputs can be received. Note also that the signal inverters 110a, 110b shown in FIG. 1 would not be necessary if n-channel metal oxide semiconductor (NMOS) transistors were used to sink current instead of PMOS transistors. [00042] Referring now to FIG. 2, a time-mode analog computation circuit 200, according to another embodiment of the invention is illustrated. The computation circuit 200 illustratively includes a first input 202a and a second input 202b for receiving, respectively, a first temporal input signal at t/ and a second temporal input signal at time t2. The computation circuit also includes circuitry 204 for performing a mathematical operation based on the temporal input signals, the mathematical operation defining the computation of a weighted or unweighted sum of the two temporal input signals and the result of the mathematical operation being expressed as a timing of an output signal generated by the circuit. [00043] The circuitry 204, more particularly, illustratively includes a first current source 206a, a second current source 206b, and a third current source 206c. The circuitry 204 further includes a first transistor 208a and a second transistor 208b. Illustratively, the first and second transistors 208a, 208b are each PMOS transistors having a source, drain, and gate. The gate of the first transistor 208a is electrically connected to the first input 202a, with a first signal inverter 210a being connected between the gate and first input. The gate of the second transistor 20b is electrically connected to the second input 202b, with a second signal inverter 210b being connected between the gate and second input. The third current source 206c is connected between the drains of the first and second transistors 208a, 208b and ground. [00044] Additionally, the circuitry 204 illustratively includes a capacitor 212 connected between ground and the respective drains of each of the first and second transistors 208a, 208b. The circuitry 204 also illustratively includes a comparator 214 having a first input connected to the respective drains of each of the first and second transistors 208a, 208b and a second input connected to a voltage source providing a threshold voltage, Vm- A logic AND gate 216 having a first input connected to the output of the comparator 214 and a second input for receiving the first temporal input signal at t\ and an output is also a component of the circuitry 204. Illustratively, both the first temporal input signal at tj and the second temporal input signal at time ^ are each step inputs. [00045] The output of the logic AND gate 216 provides a single-ended output. The inputs and outputs occurring at t/, t2 and tour, respectively, are defined with respect to a time reference. When the reference time begins, the third current source 206c provides a current /? that starts discharging the capacitor 212. When the first temporal signal is applied to the computation circuit 200 at time tj, the first current source 206a provides a current Ij. As a result, a total current defined by the difference I1-I3 between the respective currents provided by the first and third current sources 206a, 206c, respectively, starts charging the capacitor 212. When the second input signal is applied to the computation circuit 200 at a time t2, the second current source 202b provides current I2 and the net current //+ I2-h charges the capacitor 212. When the voltage across capacitor 212 reaches the threshold voltage, Vw, of the comparator 214, the computation circuit 200 outputs a step output at time tout. [00046] Without the logic AND gate 216 in series with the output of the comparator 214 shown in FIG. 2, the output of the comparator would contain an unwanted pulse at the reference time because the positive and negative terminals of the comparator would carry the same voltage, VJH - The logic AND gate 216 connected to the output of the comparator 214 ensures that the output from the block contains only a step output at time toυτ, touτ again being the time when the output of the computation circuit 200 illustratively makes its transition from a low to high voltage. The time value, tour is determined according to the following formula:

I 1OfIUT TTT

From equation (2), it is observed that the computation circuit 200 computes a weighted sum of the two step inputs occurring, respectively, at times tt and t2. When I1=I2=Is=I, the following result is obtained: ^- OUT = h "*■ ^2 [00047] This situation corresponds to the sum of two step inputs occurring at ti and tø, as already stated. However, by controlling the magnitudes of the current sources, functionalities different from the block-sum and weighted sum alternately can be obtained. [00048] A computation circuit 300 for computing a weighted difference of two temporal signals, according to yet another embodiment of the invention, is illustrated in FIG. 3. The computation circuit 300 illustratively includes a first input 302a for receiving the first of the two temporal input signals at time tj and a second input 302b for receiving the second of the two temporal input signals at time t2- The computation circuit 300 further includes circuitry 304 for computing the weighted difference, the result of the computation being expressed in a timing of an output signal generated by the circuit. [00049] The circuitry 304 illustratively includes first and second current sources 306a, 306b as well as first and second transistors 308a, 308b. Illustratively, the first transistor 308a is a PMOS transistor having a source, drain, and gate, wherein the source is connected to the first current source 306a and the gate is connected to a signal inverter 310 that, in turn, is connected to the first input 302a. The second transistor 308b is illustratively an NMOS transistor having a source, drain, and gate, wherein the drain of the second transistor is connected to the drain of the first transistor 308a. The gate of the second transistor 308b is connected to the second input 302b, and the source of the second transistor 308b is connected to the second current source 306b. [00050] The circuitry 304 further illustratively includes a capacitor 312 connected between ground and the juncture of the drain of the first transistor 308a and the drain of the second transistor 308b. Also illustratively included in the circuitry 304 is a comparator 314 having first and second inputs and an output. The first input of the comparator 314 is connected to the juncture of the drain of the first transistor 308a and the drain of the second transistor 308b. The second input of the comparator 314 is connected to a voltage source providing a threshold voltage, VTH- The circuitry 304 also illustratively includes a logic AND gate 316. The logic AND gate 316 has a first input connected to the output of the comparator 314 and a second input that receives the first temporal input signal at time t/. Illustratively, both the first temporal input signal at t/ and the second temporal input signal at time t2 are each step inputs. The output of the computation circuit 300 is the output of the logic AND gate 316. The output is a single-ended output having absolute time as its reference. [00051 ] Note that in replacing a PMOS transistor with an NMOS transistor and changing the direction of the current provided by the second current source, the previously described computation circuit 100 is transformed into the computation circuit 300 shown in FIG. 3 for performing a weighted subtraction of input signals occurring at tj and /2- [00052] It is assumed with respect to the computation circuit 300 that the capacitor 316 is initially charged to a voltage Vm- As soon as the first temporal signal, illustratively a step input, is applied to circuit 300 at time ti, the first current source 306a provides a current // that begins charging the capacitor 312. When the step input occurs at time t∑, the second current source 306b provides a current I 2 {h > If) that begins discharging the capacitor 312. When the capacitor 312 voltage reaches the threshold voltage, VTH, the comparator 314 outputs a step output at time touτ- As with circuit 200, the output of the comparator 314 in circuit 300 would contain an unwanted pulse at the reference time because the positive and negative terminals of the comparator would carry the same voltage VTH. The AND gate 316 connected to the output of the comparator 314 ensures that the output from the block contains only a step output at time tour- The output of the computation circuit 300 at time tout is given by the following equation: _ I2t2 - Ixtλ 1OUT ~ j j 2 1 (3) From the equation it is seen equation that the computation circuit 300 applies a weight

to tj.

[00053] Figure 4 illustrates a computation circuit 400 that computes a threshold difference between two temporal signals, according to still another embodiment of the invention. The computation circuit 400 illustratively includes a first input 402a for receiving the first of the two temporal input signals at time tj and a second input 402b for receiving the second of the two temporal input signals at time t2. Illustratively, the computation circuit 400 additionally includes circuitry 404 for computing the threshold difference, the result being expressed in a timing of an output signal generated by the circuit. [00054] The circuitry 404 illustratively includes a first current source 406a and a second current source 406b. The circuitry also illustratively includes a first transistor 408a and a second transistor 408b. The first transistor 408a is illustratively a PMOS transistor having a source, drain, and gate. The source of the first transistor 408a is connected to the first current source 406a, and the gate of the first transistor is connected to a signal inverter 410, which, in turn, is connected to the first input 402a. The second transistor 408b is illustratively an NMOS transistor having a source, drain, and gate. The drain of the second transistor 408b is connected to the drain of the first transistor 408a, and the gate of the second transistor is connected to the second input 402b. The source of the second transistor 408b is connected to the second current source 406b. [00055] Illustratively, the circuitry 404 further includes a capacitor 412 connected between ground and the juncture of the drain of the first transistor 408a and the drain of the second transistor 408b. The circuitry further includes a first comparator 414a and a second comparator 414b. The first comparator 414a has a first input connected to the juncture of the drain of the first transistor 408a and the drain of the second transistor 408b, and a second input of the of the first comparator 414a is connected to a voltage source providing a threshold voltage, VTH.- The second comparator 414b has a first input connected also to the juncture of the drain of the first transistor 408a and the drain of the second transistor 408b. A second input of the second comparator 414b, however, is connected to a voltage source providing a negative threshold voltage, - VTH.- [00056] The computational circuit 400 can be used to check whether the time difference between two temporal signals is greater than or equal to a threshold value (CVTH/I)- One application for such as circuit is for time-based edge detection. For example, the thresholded difference circuit 400 can be used to process the outputs of a time-based imager and determine the presence or absence of edges in images. A similar time-based edge detection circuit can also be used to determine significant differences between adjacent sensors in arrays of any type of time-based sensor, each such sensor generating signals in response to predetermined phenomena or conditions as will be readily understood by one of ordinary skill in the art. [00057] By replacing a PMOS transistor with an NMOS transistor and changing the direction of the second current source in circuit 100, the computation circuit 400 is obtained, which can be used to obtain thresholded differences of steps. There are two situations to be considered assuming that the voltage across capacitor 412 (Vc) is initially reset to a midrange voltage value. [00058] In the first situation, one of two steps inputs ( at ti or at t2, repectively) is applied to circuit 400 before the other. If the initial step input is applied to the first input 402a of the circuit 400 (i.e., t/ < t2), then the first current source 406a provides a current //=/ that linearly charges the capacitor 412 until the capacitor attains the positive threshold VTH- Conversely, if the initial step input is applied to the second input 402b of the circuit 400 (i.e., h < ^/)) then the second current source 406b provides a current /2=/, and the capacitor discharges until the capacitor attains the negative threshold, -Vm- A step outpu at a time tour is given as follows:

where i=\ when the initial step input is applied to the first input 402a, and, alternatively, i=2 when the initial step input is applied to the second input 402b. [00059] The threshold implemented by circuit 400 is CVTH/I- This threshold value can be simply programmed by choosing appropriate values for Vm and /. [00060] In the second situation, the two step inputs arrive within the threshold time CVTH/I- Since the positive and negative current sources exactly cancel each other, no step is generated from either the positive or negative output indicating no edge between pixels. Mismatches between the two current sources will eventually cause one of the outputs to fire, but generally at a time much longer than the frame time of the system. If the threshold time CVTH/I is set to be the minimum difference in intensities required between a bright pixel and dark pixel, circuit 400 can be used to determine the presence or absence of an edge between 2 adjacent pixels. [00061] FIG. 5 illustrates a computation circuit 500 for computing a scalar multiplication of a temporal signal, according to still an embodiment of the invention. The computation circuit 500 illustratively includes an input 502 for receiving a temporal input signal and circuitry 504 for performing scalar multiplication based upon the temporal signal, the result being expressed in a timing of an output signal generated by the circuit. [00062] The circuitry 504 illustratively includes first and second current sources 506a, 506b and a transistor 508. The transistor 508 is illustratively an NMOS transistor having a source, drain, and gate. The drain of the transistor 508 is connected to the first current source 506a, and the source of the transistor is connected to the second current source 506b. The gate of the transistor 508 is connected to the input 502. [00063] The circuitry 504 further illustratively includes a capacitor 512 connected between ground and a juncture of the first current source 506a and the drain of the transistor 508. The circuitry 504 also illustratively includes a comparator 514 having a first input connected to the capacitor and the juncture of the first current source 506a and the drain of the transistor 508. A second input of the comparator 514 is connected to a voltage source that supplies a threshold voltage, VJH- Illustratively, the circuitry 504 also includes a logic AND gate 514 having a first input connected to the output of the comparator 514 and second input for receiving the temporal signal, as shown. The output of computation circuit 500 is the output of the logic AND gate 514. The output of the computation circuit 500 is a single- ended output, and the inputs and outputs are defined with respect to a reference time. [00064] By removing the PMOS transistor that controlled the first current source and replacing the PMOS transistor with an NMOS transistor, while also changing the direction of the second current source of the circuit 100, the computation circuit 500 performs scalar multiplication of a temporal signal entering circuit 500 at time t2. [00065] If it is assumed that the capacitor 512 is initially charged to a voltage, Vm, the first current source 506a starts to charge the capacitor with a current // as soon as the reference time starts. When the input step occurs at time ^, the second current source 506b provides a current h (>//) that starts discharging the capacitor 512. When the capacitor voltage reaches VTH, the comparator outputs a step at time tout. The output of the comparator 514 would also contain an unwanted pulse at the reference time because the positive and negative terminals of the comparator would carry the same voltage VTH. The logic AND gate 516 connected to the output of the comparator 514 ensures that the output from circuit 500 contains only a step output at time tour- The time-based output tout from circuit 500 is given by the following equation:

From equation (5), it is seen that circuit 500 multiplies time tø with a scalar — -

[00066] FIG. 6 illustrates a circuit 600 that computes the maximum of two temporal signals, according to an embodiment of the invention. The circuit 600 supports inputs and outputs that have absolute time as the reference. The output from circuit 600 is a single- ended output. The circuit 600 processes two temporal signals, such as time steps occurring at tj and t2 as illustrated in FIG. 6, and determines the maximum, Max (tj, ti), of the two steps. Thus, if f/ is 300 μs and ^ is 600 μs, tout is 600 μs. If the signal was to be represented using voltages or currents as in conventional computation circuits, an extremely complex circuit would be required to compute Max(F/,F2) or Max(/y, Ii). In time-based analog computation according to the invention, as demonstrated by the circuit 600 shown in FIG. 6, the circuitry to compute Max(//, t}) is substantially simplified. [00067] FIG. 7 illustrates a circuit 700 that computes the minimum of two temporal signals, according to an embodiment of the invention. The circuit 700 supports inputs and outputs that have absolute time as the reference. The output from the circuit 700 is a single- ended output. The circuit 700 processes two time steps, such as time steps occurring at t/ and t2 as shown in FIG. 7, and determines the minimum, Min(t/, ti), of the two steps. The circuit 700 achieves the same efficiencies over conventional computational architectures as noted above relative to circuit 600. [00068] The time-based computation circuits according to the invention are expected to be applicable to a wide variety of applications. For example, present and future VLSI/Nano chips can benefit from the invention. Other applications for time-mode circuits according to the invention include Finite Impulse Response (FIR) and Infinite Impulse Response (IIR) filters, adaptive filters, multilayer perceptrons and other types of neural networks.

Examples [00069] The present invention is further illustrated by the following specific examples, which should not be construed as limiting the scope or content of the invention in any way. [00070] Circuit 100 shown in FIG. 1 was simulated and prototype time-mode circuits according to the invention measured under a variety of conditions. FIG. 8 shows Cadence- Spectre simulation results where circuit 100 was used to compute the arithmetic mean of two input steps, ti and t2. The values of t/, t2, C, Vm and I (I]=I2) used in the simulation were 200 μs, 400 μs, 20 pF, 2.5V and 50 nA, respectively. The output expected from circuit 100 from equation (1) above is 800 μs which includes a 500 μs offset term (CVTH/J) thus computing the actual mean of ti and t2 of 300 μs. The output obtained from simulations performed was 801 μs. It is noted that random variations in this delay and in the current sources can lead to inaccuracies in the calculations generated. [00071] FIG. 9 shows measured data from a fabricated integrated circuit 100 when one step input was provided to circuit 100 (entering circuit 100 at ti) with C=20 pF and Vref=2.5V. The current source I was varied and the output touτ was measured and plotted. CV The output expected from circuit 100 when I= I]=I2 is touτ = t, +- TH

[00072] FIG. 10 shows touτ measured data from circuit 100 when one step input was provided to circuit 100 (entering circuit 100 at ti) with C=20 pF, /=1.0476 uA and The input transition time ti was varied externally from off-chip and the output touτ was CV measured and plotted. The output expected from circuit 100 is touτ = tx + — — which is also

plotted In FIG. 9. The mean squared error between the expected results and the measured results - 7.020IxIO"14 sec2. [00073] FIG. 11 shows touτ measured data from circuit 100 where the first input (ti) entering circuit 100 was fixed as 1 μs, 8.5 μs and 32.5 μs for three different sets of measurements. The circuit 100 components had the following values: C=20 pF, /=1.552 uA and Vw =2.5 V. The transition time (t2) of the second input was varied externally and the output touτ was measured and plotted. The output expected from circuit 100 for different

values of t] and t2 is touτ - J — ~ error between the expected

results and the measured results The Mean squared error between the expected results and the simulated results = 7.0201χ 10"14 sec2. [00074] FIG. 12 shows touτ measured data from circuit 100 where the first input (ti) entering circuit 100 was fixed as 1 μs, 8.5 μs and 32.5 μs for three different sets of measurements. The circuit components had the following values: C=20 pF, // =1.46 uA, h = 0.29 uA and VTH =2.5V. The transition time of the second input (t2) was varied externally and the output touτ was measured and plotted. The output expected from the block for different

values of ti and t2 is touτ = — — + — . The Mean squared error between the expected Ix + I2 I1 + 12 results and the measured results are shown in FIG. 12. [00075] Circuit 100 demonstrated the following measured results under the conditions C=20 pF, Ii = h = 0.29 uA and VTH =2.5V at room temperature: SNR: 56 dB Common-mode DR: Close to Infinity Differential-mode DR: 62 dB Power Consumption: Q.βμW [00076] This invention has been described herein in considerable detail to provide those skilled in the art with information relevant to apply the novel principles and to construct and use such specialized components as are required. However, it is to be understood that the invention can be carried out by different equipment, materials and devices, and that various modifications, both as to the equipment and operating procedures, can be accomplished without departing from the scope of the invention itself.