Title:
TIME-TO-DIGITAL CONVERTING CIRCUIT AND PHASE-LOCKED LOOP
Document Type and Number:
WIPO Patent Application WO/2019/146177
Kind Code:
A1
Abstract:
According to the present invention, power consumption is suppressed in a time-to-digital converting circuit (TDC) used in a phase-locked loop. The time-to-digital converting circuit is provided with an analog-to-digital converting circuit and a current source circuit. The analog-to-digital converting circuit is provided with a prescribed charge capacitor. The current source circuit supplies a charge current that charges an electric charge to the charge capacitor of the analog-to-digital converting circuit. The charge current is supplied by the current source circuit such that a charged voltage has a constant slope over a charge time while the charge capacitor of the analog-to-digital converting circuit is charged by the charge current,.
Inventors:
ETOU SHINICHIROU (JP)
FUJIWARA TETSUYA (JP)
FUJIWARA TETSUYA (JP)
Application Number:
PCT/JP2018/038313
Publication Date:
August 01, 2019
Filing Date:
October 15, 2018
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
H03L7/085; H03K5/26; H03L7/08
Domestic Patent References:
| WO2016104464A1 | 2016-06-30 |
Foreign References:
| US20160373120A1 | 2016-12-22 | |||
| JP2014207569A | 2014-10-30 |
Attorney, Agent or Firm:
MARUSHIMA, Toshikazu (JP)
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