Title:
TRANSISTOR AND DISPLAY DEVICE
Document Type and Number:
WIPO Patent Application WO/2019/187070
Kind Code:
A1
Abstract:
A transistor (1) has, laminated in order upon a substrate (2), a first insulation film (3), an oxide semiconductor layer (4), a gate insulating film (5), an upper gate electrode (6), and a second insulating film (7) and comprises a source electrode (11a) and a drain electrode (11b) that are electrically connected to the oxide semiconductor layer (4) via a contact hole provided in the second insulating film (7). The oxide semiconductor layer (4) has a first channel region (TR1), a second channel region (TR2), and a third channel region (TR3) in a section that overlaps the upper gate electrode (6) in the planar view. The third channel region (TR3) is interposed between the first channel region (TR1) and the second channel region (TR2). The channel width of the third channel region (TR3) is different from the channel widths of the first channel region (TR1) and the second channel region (TR2).
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Inventors:
MIYAMOTO TADAYOSHI
Application Number:
PCT/JP2018/013811
Publication Date:
October 03, 2019
Filing Date:
March 30, 2018
Export Citation:
Assignee:
SHARP KK (JP)
International Classes:
H01L29/786
Foreign References:
| JP2017108065A | 2017-06-15 | |||
| JPS5623780A | 1981-03-06 | |||
| JP2005317851A | 2005-11-10 | |||
| JPH10116990A | 1998-05-06 | |||
| JP2013161895A | 2013-08-19 | |||
| JP2002009289A | 2002-01-11 | |||
| JP2006287220A | 2006-10-19 |
Attorney, Agent or Firm:
ARC PATENT ATTORNEYS' OFFICE (JP)
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