Title:
TRANSMISSION CIRCUIT, INTERFACE CIRCUIT AND MEMORY
Document Type and Number:
WIPO Patent Application WO/2022/041973
Kind Code:
A1
Abstract:
Provided are a transmission circuit, an interface circuit and a memory. The transmission circuit comprises: an upper-layer clock pad (101), which is used for transmitting a clock signal; M upper-layer data pads (102), which are used for transmitting data signals; a lower-layer clock pad (111), which is electrically connected to the upper-layer clock pad (101), wherein the area of the lower-layer clock pad (111) is less than that of the upper-layer clock pad (101); and M lower-layer data pads (112), which are electrically connected in one-to-one correspondence to the M upper-layer data pads (102), wherein the area of each lower-layer data pad (112) is less than that of each upper-layer data pad (102); the upper-layer clock pad (101) and the upper-layer data pads (102) are located in a first layer; the lower-layer clock pad (111) and the lower-layer data pads (112) are located in a second layer; a dielectric layer is arranged between the first layer and the second layer; and the first layer, the dielectric layer and the second layer are all located on the same substrate.
Inventors:
LIN FENG (CN)
Application Number:
PCT/CN2021/101365
Publication Date:
March 03, 2022
Filing Date:
June 21, 2021
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
G11C11/4093; H03M9/00
Foreign References:
| CN111105826A | 2020-05-05 | |||
| CN107463295A | 2017-12-12 | |||
| CN110060970A | 2019-07-26 | |||
| US20140301125A1 | 2014-10-09 | |||
| KR20090045753A | 2009-05-08 | |||
| CN202010873287A | 2020-08-26 |
Other References:
See also references of EP 4027345A4
Attorney, Agent or Firm:
SHANGHAI CHENHAO INTELLECTUAL PROPERTY LAW FIRM GENERAL PARTNERSHIP (CN)
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