TWO-MODULUS PRESCALER CIRCUIT - NIPPON TELEGRAPH & TELEPHONE

Title:

TWO-MODULUS PRESCALER CIRCUIT

Document Type and Number:

WIPO Patent Application WO/2003/058817

Kind Code:

A1

Abstract:

A prescaler circuit comprising n DFF circuits (n≥3); a first multi-input logic gate circuit having two or more inputs; and a second multi-input logic gate circuit, wherein the output terminals of the first multi-input logic gate circuit are connected to the data input terminals of a first DFF circuit; the output terminals of the first through (n - 2)-th DFF circuits are connected to the data input terminals of the second through (n - 1)-th DFF circuits, respectively; the output terminals of the (n - 1)-th and n-th DFF circuits are connected to the input terminals of the first multi-input logic gate circuit; switch signals and the output signals of the (n - 1)-th DFF circuit are inputted to the second multi-input logic gate circuit; the output terminals of the second multi-input logic gate circuit are connected to the data input terminals of the n-th DFF circuit; and wherein all of the foregoing connections use differential signals.

Inventors:

YAMAGISHI AKIHIRO (JP)
TSUKAHARA TSUNEO (JP)
SHIMPO YUKIO (JP)

Application Number:

PCT/JP2002/013190

Publication Date:

July 17, 2003

Filing Date:

December 17, 2002

Export Citation:

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Assignee:

NIPPON TELEGRAPH & TELEPHONE (JP)
NTT ELECTRONICS CORP (JP)
YAMAGISHI AKIHIRO (JP)
TSUKAHARA TSUNEO (JP)
SHIMPO YUKIO (JP)

International Classes:

H03K21/00; H03K23/64; H03K23/66; (IPC1-7): H03K21/00; H03K23/64

Foreign References:

JP2001186012A	2001-07-06
JPH08204541A	1996-08-09
JP2000049590A	2000-02-18

Other References: