FIELD OF THE INVENTION

[001] This invention relates to a two-wire trailing edge dimmer circuit arrangement and more particularly to a two-wire trailing edge dimmer circuit arrangement configured to eliminate or substantially ameliorate the effects of ripple injection signals and/or superimposing of supply authority ripple control signals upon the AC mains supply so as to improve the control of operation of the load under the control of the two-wire trailing edge dimmer circuit arrangement.

BACKGROUND ART DISCUSSION

[002] A two-wire trailing edge dimmer also referred to as reverse phase control dimmer removes power from the end or trailing edge of each AC mains supply half cycle. These two terminal dimmers and the included circuitry control an ON/OFF period of supply of the AC mains supply input wave signal to the load, such as a dimmable lamp, and for the most part are wired in series with the load and the time at which a timer is started and stopped for the ON/OFF period is derived by processing the voltage that appears across the active terminal and load terminal.

[003] For best controlled operation the instant at which the voltage across the active terminal and load terminal falls to zero volts is used as the reference instant to commence the ON/OFF period of supply of the AC mains supply to the load.

[004] Nonetheless the addition of AC voltages to the AC mains supply frequencies, that allow supply authorities to remotely switch equipment, can cause variations in the instant at which the dimmer’s terminal voltage will cross any particular voltage level, including zero volts. Consequently, that in turn causes variations in the time that the dimmer circuit arrangement controlling the operation of the load applies or instigates the ON/OFF period of the AC mains supply to the load, which results in modulation of the power delivered to the load such as a lamp or light and hence causes flickering and/or changes in lamp/light brightness. [005] This ripple injection and/or superimposing of additional AC voltages to the AC mains supply are problematic to effective dimming capabilities and if the two-wire trailing edge dimmer circuit arrangement is going to appropriately be able to control the luminosity of the light or lamp over the dimming range without undesirable light intensity flickering and the like, there will be the requirement to reduce the modulating effects of those supply authority control signals referred to generally hereafter as ripple injection signals.

[006] As the added or injected AC ripple injection signals are at frequencies higher than those of the AC mains supply frequency, trailing edge dimmer circuit arrangements may introduce low pass filtering of the voltage across the active and load terminals into the control circuitry in order to remove these unwanted ripple injection signals.

[007] The prior art provides for low pass filtering means to regenerate a clean fundamental AC mains supply waveform free of ripple injection signals, that is necessarily delayed in time, and then uses a microcontroller to measure and compensate for the delay in the low pass filtering to generate control signals equivalent in time to the instant at which the AC mains supply frequency component of the terminal voltage, in the absence of noise or other interference, would cross zero voltage.

[008] While such hitherto circuit control arrangements are useful for dimming applications when both mains active and neutral wires are available, usually referred to as ‘three terminal’ dimmers, such circuit control arrangements are not suitable for ‘two terminal’ dimmers in which only either the mains active or neutral wire, plus the load wire, are available.

[009] The problem with any low-pass filtering is that it inherently introduces a time delay of the sensed dimmer terminal voltage and generally means that the timing signal that is produced will only become available too long after the dimmer terminal voltage has actually crossed zero volts and therefore too late for use in two-wire trailing edge dimmers that preferably require timing to be provided with the generated reference signal slightly before the dimmer terminal voltage crosses zero volts or at the very least, such timing reference signal must be available in time to initiate the removal of power from the load a short time after the AC mains supply zero crossing.

[010] W O 2017/063022 A1 discloses several arrangements based on high pass separation of the ripple frequencies and cancellation techniques to remove the ripple injection signals which avoids the large delays inherent in conventional low pass filtering, with all described arrangements relying on the cancellation techniques to remove the ripple injection signals using just a conventional single ‘fixed’ voltage as the reference level for the comparator that produces the timing reference signal which instigates the ON/OFF period of the AC mains supply to the load.

[011] The use of a single ‘fixed’ voltage as the reference level for the comparator to assist in removing the effects of ripple injection signals in certain circumstances can influence the range of signals to be handled and therefore potentially influence the performance ability of the two-wire trailing edge dimmer circuit arrangement control to have the comparator produce the timing reference signal instigating the ON/OFF period of the AC mains supply to the load at the required time.

[012] Therefore, an object of this invention is to provide an improved two-wire trailing edge dimmer circuit arrangement configured to eliminate or substantially reduce the effects of ripple injection signals on the incoming AC mains supply so as to more accurately produce the timing reference signal instigating the ON/OFF period of the AC mains supply to the load at the required time than that of the existing prior art arrangements including those discussed above.

[013] Further objects and advantages of the invention will become apparent from a complete reading of the specification.

SUMMARY OF THE INVENTION

[014] In one form of the invention there is provided a two-wire trailing edge dimmer circuit arrangement, said two-wire trailing edge dimmer circuit arrangement including:

[015] a voltage comparator; [016] a low pass filter arrangement, said low pass filter arrangement connectable to an active terminal and a load terminal of an AC mains supply, and wherein the low pass filter arrangement is configured to remove high frequency ripple injection signals from an AC mains supply input wave signal, wherein an output voltage derived from said low pass filter arrangement is coupled to a first input of said voltage comparator;

[017] a reference voltage arrangement, wherein the reference voltage arrangement is connectable to the active terminal and the load terminal of the AC mains supply, wherein the reference voltage arrangement is configured to provide a newly established reference voltage each half cycle of an AC mains supply input wave signal, said newly established reference voltage generated at each half cycle of the AC mains supply input wave signal coupled to a second input of said voltage comparator;

[018] said voltage comparator adapted during each half cycle of the AC mains supply input wave signal to compare voltage of the output voltage derived from the low pass filter arrangement coupled to the first input of the voltage comparator with the newly established reference voltage on the second input of the voltage comparator such than when the compared voltage of the output voltage derived from the low pass filter arrangement matches or falls below the newly established reference voltage, the voltage comparator generates a timing signal for each half cycle of the AC mains supply input wave signal, wherein the generated timing signal for each half cycle of the AC mains supply input wave signal instigates an ON/OFF period of supply of the AC mains supply input wave signal to a load under the control of the two-wire trailing edge dimmer circuit arrangement.

[019] Advantageously, as the voltage comparator is configured during each half cycle of the AC mains supply input wave signal to compare the voltage amplitude of the output voltage derived from the low pass filter arrangement with the newly established reference voltage, the voltage comparator generates the timing signal to instigate the ON/OFF period of supply to the load momentarily before or at a true zero crossing interval of the AC mains supply input wave signal. [020] In preference the low pass filter arrangement includes a pair of equal valued resistors, wherein the pair of equal valued resistors are valued to provide attenuated voltage of the AC mains supply input wave signal to a first capacitor of the low pass filter arrangement, wherein voltage across said first capacitor of the low pass filter arrangement is coupled to the first input of said voltage comparator.

[021] In preference the pair of equal valued resistors includes a first resistor connected to the active terminal of the AC mains supply and a second resistor connected to the load terminal of the AC mains supply.

[022] In preference the equal valued resistors of the low pass filter arrangement provide an attenuated replica of the AC mains supply input wave signal.

[023] In preference the low pass filter arrangement includes further resistors and capacitors for further order filtering of the high frequency ripple injection signals.

[024] In preference the reference voltage arrangement includes a reference voltage arrangement low pass filter.

[025] In preference a peak voltage derived from the reference voltage arrangement low pass filter provides the new reference voltage each half cycle of the AC mains supply input wave signal coupled to the second input of said voltage comparator.

[026] In preference the reference voltage arrangement is configured to couple the derived peak voltage from the reference voltage arrangement low pass filter to the second input of said voltage comparator until voltage of the output voltage derived from the low pass filter arrangement coupled to the first input of said voltage comparator matches or falls below the derived peak voltage from the reference voltage arrangement low pass filter.

[027] In preference the reference voltage arrangement low pass filter includes at least one attenuating resistor and a filter capacitor.

[028] In preference the peak voltage derived from the reference voltage arrangement low pass filter is provided from the voltage across the filter capacitor of the reference voltage arrangement low pass filter during each half cycle of the AC mains supply input wave signal.

[029] In preference the reference voltage arrangement includes a diode configured to maintain coupling of the derived peak voltage from the filter capacitor of the reference voltage arrangement low pass filter to the second input of said voltage comparator until voltage of the output voltage derived from the low pass filter arrangement coupled to the first input of said voltage comparator matches or falls below the derived peak voltage from the filter capacitor of the reference voltage arrangement low pass filter.

[030] In preference the reference voltage arrangement includes a discharge diode, wherein the discharge diode is configured to allow discharge of voltage from the filter capacitor of the reference voltage arrangement low pass filter when voltage of the output voltage derived from the low pass filter arrangement coupled to the first input of said voltage comparator matches or falls below the derived peak voltage from the filter capacitor of the reference voltage arrangement low pass filter allowing establishment of a new derivable peak voltage from the filter capacitor of the reference voltage arrangement low pass filter on a following half cycle of the AC mains supply input wave signal.

[031] In preference the reference voltage arrangement includes a pair of diodes, wherein the pair of diodes is configured to full wave rectify the AC mains supply input wave signal.

[032] In an alternative embodiment of the invention the low pass filter arrangement to which an output voltage from said low pass filter arrangement is coupled to the first input of the voltage comparator has less of a delay in filtering the AC mains supply input wave signal than the delay in filtering the AC mains supply input wave signal from the reference voltage arrangement low pass filter coupled to the second input of the voltage comparator.

[033] In preference the reference voltage arrangement low pass filter arrangement incudes at least a pair of attenuating resistors. [034] In preference resistor attenuation of the pair of attenuating resistors of the reference voltage arrangement low pass filter arrangement provides approximately 80% of a peak voltage amplitude of the output voltage derived from the low pass filter arrangement coupled to the first input of said voltage comparator.

[035] In preference the pair of equal valued resistors and the first capacitor of the low pass filter arrangement are valued to provide a cut off frequency of the low pass filter arrangement approximately twice that of the AC mains supply input wave signal.

[036] In an alternative embodiment of the invention the reference voltage arrangement low pass filter includes a pair of equal valued resistors, an attenuating resistor and a filter capacitor.

[037] In preference the equal valued resistors of the reference voltage arrangement low pass filter provide an attenuated replica of the AC mains supply input wave signal across the filter capacitor coupled to the second input of the voltage comparator wherein the reference voltage arrangement low pass filter is configured to provide a lower cut off frequency of the AC mains supply input wave signal than a cut off frequency of the AC mains supply input wave signal of the low pass filter arrangement coupled to the first input of the voltage comparator.

[038] In preference the voltage comparator is a bipolar junction transistor (BJT).

[039] In preference the BJT transistor is a PNP BJT transistor.

[040] In preference a base of the PNP BJT transistor provides the first input of the voltage comparator.

[041] In preference an emitter of the PNP BJT transistor provides the second input of the voltage comparator.

[042] In preference the output voltage derived from said low pass filter arrangement is coupled to the base of the PNP BJT transistor and wherein the newly established reference voltage generated at each half cycle of the AC mains supply input wave signal is coupled to the emitter of the PNP BJT transistor. [043] In preference a collector of the PNP BJT transistor is coupled to an NPN BJT transistor and wherein the PNP BJT transistor is further configured such that conduction at the base of the PNP BJT transistor occurs whenever voltage of the output voltage from the low pass filter arrangement at the base of the PNP BJT transistor matches or falls below the newly established reference voltage of the reference voltage arrangement low pass filter arrangement at the emitter, wherein conduction at the base of the PNP BJT transistor causes the NPN BJT transistor to switch on.

[044] In preference the timing signal to instigate the ON/OFF period of the supply of the AC mains supply input wave signal to the load is generated each half cycle of the AC mains supply input wave signal when the collector of the NPN BJT transistor falls to zero volts.

[045] In preference the newly established reference voltage provided by the reference voltage arrangement low pass filter arrangement at the emitter of the PNP BJT transistor for each half cycle of the AC mains supply input wave signal is provided from a filter capacitor of the reference voltage arrangement low pass filter arrangement.

[046] In preference the reference voltage arrangement includes a diode configured to maintain the newly established reference voltage for each half cycle of the AC mains supply input wave signal at the emitter of the PNP BJT transistor until voltage of the output voltage derived from the low pass filter arrangement coupled to the base of the PNP BJT transistor matches or falls below the newly established reference voltage.

[047] In preference the newly established reference voltage for each half cycle of the AC mains supply input wave signal at the emitter of the PNP BJT transistor derived from the filter capacitor of the reference voltage arrangement low pass filter arrangement is dischargeable through the PNP BJT transistor once the voltage amplitude of the output voltage derived from the low pass filter arrangement coupled to the base of the PNP BJT transistor matches or falls below the newly established reference voltage. [048] In preference the base of the PNP BJT transistor is connected to a diode, wherein the diode is configured to ensure when output voltage of the low pass filter coupled to the base of the PNP BJT transistor is much greater than the output voltage of the reference voltage arrangement low pass filter coupled to the emitter of the PNP BJT transistor that such a voltage difference does not appear at the base of the PNP BJT transistor.

[049] In preference the base of the PNP BJT transistor is connected to a resistor, wherein the resistor is valued to prevent leakage current from the diode connected to the base of the PNP BJT causing the emitter-base voltage rating of the PNP BJT transistor to be exceeded.

[050] In a further form of the invention there is provided a two-wire trailing edge dimmer circuit arrangement, said two-wire trailing edge dimmer circuit arrangement including:

[051] a voltage comparator;

[052] a high frequency cancellation arrangement, said high frequency cancellation arrangement connectable to an active terminal and a load terminal of an AC mains supply, and wherein the high frequency cancellation arrangement is configured to cancel out high frequency ripple injection signals from an AC mains supply input wave signal, wherein voltage amplitude of a cleaned AC mains supply input wave signal having said high frequency ripple injection signals cancelled by the high frequency cancellation arrangement is coupled to a first input of said voltage comparator;

[053] a reference voltage arrangement, wherein the reference voltage arrangement is configured to receive the cleaned AC mains supply input wave signal having said high frequency ripple injection signals cancelled by the high frequency cancellation arrangement, wherein the reference voltage arrangement is further configured to provide a newly established reference voltage from the cleaned AC mains supply input wave signal each half cycle of an AC mains supply input wave signal, said newly established reference voltage generated at each half cycle of the AC mains supply input wave signal coupled to a second input of said voltage comparator;

[054] said voltage comparator adapted during each half cycle of the AC mains supply input wave signal to compare voltage amplitude of the cleaned AC mains supply input wave signal having said high frequency ripple injection signals cancelled by the high frequency cancellation arrangement coupled to the first input of the voltage comparator with the newly established reference voltage on the second input of the voltage comparator to generate a timing signal for each half cycle of the AC mains supply input wave signal, wherein the generated timing signal for each half cycle of the AC mains supply input wave signal instigates an ON/OFF period of supply of the AC mains supply input wave signal to a load under the control of the two-wire trailing edge dimmer circuit arrangement.

[055] In preference the high frequency cancellation arrangement includes a filter adapted to filter the high frequency ripple injection signals from the AC mains supply input wave signal and wherein the high frequency cancellation arrangement is further configured to invert the filtered high frequency ripple injection signals to provide for an inverted filtered high frequency ripple injection signal.

[056] In preference the high frequency cancellation arrangement is further configured to combine the inverted filtered high frequency ripple injection signal with the AC mains supply input wave signal having said high frequency ripple injection signals superimposed thereon to eliminate the high frequency ripple injection signals from the AC mains supply input wave signal to provide the cleaned AC mains supply input wave signal.

[057] In preference the voltage comparator is a bipolar junction transistor (BJT).

[058] In preference the BJT transistor is a PNP BJT transistor.

[059] In preference voltage of the cleaned AC mains supply input wave signal having said high frequency ripple injection signals cancelled by the high frequency cancellation arrangement is coupled to the base of the PNP BJT transistor and wherein the newly established reference voltage generated at each half cycle of the AC mains supply input wave signal is coupled to the emitter of the PNP BJT transistor.

[060] In preference the reference voltage arrangement includes a capacitor, wherein the reference voltage arrangement is further configured to charge said capacitor to a peak voltage each half cycle of the cleaned AC mains supply input wave signal, wherein the peak voltage is equal to the input voltage of the cleaned AC mains supply input wave signal coupled to the base of the PNP BJT transistor.

[061] In preference the timing signal to instigate the ON/OFF period of the supply of the AC mains supply input wave signal to the load is generated each half cycle when voltage across the active terminal and the load terminal begins to fall and voltage derived from the cleaned AC mains supply input wave signal at the base of the PNP BJT transistor falls to approximately 0.6V below the newly established reference peak voltage from the capacitor of the reference voltage arrangement.

[062] In preference the two-wire trailing edge dimmer circuit arrangement further includes a detector arrangement that monitors a rate of increase of voltage across the active terminal and the load terminal and wherein the detector arrangement further monitors an instant at which voltage across the active terminal and the load terminal ceases to be increasing.

[063] In preference the two-wire trailing edge dimmer circuit arrangement is configured to force an attenuated voltage derived from the voltage across the active terminal and the load terminal to decrease at a rate sufficient to activate the voltage comparator wherein said forcing is activated when the voltage across the active terminal and the load terminal stops increasing.

[064] In preference the two-wire trailing edge dimmer circuit arrangement further includes a voltage detector arrangement configured to monitor voltage amplitude across the active terminal and the load terminal at a start and an end of each OFF time of the ON/OFF period of the supply of the AC mains supply input wave signal to the load. [065] In preference the voltage detector arrangement configured to monitor voltage amplitude across the active terminal and the load terminal at the start and the end of each OFF time of the ON/OFF period of the supply of the AC mains supply input wave signal to the load time includes an additional comparator using an absolute reference voltage and a high valued resistor ensuring no loading on the voltage comparator input voltage.

[066] In preference the output of the voltage detector arrangement configured to monitor voltage amplitude across the active terminal and the load terminal at the start and the end of each OFF time of the ON/OFF period of the supply of the AC mains supply input wave signal to the load is combined in a logical OR arrangement of the voltage comparator and the additional comparator.

[067] In preference the voltage comparator and the additional comparator are both PNP BJT transistors.

BRIEF DESCRIPTION OF THE DRAWINGS

[068] Figure 1 is a two-wire trailing edge dimmer circuit arrangement in a preferred embodiment of the invention.

[069] Figure 2 is a two-wire trailing edge dimmer circuit arrangement in a further preferred embodiment of the invention.

[070] Figure 3 is a two-wire trailing edge dimmer circuit arrangement in a further preferred embodiment of the invention.

[071] Figure 4 is a two-wire trailing edge dimmer circuit arrangement in a further preferred embodiment of the invention.

[072] Figure 5 is a two-wire trailing edge dimmer circuit arrangement in a further preferred embodiment of the invention.

[073] Figure 6 is a two-wire trailing edge dimmer circuit arrangement in a further preferred embodiment of the invention. DETAILED DESCRIPTION OF THE DRAWINGS

[074] Referring to the drawings now in greater detail wherein Figure 1 provides a two-wire trailing edge dimmer circuit arrangement, shown generally as (10) that provides a stable timing reference signal from the comparator (12) to a gate drive control circuit arrangement (36), wherein the gate drive control circuit arrangement (36) is responsible for controlling through the Field Effect Transistors (FETs) (20) and (22) the ON/OFF period of supply of the AC mains supply input wave signal to a load (not shown) under the control of the two-wire trailing edge dimmer circuit arrangement (10).

[075] The FETs (20) and (22) comprise the switch control for the load (14) (not shown) which as introduced above are controlled by the gate drive control circuit arrangement (36). As illustrated FETs (20) and (22) each has corresponding intrinsic body diodes (17) and (19) that allow conduction of current in one direction and with the FETs (20) and (22) configured in a back to back arrangement the FETs (20) and (22) allow current flow to be controlled in either direction.

[076] The AC mains supply input wave signal to place this invention in the context of its application also includes the effects of the ripple injection signals and/or the superimposed supply authority ripple control signals which are riding there upon the AC mains supply input wave signal which is inputted to the two-wire trailing edge dimmer circuit arrangement (10) via active voltage terminal (14) and load voltage terminal (16).

[077] The focus of this invention is how a Comparator (12) generates a timing signal sent on line (34) from the output (35) of the comparator (12) for each half cycle of the AC mains supply input wave signal that is inputted into the gate drive control circuit arrangement (36), so the gate drive control circuit arrangement (36) through a control signal path line (37) to the gates of the FETs (20) and (22) can commence the required ON/OFF period of supply of the AC mains supply input wave signal to the load under the control of the two-wire trailing edge dimmer circuit arrangement (10) at or as close as possible to a true zero voltage crossing of the AC mains supply input wave signal as provided at the dimmer terminals via the load. [078] Equal value resistors (40) and (41 ) supply positive parts of the AC mains supply input wave signal to a filter capacitor (43) that forms a shunt branch of a single order low pass filter arrangement wherein the output voltage derivable across the filter capacitor (43) is inputted into the positive input (44) of the comparator (12).

[079] Diodes (46) and (47) full-wave rectify the AC mains supply input wave signal, wherein resistor (48), capacitor (49) and the attenuating resistor (50) provide for a low pass filter arrangement which will form the basis of establishing a new reference voltage each half cycle of the AC mains supply input wave signal that will be coupled to the negative input (52) of the comparator (12).

[080] A peak voltage for each half cycle of the AC mains supply input wave signal across capacitor (49) is held by diode (51) at the negative input (52) of comparator (12).

[081] The peak voltage developed across capacitor (49) is held by diode (51) until the timing reference signal on (34) is generated at the output (35) of the comparator (12).

[082] The low pass filter arrangement made up of resistors (40), (41 ) and filter capacitor (43) removes any high frequency ripple injection signals from the AC mains supply input wave signal wherein then the output voltage derived across filter capacitor (43) is coupled to the positive input (44) of the comparator (12).

[083] The voltage, as introduced above, which is then coupled to the negative (52) input of the comparator (12) is derived from the reference voltage arrangement made up of resistors (48) and (50) and the capacitor (49) wherein that peak voltage being developed across capacitor (49) from a ripple frequency cleaned AC mains supply input wave signal is held through the unique inclusion of diode (51 ) and to couple that generated peak voltage to negative input (52) of comparator (12) so as to allow the comparator during each half cycle of the AC mains supply input wave signal to compare voltage amplitude of the output derived from the filter capacitor (43) coupled to the positive input (44) of the comparator (12) with the peak voltage derived across capacitor (49) and held there by diode (51) coupled to the negative input (52) of the comparator (12) so that when the voltage amplitude of the positive input (44) of the comparator (12) falls below the held peak voltage coupled to the negative input (52) of the comparator (12) the timing reference on (34) from the output (35) of the comparator (12) will be generated.

[084] When the amplitude voltage across capacitor (43) inputted into positive input (44) of the comparator (12) falls below the peak voltage obtained from capacitor (49) at the negative input of the comparator (12), diode (54) allows the discharge of capacitor (49) so that on the next half cycle of the AC mains supply input wave signal a newly established reference voltage can again be coupled to the negative input (52) of the comparator (12) derived from the peak voltage from the capacitor (49).

[085] The amplitude of the voltage level on capacitor (49), that is the peak voltage which is newly established each half cycle of the AC mains supply input wave signal as the reference voltage to the negative input (52) of comparator (12) is determined by the selection of the resistor values (48) and (50) and capacitor (49).

[086] Generally the established reference voltage would be chosen to be approximately 80% of the peak voltage that is inputted into the positive input (44) of the comparator (12). In this way the generated timing reference signal on (34) from the output (35) of the comparator (12) will be generated at the instant when the voltage across the filter capacitor (43) which is coupled to the positive input (44) of the comparator (12) has fallen from the peak voltage value to below 80% of the peak voltage value.

[087] Generally the cut off frequency of the low pass filter arrangement made up of resistors (40) and (41) with the filter capacitor (43) is selected slightly above twice the AC mains supply input wave frequency. The cut off frequency of capacitor (49) which forms the part of the low pass filter arrangement to which the peak voltage is coupled to the negative input (52) of the comparator (12) which provides the newly established reference voltage at each half cycle of the AC mains supply input wave to the comparator (12) is preferably selected to be lower than the cut off frequency for the low pass filter arrangement derived from resistors (40), (41) and filter capacitor (43). [088] By selecting the cut off frequencies and also attenuation of resistors (48) and (50) it is possible to arrange that the timing reference signal on (34) is generatable up to 1 milliseconds before normal AC mains supply input wave signal zero voltage crossing. That is advantageous when for example a load such as a lamp has its ON time is set to dimmest and turn off is generated close to, or slightly after, zero voltage crossing.

[089] Accordingly, a timing reference signal on (34) derived from the output (35) of the comparator (12) into the gate drive control circuit arrangement (36) is always available to start the ON time of the timer within the gate drive control circuit arrangement (36) that determines the instant the load turns OFF, well before it is required. For example, if the lamp is required to be at the dimmest and is required to be turned OFF at 1 millisecond after a zero voltage crossing, the generated timing signal on (34) will have been provided 1 millisecond before the zero voltage crossing and the timer within the gate drive control circuit arrangement (36) will generate a time of 2 milliseconds.

[090] Further, if the lamp is brightest, thereby requiring the ON time to be turned OFF about 7-8 milliseconds after the zero voltage crossing the timing signal is already available at around the zero voltage crossing interval.

[091] While the two-wire trailing edge dimmer circuit arrangement (10) shown in Figure 1 utilizes the basic structure of a conventional low pass filter to remove the high frequency ripple injection signals which will inherently introduce a time delay of the sensed terminal voltage across the active terminal (14) and the load terminal (16), this problem is overcome and the timing signal sent to the gate drive control circuit arrangement (36) can still be timed appropriately so that the ON/OFF period of AC mains supply to the load can commence at the true zero voltage crossing interval and not some time thereafter because through the use of comparator (12) the comparison with that voltage amplitude coupled to the positive input (44) of the comparator (12) is compared, not with a fixed reference value, but alternatively with a newly established reference voltage that is coupled to the negative input (52) of the comparator (12) which is derived from the peak voltage obtained across capacitor (49) in the preferred embodiment shown in Figure 1 [092] Figure 2 shows an alternative two-wire trailing edge dimmer arrangement (60).

[093] The low pass filter arrangement made up of resistors (61 ) and (62) and filter capacitor (63) remains consistent with the discussions detailed in Figure 1 that provide a filtered AC mains supply input wave signal where the high frequency ripple injection signals have been removed with the voltage across the filter capacitor (63) then coupled to the positive input (64) of the comparator (65). However, instead of rectifying and peak detecting the voltage available across the active terminal (14) and load terminal (16) to newly establish a reference voltage generatable at each half cycle of the AC mains supply input wave signal, a low pass filter made up of resistors (66), (67), attenuating resistor (68) and filter capacitor (69) can be utilized that have an even lower cut off frequency with respect to the cut off frequency of the low pass filter arrangement coupled to the positive input (64) of the comparator (65) than was discussed in Figure 1.

[094] The longer filter delay ensures that the positive input (64) to the comparator (65) will initially be larger than the voltage coupled to the negative input (70) of the comparator (65) while the voltage across the active terminal (14) and load terminal (16) is rising, but will fall below it when the voltage of the incoming AC mains supply input wave across the active terminal (14) and load terminal (16) is falling.

[095] Diode (71 ) has the same function of diode (54) in Figure 1 , whereby the voltage derived from the filter capacitor (69) coupled to the negative input (70) of the comparator (65) becomes dischargeable through diode (71) once the timing signal is generated on (72) so that again a newly established reference voltage becomes coupled to the negative input (70) of the comparator (65) for the next half cycle of the AC mains supply input wave signal.

[096] Operation of the gate drive control circuit arrangement which in Figure 2 is shown as (73) and the controlling ON/OFF period of supply of the AC mains supply input wave signal to a load under the control of the two-wire trailing edge dimmer circuit arrangement (60) through FETS (74) and (75) remain consistent with the discussions detailed for these features in Figure 1. [097] The two-wire trailing edge circuit arrangements (80) for Figure 3 and (100) for Figure 4 operate on the same general principle as the two-wire trailing edge dimmer circuit arrangement (10) in Figure 1 and (60) in Figure 2, however in both Figures 3 and 4 the comparator is a PNP BJT transistor.

[098] The low pass filter that includes the equal valued resistors (84) and (85) and the filter capacitor (83) makes available that output voltage of the filter capacitor (83) to the base (81) of the PNP BJT transistor (82).

[099] The two-wire trailing edge circuit arrangements (80) also includes as in Figure 1 , rectifier diodes (76) and (77) and wherein the low pass filter which includes resistors (86) and (87) as well as the filter capacitor (88) makes up the reference voltage arrangement responsible for establishing the reference voltage duly generated at each half cycle of the AC mains supply input wave signal and which is then coupled to the emitter (89) of the PNP BJT transistor (82).

[0100] Therefore, in essence the PNP BJT transistor (82) functions so as to generate a required timing signal on (90) into the gate drive control circuit arrangement also shown as (36) in Figures 3 and 4 for the operation of the gate drive control circuit arrangement (36) in Figures 3 and 4 and the control of the corresponding FETS (20) and (22) in order to provide the required ON/OFF period of supply of the AC mains supply input wave signal to the load under the control of the two-wire trailing edge circuit arrangement at, or as close as possible, to the true zero voltage crossing of the AC mains supply input wave signal will be the same in Figures 3 and 4 as that discussed in the context of Figures 1 and 2.

[0101] The only real differences between the fundamental operation of the two-wire trailing edge dimmer circuit arrangements (10) and (60) in Figures 1 and 2, as introduced above, in this embodiment shown in Figure 3 is the introduction of the PNP BJT transistor (82) to act as the comparator, wherein voltage matching and/or differences between its base and emitter generate the timing signal (90) using the newly established reference voltage generated across the filter capacitor (88) at each half cycle of the AC mains supply input wave signal which is coupled to the emitter (89) of the PNP BJT transistor (82). [0102] The voltage on filter capacitor (83) rises as the terminal voltage across the active terminal (14) and load terminal (16) rises. The terminal voltage which naturally would have a peak voltage at 5 milliseconds after an AC mains supply input wave signal zero voltage crossing, is delayed by the action of the low pass filter arrangement of resistor (84) and filter capacitor (83) or resistor (85) with filter capacitor (83) whereby the peak voltage of the terminal voltage is closer to 7 milliseconds.

[0103] The voltage of filter capacitor (88) which is coupled to the emitter (89) of the PNP BJT transistor (82) has a peak voltage at a similar timing because the low pass filter associated with that voltage across filter capacitor (88) made up of resistors (86) and (87) with the filter capacitor (88) in the preferred embodiment is configured to have a cut off frequency similar to the low pass filter arrangement made up of filter capacitor (83) and resistors (84) and (85) coupled to the base of the PNP BJT transistor.

[0104] Consistent with discussions detailed in Figures 1 and 2, diode (91) prevents a discharging of filter capacitor (88) after the voltage caused by resistors (86) and (87) has reached peak voltage and commences to fall.

[0105] The output of the PNP BJT transistor (82) controls the voltage at the collector

(94) of the NPN BJT transistor (95). When the PNP BJT (82) is off, collector (94) will be the same as the supply voltage, which in this instance is plus 10 volts shown generally as (96) connected through resistor (79), because the NPN BJT transistor

(95) is turned OFF. It is OFF whenever the voltage across filter capacitor (83) of the low pass filter arrangement that includes resistor (84) with filter capacitor (83) or resistor (85) with filter capacitor (83) coupled to the base of the PNP BJT transistor (82) is greater than that of the voltage of filter capacitor (88) which is part of the reference voltage arrangement which couples that voltage of filter capacitor (88) to the emitter (89) of the PNP BJT transistor (82).

[0106] When the voltage of filter capacitor (83) coupled to the base (81) of the PNP BJT transistor (82) falls below the voltage on filter capacitor (88) coupled to the emitter (89) of the PNP BJT transistor (82) by approximately 1.2 volts, this is then sufficient to cause conduction in diode (97) and the PNP BJT transistor (82) which then, in turn, turns ON the NPN BJT transistor (95) and the collector (94) voltage will fall to zero volts.

[0107] In the preferred embodiment shown in Figures 3 it is the falling edge of the collector voltage to zero volts which then instigates the timing signal on (90) into the gate drive control circuit arrangement (36) to commence the required ON/OFF period of supply of the AC mains supply input wave signal to the load.

[0108] Diode (97) and resistor (98) are included to ensure that, when the voltage on filter capacitor (83) is much greater than the voltage that is on filter capacitor (88), this voltage difference will not appear at the base (81) of the PNP BJT transistor (82) and cause an emitter-based reverse voltage rating, typically around 5 volts, to be exceeded.

[0109] Value of resistor (98) will be chosen so that any leakage current of diode (97) does not cause the PNP BJT transistor (82) emitter-base voltage to be exceeded. A typical value is 1 megaohm. Once the voltage on filter capacitor (83) coupled to the base of the PNP BJT transistor (82) falls below that on filter capacitor (88) coupled to the emitter (89) of PNP BJT transistor (82), and PNP BJT transistor (82) is conducting, filter capacitor (88) will be discharged by the emitter current of PNP BJT transistor (82) thereby allowing, once again, the generation of a new reference voltage across the filter capacitor (88) on the following half cycle of the AC mains supply input wave signal. The current that flows into the NPN BJT transistor (95) base (99) ensures that the NPN BJT transistor (95) is turned ON. Resistor (78) is valued around 470k ohms to prevent small leakage currents in PNP BJT transistor (82) from turning ON the NPN BJT transistor (95).

[0110] In Figure 4, resistor (102) is chosen about 1/40 of the value of resistor (101) to give an attenuation of the peak terminal voltage across the active terminal (14) and the load terminal (16) by a factor of approximately 40x, for example, resistor (101) = 2.2 M ohms and resistor (102) = 56 k ohms. Filter capacitor (103) is chosen to give a conventional low pass filter cut off frequency of around 130 Hz. The attenuator made up of resistors (104) and (105) in combination with the filter capacitor (106) are chosen to have a slightly greater attenuation and a slightly lower cut off frequency.

[0111] When the scaling of the terminal voltage across the active terminal (14) and the load terminal (16) is applied and resistors (102) and (105) are relatively low in value to provide sufficient discharge of filter capacitor (103) coupled to the base (109) of the PNP BJT transistor (110) and the filter capacitor (106) coupled to the emitter (111 ) of the PNP BJT transistor (110) on each half cycle of the AC mains supply input wave signal, it is no longer necessary to use special connections of resistors (84) and (85) to the corresponding active terminal (14) and the load terminal (16) as shown in Figure 3, wherein using the conventional connection of resistor (101) and (104) after rectifier diodes (114) and (116) as illustrated in Figure 4 will be adequate.

[0112] Diode (117) provides voltage peak rectification of the reference voltage on filter capacitor (106) and the PNP BJT transistor (110) provides for discharge of the filter capacitor (106) on each half cycle of the AC mains supply input wave signal as filter capacitor (106) is not allowed to hold the largest voltage peak reference voltage as it must follow any variations. Resistor (119) will have a large value, for example 2.2 M ohms, to bypass any leakage current in the PNP BJT transistor (110) when it is OFF while avoiding loss of drive current to NPN BJT transistor (124) when it is ON.

[0113] As the voltage on filter capacitor (103) is greater than the voltage on filter capacitor (106) while the terminal voltage across the active terminal (14) and the load terminal (16) is rising there is no conduction in the PNP BJT transistor (110) during this time interval. Only when the voltage on the filter capacitor (103) falls below the peak voltage held at filter capacitor (106) will the PNP BJT transistor (110) act to discharge the filter capacitor (106) such that the newly established reference voltage can then be generated on the following half cycle of the AC mains input wave signal.

[0114] Operation of the PNP BJT transistor (110) as the comparator with lower voltages on the filter capacitor (103) and capacitor (106) means diode (97) in Figure 3 is no longer required to protect the PNP BJT transistor (110) emitter base from breakdown. Again, with the PNP BJT transistor (110) performing the comparator function the operation of the NPN BJT transistor (124) coupled to the supply voltage (125) through resistor (126) on the collector (127) side of the NPN BJT transistor (124) operates in the same function to generate the timing signal on (129) into the gate drive control circuit arrangement (36) so that once again the gate drive control circuit arrangement (36) receives the timing signal at, or as close as possible to, the true zero voltage crossing time interval of the AC mains supply input wave signal to then commence the required ON/OFF period of supply of the AC mains supply input wave signal to the load under the control of the two-wire trailing edge dimmer circuit arrangement (100) shown in Figure 4.

[0115] In Figure 5 and Figure 6 the low pass filter arrangement which was discussed in Figures 1 - 4 to remove the ripple injection signals from the AC mains supply input wave signal has been replaced with a high frequency cancellation arrangement which will be able to cancel out the effects of the ripple injection signals from the AC mains supply input wave signal.

[0116] As will be discussed in greater detail shortly hereafter, for the most part the high frequency cancellation arrangement to remove the ripple injection signals from the AC mains supply input wave signal will utilize a filter arrangement adapted to filter the high frequency ripple injection signals and then be able to invert these filtered high frequency ripple injection signals to provide an inverted signal which then can be added back to the AC mains supply wave signal having the ripple injection signals superimposed thereon so that these high frequency ripple injection signals can then be eliminated through cancellation to provide the cleaned AC mains supply input wave signal to which referencing therefrom can be utilized by the comparator arrangement so as to generate the timing signal for each half cycle of the AC mains supply input wave signal to instigate the ON/OFF period of supply of the AC mains supply input wave signal to the load under the control of the two-wire trailing edge dimmer circuit arrangement at the required time interval relative to the zero voltage crossing.

[0117] In Figure 5 voltage between the active terminal (130) and the load terminal (132) is bridge rectified by diodes (134), (135) and the two parasitic diodes (136) and (137) contained in the FETs (138) and (139). [0118] The voltage of the incoming AC mains supply input wave signal is scaled by a resistive voltage divider network consisting of resistors (140), (141) and (142) to yield two voltages that are then processed to remove high frequency ripple injection signals from the inputted AC mains supply input wave signal in the range of 700 Hz to 1100 Hz.

[0119] The voltage appearing across resistor (142) is chosen to be approximately 1 /5 ^th the amplitude of the voltage across resistors (141) plus (142). For example, the preferred value of resistor (140) is 560k ohms, resistor (141) 82k ohms and resistor (142) 22k ohms. The voltage across resistor (142) is chosen to be approximately 1/30 of the voltage across the active terminal (130) and the load terminal (132) thereby for an AC mains supply input wave signal of 230 volts reaches peaks approximately 340V/30 equaling 11V.

[0120] The voltage across resistors (141) and (142) is band pass filtered by the series capacitor (143), shunt capacitor (144) and resistor (145) in series with resistor (146). For signals greater than approximately 0.6V, of either polarity, the impedance of diode (147) or the emitter base of PNP BJT transistor (148) in series with resistor (179) is very small compared with the impedance of resistors (145) and (146) which in a preferred embodiment would be chosen to be approximately 330k ohms each.

[0121] Resistor (179) is a low value resistor, approximately 10k ohms. The arrangement of PNP BJT transistor (148) and PNP BJT transistor (149) can be referred to as a ‘current mirror’. If transistors (148) and (149) are identical transistors then a current flowing from the power supply (150), which in this preferred embodiment would be a 10V supply, that flows into resistor (146) will cause a current of nearly equal value to flow from the collector (151) of the PNP BJT transistor (149) into resistor (158). It is assumed that during normal operation there will be no current in the protecting zener diode (153) and the base currents of PNP BJT transistor (154) and PNP BJT transistor (155) will be negligible.

[0122] Practically, as PNP BJT transistor (148) and PNP BJT transistor (149) are not identical, although very similar, the inclusion of resistors (179) and (156), valued to have a voltage drop across each of them of the order of 100 - 200mV at the currents flowing in the transistor emitters, will ensure the ‘mirror current’ action is achieved even if PNP BJT transistor (148) and PNP BJT transistor (149) are not identical.

[0123] The components of the band pass filter are selected to ensure the phase shift in the filter remains close to zero over the range of the high frequency ripple injection signals to be handled. The arrangement causes the collector current of PNP BJT transistor (149) to be inverted at the high frequency of the ripple injection signals.

[0124] If the terminal voltage across the active terminal (130) and the load terminal (132) is falling in magnitude due to the effects of ripple injection signals, the voltage across resistor (142) and (resistor (141) + resistor (142)) is falling however as the PNP BJT transistor (148) is connected to the 10V power supply (150) that decrease in voltage across (resistor (141) + resistor (142)) causes an increase in the voltage across (resistor (145) + resistor (146)) and an increase in the collector current of PNP BJT transistor (148) and an equal increase in the collector current of PNP BJT transistor (149).

[0125] This increase in the collector current of the PNP BJT transistor (149) causes a voltage drop across resistor (158) to be increasing while the voltage across resistor (142) is decreasing. For the high frequency ripple injection signals, voltage at the junction of resistor (158) and the PNP BJT transistor (149) does not change when the AC mains supply input wave signal, having high frequency ripple injection signals superimposed thereon, appears across the active terminal (130) and the load terminal (132).

[0126] Accordingly, this arrangement effectively cancels the high frequency ripple injection signals from the AC mains supply input wave signal and while this cancellation of the high frequency ripple injection signals from the AC mains supply input wave signal does inherently place a time delay on the AC mains supply input wave signal appearing at the junction of resistor (158) and PNP BJT transistor (149), this time delay is much smaller than when using more conventional low pass filter arrangements to remove the effects of high frequency ripple injection signals that have been superimposed on to the AC mains supply input wave signal. [0127] As the fundamental AC mains supply input wave signal has not been filtered by the cancellation process, the voltage at the junction between resistor (158) and the PNP BJT transistor (149) is still a fraction of the voltage across the active terminal (130) and the load terminal (132) set by the voltage divider of resistor (142) and (resistor (140) + resistor (141)). The action of the ‘current mirror’ requires current to be flowing from the PNP BJT transistor (148) collector into resistor (146). The capacitive coupling of the terminal voltage across the active terminal (130) and the load terminal (132) via capacitor (143) means that current only happens while the terminal voltage is decreasing at the fundamental frequency of the AC mains supply input wave signal frequency which is 100 Hz because it has been full-wave rectified by diodes (134) and (135).

[0128] When the terminal voltage across the active terminal (130) and the load terminal (132) is increasing current in the capacitor (143) flows via diode (147) to the 10V supply (150), there is no ripple cancellation and this is of no consequence as the requirement is to generate the timing signal for each half cycle of the AC mains supply input wave signal at the instant the terminal voltage is decreasing towards a zero voltage and therefore the arrangement shown in Figure 5 is operating as required during that time because the AC mains supply and therefore the terminal voltage across the active terminal (130) and load terminal (132) is falling.

[0129] This scaled or attenuated fraction of the terminal voltage across the active terminal (130) and the load terminal (132), approximately 1/30 of its amplitude and with the high frequency ripple injection signals now removed, is processed to generate the required timing signal which importantly becomes producible at a time close to when the voltage across the active terminal (130) and the load terminal (132) crosses zero volts, in turn that is ideally close to when the AC mains supply input wave signal crossed through zero volts.

[0130] Hence unlike the arrangements shown in Figures 1 through to 4 wherein the AC mains supply input wave signal was handled through a low pass filter arrangement to remove the effects of the ripple injection signals, the cancellation arrangement of Figure 5 provides the equivalent voltage derivable from this cleaned AC mains supply input wave signal so that can be placed at the base (165) of the PNP BJT transistor (155) which will then be able to compare with the newly established reference voltage each half cycle of the AC mains supply at the emitter (167) of the PNP BJT transistor (155) such that again, as will be introduced shortly hereafter, this PNP BJT transistor (155) and its operation will be configured like a comparator as such so to compare the respective voltages so that the overcall circuitry then generates the timing signal on (166) to be received by the gate control arrangement (160) which is then responsible for instigating the ON/OFF period of supply of the AC mains supply input wave signal to the load under the control of the two-wire trailing edge circuit arrangement shown in Figure 5.

[0131] In Figure 5 the variable reference voltage derived from the cleaned AC mains supply input wave signal will be used by the comparator which in this instance will be the PNP BJT transistor (155) and is obtained from the resistor (158) and PNP BJT transistor (149) junction. This voltage derived at the junction between resistor (158) and PNP BJT transistor (149) is shifted up by one transistor Vbe approximately 0.6V using PNP BJT transistor (154) connected as an emitter follower. The upshifted voltage is developed at the junction of resistor (162) and the base of NPN BJT transistor (163).

[0132] The emitter follower NPN BJT transistor (163) shifts that voltage down one Vbe approximately 0.6V so that the voltage at the junction of the emitter of NPN BJT transistor (163) and the capacitor (164) will equal the voltage at resistor (158) and the collector (151) of PNP BJT transistor (149), while that voltage is increasing. As the voltage at NPN BJT transistor (163) stops rising and starts to decrease then NPN BJT (163) emitter follower is turned off and therefore cannot cause the voltage on capacitor (164) to increase or to decrease.

[0133] While the capacitor (164) is being charged, where its voltage is following and equal to the voltage on the base (165) of the PNP BJT transistor (155), the PNP BJT transistor (155) emitter-base voltage is zero volts and PNP BJT transistor (155) is therefore turned off. The PNP BJT transistor (155) performs the function of the comparator and will generate the timing signal on signal path (166) to the gate drive control circuit arrangement (160) when the base (165) of the PNP BJT transistor (155) falls in voltage to one Vbe, about 0.6V, below the voltage on the emitter (167) of the PNP BJT transistor (155), that is, to 0.6V below the reference voltage which is the voltage on capacitor (164).

[0134] The arrangement of transistors (154) and (163), along with capacitor (164) performs the function of peak detecting the voltage at the base (165) of the PNP BJT transistor (155). As soon as the base (165) voltage of the PNP BJT transistor (155) has decreased to 0.6V below the peak value, PNP BJT transistor (155) emitter-base will conduct and the PNP BJT transistor (155) collector current will flow through resistor (170).

[0135] The current flowing into the emitter (167) of the PNP BJT transistor (155) is the discharge current of capacitor (164). The magnitude of the current in the emitter (167) of the PNP BJT transistor (155) therefore depends on two factors, those being the voltage on the base of the PNP BJT transistor (155) being 0.6V below the peak value it reaches and the rate of decrease of the base voltage (165) of the PNP BJT transistor (155), that is, capacitor (164) voltage.

[0136] It is important that the emitter follower action of the PNP BJT transistor (155) forces the voltage on capacitor 164 to follow the decrease in voltage of the base (165) of the PNP BJT transistor (155). This means that when the terminal voltage falls to zero volts the base (165) of the PNP BJT transistor (155) is driven by resistor (158) close to zero volts. Capacitor (164) is therefore discharged to about 0.6 V for each half cycle of the AC mains supply input wave signal. This ensures the PNP BJT transistor (155) will be turned off when the terminal voltage starts rising again so the current in resistor (170) will become zero again.

[0137] When the current in resistor (170) causes its voltage to rise to about 0.6 V, the NPN BJT transistor (174) is turned on and its collector current will cause NPN BJT transistor (174) collector voltage to decrease. The fall in the NPN BJT transistor (174) collector voltage from 10V to 0V generates the timing reference pulse to the gate drive control circuit arrangement (160) that then instigates the ON/OFF period of supply of the AC mains supply input wave signal to the load. That falling edge represents the instant when the PNP BJT transistor (155) base (165) is below the voltage on capacitor (164) and is falling at a rate designed to cause the PNP BJT transistor (155) collector current to switch on the NPN BJT transistor (174). The collector of the NPN BJT transistor (174) is connected to the 10V power supply (150) through resistor (176).

[0138] Zener diode (153) is included to ensure that during mains transients, or lamp switch off for inductive lamp loads, the voltage on zener diode (153) cannot exceed the voltage for which the PNP BJT transistor (154) emitter will reach the 10 V supply or the collector-emitter voltage of the PNP BJT transistor (149) will become saturated because it decreases below about 100 mV. That is, Zener diode (153) ensures all the actions as described above must remain valid and the various signal paths do not become overloaded. It will have a value between about half supply and 7.5 V.

[0139] The operation of the circuitry in Figure 5 to remove the ripple injection signals is identical to the operation described for the cancellation of the ripple injection signals in Figure 6 so the same numbers have been used in Figure 6 as in Figure 5 for these components, and the operation and functionality of those components are consistent with what was described for Figure 5.

[0140] Figure 6 provides a further two-wire trailing edge dimmer circuit arrangement which is an extension thereof the circuit shown in Figure 5.

[0141] In summary the two-wire trailing edge dimmer circuit arrangement of Figure 6 compared to Figure 5 further includes functionality wherein the scaled terminal voltage across the active terminal and the load terminal, after processing as described for Figure 5 to cancel the ripple injection signals, is further processed to yield information about the characteristics of the load connected to the two-wire trailing edge dimmer circuit arrangement.

[0142] That information is used to modify the voltage appearing at the input to the comparator, which again in the preferred embodiment shown in Figure 6 is a PNP BJT transistor and also to ensure the timing reference signal derivable from the comparator remains valid and does not contain any false timing edge information even when the input to the existing comparator causes potential generation of invalid signals. [0143] A problem that can cause a failure is that the requirement to switch on NPN BJT transistor (174) requires that capacitor (164) is being discharged at a rate sufficient to cause the current in resistor (170) to generate a voltage that would exceed 0.6 V across resistor (170) to switch on NPN BJT transistor (174).

[0144] When the FETs (138) and (139) are switched on and the voltage across the active terminal (130) and the load terminal (132) is near zero, the voltage at the base of the PNP BJT transistor (155) will be discharged towards zero volts and eventually the rate of decrease must also approach zero. As that condition, for holding the timing signal (166) at the collector of NPN BJT transistor (174) LOW becomes marginal, any small noise on the voltage at the base of the PNP BJT transistor (155) can generate false switching edges in the timing signal which is recognised as a LOW on (166) by the gate drive circuit control arrangement (160). The input to the PNP BJT transistor (155) is essentially a fraction of the dimmer terminal voltage and can contain noise generated by many factors including the load.

[0145] To avoid noise causing a problem, the voltage level at the base of the PNP BJT transistor (155) is fed to an additional comparator, PNP BJT transistor (201), that monitors only the absolute value of the base voltage of the PNP BJT transistor (155) and does not require that level to be continuously falling. The level at the base of the PNP BJT transistor (155) is compared to a fixed reference level generated by the zener diode (202) or an equivalent arrangement.

[0146] The voltage on Zener diode (202) is set at a low value, typically less than 2 V. The comparator for the fixed voltage detection level as introduced above is provided by the PNP BJT transistor (201) which is fed via a large valued resistor (203), for example 1M ohms, that prevents the fixed reference voltage on Zener diode (202) from feeding back via the emitter-base of the comparator PNP BJT transistor (201) and increasing the voltage on the base of the PNP BJT transistor (155).

[0147] Resistor (204) provides the current for the Zener diode (202). The output of the additional comparator, PNP BJT transistor (201), is added to the output of the main comparator that being the PNP BJT transistor (155). The timing signal can be described as being a ‘logic OR’ combination of the two comparator output signals that being the PNP BJT transistor (155) and PNP BJT transistor (201 ). If one of the two signals becomes invalid the combination can remain valid.

[0148] Further ways to guarantee that the new comparator arrangement of the PNP BJT transistor (155) and the PNP BJT transistor (201) continues to function, even if the voltage across the active terminal (130) and the load terminal (132) is not falling as fast as it would if the lamp load, was simply resistive, is to arrange that the input to the comparator base of the PNP BJT transistor (155) is pulled down by using a current sink as provided and switched by the NPN BJT transistor (205) shown in Figure 6.

[0149] The additional current will be activated only when the PNP BJT transistor (155) input voltage has finished rising and be active during the subsequent fall of the PNP BJT transistor (155) input voltage. That fall will be caused by the combination of the falling dimmer terminal voltage and the additional current sink from NPN BJT transistor (205).

[0150] The amplitude of the current sink from NPN BJT transistor (205) will be arranged to vary with the input signal level to the PNP BJT transistor (155), being smallest or zero when that voltage level is large and increasing as that voltage decreases towards zero. To control when the current sink from NPN BJT transistor (205) is active, the current charging the reference voltage capacitor (164) is sensed by inserting resistor (206) in the collector of the emitter follower NPN BJT transistor (163) that supplies the charging current to capacitor (164).

[0151] Resistor (206) is valued to provide a voltage drop greater than 0.6 V while capacitor (164) is being charged by the rising PNP BJT transistor (155) input voltage and the equally rising voltage on capacitor (164). The voltage across resistor (206) is sufficient to ensure that the PNP BJT transistor (207) and PNP BJT transistor (208) are both switched on while capacitor (164) is being charged. Resistors (210) and (211) are included to ensure sharing of the base drive signal across resistor (206) by the PNP BJT transistor (207) and PNP BJT transistor (208). [0152] The collectors of the PNP BJT transistor (207) and PNP BJT transistor (208) are connected to a set/reset latch arrangement using transistors, the PNP BJT transistor (212) and the NPN BJT transistor (213). Resistors (215) and (216) are dimensioned about 5 to 10 times the values of resistor (214) and resistor (217) so that, operating on the 10 V supply (150), a voltage at least 1 V could be developed across resistor (214) if the NPN BJT transistor (213) is on. Likewise, resistor (217) can have at least 1 V if the PNP BJT transistor (212) is on. The emitter-base connections of the PNP BJT transistor (212) and the NPN BJT transistor (213) across resistors resistor (214) and resistor (217) will ensure that they are turned on and the voltage across resistors (214) and (217) will actually only rise to about 0.6 V when a collector current from either the PNP BJT transistor (212) or the NPN BJT transistor (213) is present.

[0153] If the NPN BJT transistor (213) is driven on by collector current from the PNP BJT transistor (212) then the PNP BJT transistor (212) is also driven on by NPN BJT transistor (213) collector current. If the PNP BJT transistor (212) is off there is no drive to NPN BJT transistor (213) so it is off. The arrangement has two stable states and may be ‘set’ to the on state by a brief base drive that turns on either the PNP BJT transistor (212) or the NPN BJT transistor (213) or ‘re-set’ to the off state if the base of either the PNP BJT transistor (212) or the NPN BJT transistor (213) is turned off by reducing its emitter-base voltage below 0.6 V.

[0154] This latch is re-set to the off state each time the FETs (138), (139) are turned off by the respective gates of the FETs (138), (139) being driven towards zero volts. The falling edge of the FETs (138), (139) gate drive is coupled by capacitor (220) and resistor (221) to the base of the NPN BJT transistor (213) briefly forcing its base below zero volts and turning the NPN BJT transistor (213) off. Typical values for capacitor (220) would be about 470pF and for resistor (221) about 470k ohms.

[0155] The FETs (138), (139) gates are driven off every half cycle of the AC mains supply, at the end of the load on period through the gate drive circuit control arrangement (160), and this is the instant that the voltage across the active terminal (130) and the load terminal (132) should start to increase because it is connected via the load to the AC mains supply. It is the time the input to the comparator PNP BJT transistor (155) should start to increase and that the comparator PNP BJT transistor (155) reference voltage capacitor (164) should start charging. It is therefore the time when the PNP BJT transistor (207) and PNP BJT transistor (208) should be driven on by the sensed charging current of capacitor (164).

[0156] The collector current of the PNP BJT transistor (208), feeding the base of the PNP BJT transistor (212) in the latch, acts to pull the base voltage of the PNP BJT transistor (212) towards the 10 V supply (150). That is, it acts to turn off the PNP BJT transistor (212). The PNP BJT transistor (212) has been re-set to off so the PNP BJT transistor (208) collector current causes no change in the state of the latch but it will hold the PNP BJT transistor (212) off during the time that the reference capacitor (164) is being charged even if the NPN BJT transistor (213) is turned on.

[0157] Because the PNP BJT transistor (207) is also turned on by the charging of capacitor (164) its collector current drives via resistor (224) to the base of the NPN BJT transistor (213) and is acting to turn the NPN BJT transistor (213) on as soon as the turn off pulse from capacitor (220) and resistor (221) ends. Resistor (224) is valued similarly to resistor (216) so that when the collector of the PNP BJT transistor (207) is at 10 V, because the PNP BJT transistor (207) is driven on, then the voltage developed across resistor (217) will be sufficient to turn on the NPN BJT transistor (213).When the NPN BJT transistor (213) is turned on its collector current flowing via resistor (215) would turn on the PNP BJT transistor (212) except for the action of the PNP BJT transistor (208) collector current holding the PNP BJT transistor (212) off.

[0158] During the time the latch of the PNP BJT transistor (212) and the NPN BJT transistor (213) is reset to off, or while the PNP BJT transistor (212) is held off by PNP BJT transistor (208), the collector voltage of the PNP BJT transistor (212) will be pulled towards 0.6 V by resistor (216) and towards ground, 0 V, by resistors (230) and (231). The result is that it will be at a voltage less than 0.6 V and therefore too small to turn on the PNP BJT transistor (232) which has the base on ground or at a voltage higher than 0 V if NPN BJT transistor (233) is on and it requires at least 0.6 V on its emitter to turn it on. If there is no collector current in the PNP BJT transistor (232) there is no current in NPN BJT transistor (234) and no current in NPN BJT transistor (205). [0159] When the capacitor (164) on the comparator PNP BJT transistor (155) reference voltage stops being charged then collector current of the NPN BJT transistor (163) ceases and the PNP BJT transistor (207) and PNP BJT transistor (208) turn off.

[0160] The collector voltage of the PNP BJT transistor (207) is held at 10 V by a small valued capacitor (236) so the current in resistor (224), that is turning on the NPN BJT transistor (213) in the latch, remains active for a short time but the collector current of the PNP BJT transistor (208) immediately becomes zero so PNP BJT transistor (212) in the latch can be turned on by the NPN BJT transistor (213) and the latch is set to on. The voltage at the collector of the PNP BJT transistor (212) is held by the PNP BJT transistor (212) at 10 V (150).

[0161] Resistors in the divider made up of resistors (230) and (231) are valued to provide about half the 10 V supply at the emitter of the PNP BJT transistor (232) when the base of the PNP BJT transistor (232) is held above that voltage, above about 5 V, by the emitter follower NPN BJT transistor (233) and therefore no current is flowing in the PNP BJT transistor (232).

[0162] Resistor (238) provides a small loading on the emitter follower the NPN BJT transistor (233) to ensure leakage in the NPN BJT transistor (233) does not affect the voltage on the base of the PNP BJT transistor (232). The NPN BJT transistor (233) sets the base voltage of the PNP BJT transistor (232) to one emitter-base voltage, about 0.6 V, below the voltage on the reference voltage capacitor (164).

The PNP BJT transistor (232) will therefore be turned on whenever the voltage on the reference capacitor (164) falls below the voltage at the junction of divider resistors

(230) and (231).

[0163] The current that will flow in the collector of the PNP BJT transistor (232) is equal to the difference between the voltage at the junction of resistors (230) and

(231) and the voltage on capacitor (164) divided by an effective resistance formed by resistor (230) in parallel with resistor (231). [0164] This current flows to the NPN BJT transistor (234) that is connected in a ‘current mirror’ configuration with the NPN BJT transistor (205). When current flows into the collector of the NPN BJT transistor (234), with the collector of the NPN BJT transistor (234) joined to the base of the NPN BJT transistor (234), it causes a base to ground voltage which is connected to the base of the NPN BJT transistor (205). If the NPN BJT transistor (205) and the NPN BJT transistor (234) have identical characteristics the respective collector currents will be equal when their respective base-emitter voltages are equal. Resistors (241) and (240) are equal and valued to each provide a voltage drop of about 200 mV at the currents flowing in the NPN BJT transistor (205) and the NPN BJT transistor (234). Typical values will be 10k ohms each which ensures a match of collector currents of the NPN BJT transistor (205) and the NPN BJT transistor (234) even if the NPN BJT transistor (205) and the NPN BJT transistor (234) do not have identical characteristics.

[0165] The collector current of the NPN BJT transistor (205) is connected to the comparator PNP BJT transistor (155) input so it sinks current and increases the rate at which this voltage is falling toward zero at the end of each AC mains supply half cycle at the time when the timing signal on (166) into gate drive circuit arrangement (160) must be generated.

[0166] If the terminal voltage across the active terminal (130) and the load terminal (132) has been large and the reference capacitor (164) has been charged to a large voltage then the current flowing in the PNP BJT transistor (232) and pulling down on the comparator the PNP BJT transistor (155) input will be small or zero. As the reference capacitor (164) is discharged the voltage on the base of PBP BJT 232 reduces and its collector current increases, causing a stronger pull-down on the input voltage to the comparator PNP BJT transistor (155).

[0167] Capacitor (243) has been added to the input of the comparator PNP BJT transistor (155) to ensure that this voltage cannot have any sudden large changes caused by the activation of the pull-down current from the NPN BJT transistor (205). The ripple injection signal cancelling arrangement described in Figure 5, and repeated in Figure 6, only requires the ripple injection signal cancelling current flowing from the collector of the PNP BJT transistor (149) to produce a voltage drop across resistor (158) equal to the ripple injection signal voltage across resistor (142) in order that no ripple injection signal appears at the base of the comparator PNP BJT transistor (155).

[0168] The presence of other components such as the NPN BJT transistor (205) does not affect that cancellation of the ripple injection signal process. The pull-down current from the NPN BJT transistor (205) contains negligible ripple injection signal frequency components so also has no effect on the ripple injection signal cancellation process. Capacitor (243) will cause some small additional low-pass filtering of the signal input to the comparator PNP BJT transistor (155) and therefore some delay in the generation of the timing signal at the collector of the NPN BJT transistor (174). However the pull-down current from the NPN BJT transistor (205) speeds the fall of the comparator PNP BJT transistor (155) input voltage and will cause the timing signal to be generated slightly earlier meaning a small delay due to capacitor (243) is acceptable.

[0169] At the end of the FETs (138) and (139) OFF period, and so the start of the FETs (138) and (139) ON period that is initiated by the terminal voltage zero crossing detection, the gates of the FETs (138) and (139) are driven towards +10V. The gate voltage of FETs (138) and (139) is coupled by capacitor (220) and resistor (221) to the base of NPN BJT transistor (213), driving it to the ON state, but the latch formed by NPN BJT transistor (213) and PNP BJT transistor (212) is in the ON state so it has no effect. In the following half cycle of the AC mains supply input wave signal, at the start of the next FET OFF period when the FETs (138) and (139) are driven towards zero volts, the latch is again re-set to the off condition and remains off until the process of capacitor (164) charge current detection is repeated.