2. Description of the Prior Art In power conversion the bridge configuration is the one that can be used in an extremely large number of applications including those that use pulse width modulation to amplify low frequency signals at high efficiency.

The applications can be divided into following major categories: AC to DC, DC to DC, DC to AC, and AC to AC converters.

The most common approach would be to choose a standard high side drive, include a dead zone processing circuit to avoid shoot through and use a series low valued resistor between the supply and the switching device for current sensing. It turns out that for each different application a new design needs to be created with additional waste of engineering time. Also, the prior art solutions above IOQV supply voltage have so rnuch variation in propagational delay that direct paralleling of these solutions is not permitted. In the case of a pulse width modulation input signal at modulation extreme, most solutions utilizing a bootstrap circuit will fall apart due to the finite value which the holdup capacitor may have.

Also, chip solutions have to deal with the quadratic power loss increase as a function of operating voltage at a given frequency. The series current sensing resistor, especially at higher power, becomes very troublesome, not just as a result of the extra heat, but also the increase of ESL of the bypassing circuit.

Due to the high dv/dt and di/dt involved in high speed, high power circuitry, the design of the printed circuit board becomes a major task for accomplishing a sound design.

OBJECTS AND SUMMARY OF THE INVENTION Accordingly, an object of this invention is to provide a topology for a universal power converter free from the defects encountered in the prior art bridge mode power converters. Another object of the invention is to provide a method of constructing a power converter of the widest possible use without fundamental change in the topology or even in the printed circuit board design, i. e. to enable the bridge mode converter to be truly universal use. In accordance with the present invention, a universal power converter is provided having a well defined, very low propagational delay, typically 4 times less the conventional solutions, to enable direct paralleling of converters without the need for the reduction of frequency of operation, having a well defined limit in minimum and maximum duty cycle in the event that the input signal has a duty cycle variation of 0 to 100 %, and also having a lossless current sensing method that tracks switching device on resistance change versus temperature to ensure a safe over current protection level at all allowable temperatures without dissipating extra power or introducing any inductance to the circuit. Yet another advantage of the present invention is that the same printed circuit board can be used for power levels of a few hundred watts to several kilowatts economically by simply reselecting the devices. The universal power converter of the present invention has myriad applications ranging from high fidelity audio to high power miniature welders, battery chargers, etc.

BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a schematic circuit diagram showing a prior art power converter, FIG. 2 is a schematic circuit diagram showing an example of the universal power converter according to the present invention ; and FIGS. 3A to 3H are waveform diagrams used for explaining the operation of the example of the invention shown in FIG. 2.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT E order to better understand the present invention a prior art power converter will be described with reference to FIG. 1 which is a half bridge power converter building Mock. The PWM signal is applied to signal input terminal 1 which is also the input for input buffer 2. The output of input buffer 2 is then connected to upper delay network 3 and lower delay network 4. The outputs of upper and lower delay networks 3 and 4, respectively, are connected to inputs of high/low side drive and shut down circuit S. The upper drive output of high/low side drive and shut down circuit 5 is connected to the control electrode of the upper switching element 6. The lower drive output of high/low side drive and shut down circuit 5 is connected to the control electrode of lower switching element 7. Current sensing resistor 8 is connected between supply terminal ofthe lower switching element 7 and negative DC supply 12 and the junction is then fed to the shut down input of high/low side drive circuit 5. Bootstrap capacitor 9 is connected to high/low side drive and shut down circuit 5 to supply power to the upper switching element 6 when it is turned on. The output terminal of upper switching element 6 is connected to the positive DC supply 10 The output terminal of upper switching element 6 and output terminal of lower switching element 7 are connected together to output terminal 11.

With the prior art power converter shown in FIG. 1, if the PWM signal applied to signal input terrninal I exceeds 100% duty cycle, the upper switching element 6 may lose its supply, which is usually stored in bootstrap capacitor 9, causing severe distortion.

The dead zone protection delay networks 3 and 4 are supplying the signal for the upper and lower drive outputs of highJlow side drive and shut down circuit 5. This results in a propagational delay of turn off ofthe upper and lower switching elements 6 and 7, respectively, as high as 100 nanoseconds with large variation in operating conditions and from device to device. Therefore, paralleling of such power converters is only possible if the dead zones are selected very high which would impair the quality of the low frequency signal to be reproduced.

Current sensing resistor 8 is installed in series with negative DC supply ! 2 introducing power loss and inductance which is an impairment from the bypassing point of view and can easily introduce distortion.

An example of the universal power converter according to the present invention, which is free from the defects above, will be described with reference to FIG. 2.

In the example of the invention shown in FIG. 2, clock input terminal 11 is connected to first upper delay network 13 and first lower delay network 14. PWM input terminal 12 is connected to an input of logic circuit 15. Output of logic circuit 15 is connected to an input of shut down circuit 16. The upper drive output of shut down circuit 16 is connected to second upper delay network 18. The lower drive output of shut down circuit 16 is connected to second lower delay network 19. The output of second upper delay network 18 is connected to switched current source 20 and output of switched current source 20 is connected to input of first buffer 22. The output of first buffer 22 is connected to input of upper capacitive level shifter 23 and output of upper capacitive level shifter 23 is connected to input of second<BR> buffer 26. Output of second buffer 26 is connected to control electrode of upper switching element 29.

Supply terminal of upper switching element 29 ist connected to a power supply terminal 28 which is supplied with a positive DC voltage +VCC and supply terminal of lower switching element 31 is connected to a power supply terminal 32 which is supplied with a negative DC voltage-VCCwhose absolute value is same as that of positive DC voltage +VCC. Output of second lower delay network 19 is connected to input of lower capacitive level shifter 24 and control input of controlled switch 21.

Controlled switch 21 is connected to voltage sense circuit 25. Input of voltage sense circuit 25 is connected to a output terminal 30. Output of voltage sense circuit 25 is connected to input of monostable circuit 17 and output of monostable circuit 17 is connected to an input of shut down circuit 16. Output of lower capacitive level shiter 24 is connected to input of third buffer 27 and output of third buffer 27 is connected to control electrode of lower switching element 31. Output terminal of lower switching element 31 and output terminal of upper switching element 29 are connected together to output terminal 30.

The operation of the above-described circuit will now be explained. Clock input signal Sl, such as that shown in FIG. 3A, supplied to clock input terminal 11 is then input to the first upper delay network 13 which will be initiated at the positive going transition of the clock input signal Sl. The first lower delay network 14 will be initiated at the negative going transition of the clock input signal Sl at clock input terminal 11 and will have such output as that shown in FIG. 3B. Logic circuit 15 will combine the two delayed clock signals such that if PWM signal input SZ, such as that shown in FIG. 3E, which is then input ta fWM input terminal i2, approarhesthe la4% modulation angle or 0 modulation angle and then a maximum and minimum pulse width, respectively, in both directions of the modulation shall be supplied at the output of logic circuit 15 as shown in FIGS. 4C and 4D respectively. Here T is the period of the clock and At is the delay interval.

As logic circuit signal S3 is fed through the shut-down circuit 16, a disable function may be facilitated, if monostable circuit 17 is triggered by voltage sense circuit 25 due to over current condition, by rendering upper switching element 29 and lower switching element 31 inactive by producing zero voltage at the control electrodes of said devices. Shut down circuit 16 via second upper delay network 18 drives a switched current source 20 that is configured such that under no condition shall said switched current source 20 saturate. This configuration then yields a very high speed level translator, that has a typical propagational delay similarto the high speed first buffer 22, approximately 5 nanoseconds. Low voltage logic level signal S4 at the output terminal of first buffer 22 is fed to second buffer 26 via upper capacitive level shifter 23. Second buffer 26 is of high current capacity such that the propagational delay can be maintained again at approximately 5 nanosecond while signal levels are increased typically three fold to drive the control electrode of upper switching element 29 with signal such as that shown in FIG.

3F. As a final result, the delay from the output of first buffer 22 to control electrode of upper switching element 29 will be approximately 15 nanoseconds with a source and sink current of 10 amperes or greater thereby enabling very high speed drive of the high side upper switching element 29 at rail voltages of several hundred volts and output current of over 100 amperes (which is usually associated with very large control electrode to supply terminal capacitance).

The low side lower switching element 31 is driven in a similar fashion to maintain high power and high speed. Low voltage logic level signal S5, such as that shown in FIG. 3G, at the lower drive output of shut down circuit 16 is fed to third buffer 27 via second lower delay network 19 and via lower capacitive level shifter 24. The resultant signal at the control electrode of lower switching element 31 is such as that shown in FIG. 3H.

The operation of the short circuit protection of the above mentioned circuit will now be explained. The voltage drop across lower switching element 31 is directly proportional to the current flowing through it and is being sensed by voltage, sense circuit 25. If current across lower switching<BR> element 34 exceeds def ! ned limit, overload condition, voltage sense circuit 25 will turn on and trigger monostable circuit 17 which, in hun, shall initiate shut down condition via shut down circuit 16. The shut down condition is maintained until rnonostable circuit 17 times out (i. e. several hundred milliseconds).

This process then repeats until the overload condition is removed. Switch 21 is to keep voltage sense circuit 25 in the off state during off states of lower switching element 31. Thus, lossless current sensing is<BR> achieved having the additional feature of moving the current limit to a lower value when the junction temperature increases, further increasing the reliability of the circuit. Also, it is of great advantage that series sensing resistance is not used, the use of which would result in a decrease of the effectiveness of bypassing the upper and lower switching elements 29 and 31 and would decrease the efficiency of the circuit.