Title:
VERTICAL GATE-ALL-AROUND TRANSISTOR STRUCTURE AND PREPARATION METHOD THEREFOR, AND VERTICAL GATE-ALL-AROUND CAPACITOR-LESS MEMORY STRUCTURE AND PREPARATION METHOD THEREFOR
Document Type and Number:
WIPO Patent Application WO/2024/087380
Kind Code:
A1
Abstract:
The present invention relates to a vertical gate-all-around transistor structure and a preparation method therefor, and a vertical gate-all-around capacitor-less memory structure and a preparation method therefor. The capacitor-less memory structure comprises, from bottom to top: a base; an isolation layer; a read bit line layer; first columnar stacking structures, which are arranged on the upper surface of the read bit line layer, and are each formed by stacking a first channel layer, a read word line layer and a first hard mask layer; a first gate dielectric layer, which is arranged, in a surrounding manner, on side surfaces and upper surfaces of the first stacking structures and on the upper surface of the read bit line layer; a first gate layer, which covers a surface of the first gate dielectric layer; second columnar stacking structures, which are arranged on the upper surface of the first gate layer, and are each formed by sequentially stacking a second channel layer, a write bit line layer and a second hard mask layer from bottom to top; a second gate dielectric layer, which is arranged, in a surrounding manner, on side surfaces and upper surfaces of the second stacking structures and on the upper surface of the first gate layer; and a second gate layer. The present invention solves the problem of a low integration density caused by the horizontal arrangement of channels, and enhances the capability of a gate electrode to control a conductive channel.
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Inventors:
XU GAOBO (CN)
SONG ZHIYU (CN)
YAN GANGPING (CN)
YANG SHANGBO (CN)
YIN HUAXIANG (CN)
LUO JUN (CN)
SONG ZHIYU (CN)
YAN GANGPING (CN)
YANG SHANGBO (CN)
YIN HUAXIANG (CN)
LUO JUN (CN)
Application Number:
PCT/CN2022/143242
Publication Date:
May 02, 2024
Filing Date:
December 29, 2022
Export Citation:
Assignee:
BEIJING SUPERSTRING ACADEMY OF MEMORY TECH (CN)
INST OF MICROELECTRONICS CAS (CN)
INST OF MICROELECTRONICS CAS (CN)
International Classes:
H10B12/00
Domestic Patent References:
| WO2011031749A2 | 2011-03-17 |
Foreign References:
| CN114334980A | 2022-04-12 | |||
| CN114446963A | 2022-05-06 | |||
| CN114864583A | 2022-08-05 | |||
| KR20080047097A | 2008-05-28 | |||
| US20120092925A1 | 2012-04-19 |
Attorney, Agent or Firm:
BEIJING CHEN QUAN INTELLECTUAL PROPERTY LAW FIRM (CN)
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