TECHNICAL FIELD

[0001] The present invention generally relates to integrated circuits. More specifically, the present invention relates to vertical tunneling field-effect transistors.

BACKGROUND

[0002] As transistor size in integrated circuits (ICs) decreases, the power supply voltage to the transistors may also need to decrease. As the power supply voltage decreases, the threshold voltage of the transistors in the ICs may also need to decrease. Lower threshold voltages can be difficult to obtain in conventional metal-oxide-semiconductor field-effect transistors (MOSFETs) because, as the threshold voltage is reduced, the ratio of ON-current to OFF-current may also decrease. The ON-current refers to the current through a MOSFET when a gate voltage applied is above the threshold voltage and could be as high as equal to the supply voltage, and the OFF- current refers to current through a MOSFET when a gate voltage applied is below the threshold voltage and can equal zero volts.

BRIEF DESCRIPTION OF THE FIGURES

[0003] Reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and wherein:

[0004] FIG. 1 shows a diagram an example transistor, for example, a TFET having lateral structure, in accordance with one or more example embodiments of the disclosure.

[0005] FIG. 2A shows a diagram of an example vertical TFET transistor, for example, a TFET having a vertical structure (referred to also as vertical TFET herein), in accordance with one or more example embodiments of the disclosure.

[0006] FIG. 2B shows a second diagram of the vertical TFET transistor, in accordance with one or more example embodiments of the disclosure.

[0007] FIG. 3 shows a partial structure of the transistor in the fabrication of a vertical TFET, in accordance with one or more example embodiments of the disclosure.

[0008] FIG. 4 shows a partial structure of the transistor in the fabrication of a vertical TFET, in accordance with one or more example embodiments of the disclosure.

[0009] FIG. 5 shows a partial structure of the transistor in the fabrication of a vertical TFT, in accordance with one or more example embodiments of the disclosure. [0010] FIG. 6 shows a partial structure of the transistor in the fabrication of a vertical TFT, in accordance with one or more example embodiments of the disclosure.

[0011] FIG. 7A shows a first view of a partial structure of the transistor in the fabrication of a vertical TFT, in accordance with one or more example embodiments of the disclosure.

[0012] FIG. 7B shows a second view of a partial structure of the transistor in the fabrication of a vertical TFT, in accordance with one or more example embodiments of the disclosure.

[0013] FIG. 8 shows a partial structure of the transistor in the fabrication of a vertical TFT, in accordance with one or more example embodiments of the disclosure.

[0014] FIG. 9 shows a partial structure of the transistor in the fabrication of a vertical TFT, in accordance with one or more example embodiments of the disclosure.

[0015] FIG. 10 shows a view of a partial structure of the transistor in the fabrication of a vertical TFT, in accordance with one or more example embodiments of the disclosure.

[0016] FIG. 11 shows a diagram of an example flow diagram for the fabrication of a vertical TFET transistor, in accordance with one or more example embodiments of the disclosure.

[0017] FIG. 12 depicts an example of a system according to one or more embodiments of the disclosure.

DETAILED DESCRIPTION

[0018] Embodiments of the disclosure are described more fully hereinafter with reference to the accompanying drawings, in which example embodiments of the disclosure are shown. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like numbers refer to like, but not necessarily the same or identical, elements throughout.

[0019] The following embodiments are described in sufficient detail to enable at least those skilled in the art to understand and use the disclosure. It is to be understood that other embodiments would be evident based on the present disclosure and that process, mechanical, material, dimensional, process equipment, and parametric changes may be made without departing from the scope of the present disclosure.

[0020] In the following description, numerous specific details are given to provide a thorough understanding of various embodiments of the disclosure. However, it will be apparent that the disclosure may be practiced without these specific details. In order to avoid obscuring the present disclosure, some well-known system configurations and process steps may not be disclosed in full detail. Likewise, the drawings showing embodiments of the disclosure are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and may be exaggerated in the drawings. In addition, where multiple embodiments are disclosed and described as having some features in common, for clarity and ease of illustration, description, and comprehension thereof, similar and like features will ordinarily be described with like reference numerals even if the features are not identical.

[0021] The term“horizontal” as used herein may be defined as a direction parallel to a plane or surface (for example, surface of a substrate), regardless of its orientation. The term“vertical,” as used herein, may refer to a direction orthogonal to the horizontal direction as just described. Terms, such as“on,”“above,”“below,”“bottom,”“top,”� �side” (as in“sidewall”),“higher,” “lower,”“upper,”“over,” and“under,” may be referenced with respect to a horizontal plane, where the horizontal plane can include an x-y plane, a x-z plane, or a y-z plane, as the case may be. The terms“on,”“over,”“above,”“higher,”“positio ned on,” or“positioned atop” mean that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements such as an interface structure can be present between the first element and the second element. The term“direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary elements at the interface between the two elements. The term“processing” as used herein includes deposition of material or photoresist, patterning, exposure, development, etching, cleaning, ablating, polishing, and/or removal of the material or photoresist as required in formation of a described structure. The terms “perpendicular,” “orthogonal,” “coplanar,” and/or“parallel” may mean substantially perpendicular, orthogonal, coplanar, or parallel, respectively (e.g., perpendicular within +/- 10 degrees). Further, the figures shown herein may not have precisely vertical or horizontal edges, but rather may have some finite slope and have surface roughness, as is to be expected for fabricated devices.

[0022] “An embodiment,”“various embodiments,” and the like indicate embodiment(s) so described may include particular features, structures, or characteristics, but not every embodiment necessarily includes the particular features, structures, or characteristics. Some embodiments may have some, all, or none of the features described for other embodiments.“First,”“second,”“third,” and the like describe a common object and indicate different instances of like objects are being referred to. Such adjectives do not imply objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.“Connected” may indicate elements are in direct physical or electrical contact with each other and“coupled” may indicate elements co operate or interact with each other, but they may or may not be in direct physical or electrical contact. Also, while similar or same numbers may be used to designate same or similar parts in different figures, doing so does not mean all figures including similar or same numbers constitute a single or same embodiment.

[0023] Tunneling Field Effect Transistors (TFETs) represent a class of transistors that can feature performance increases and energy consumption decreases due to a steeper subthreshold slope (for example, smaller sub-threshold swing) in comparison to MOSFETs. A TFET structure can be similar to a MOSFET structure, except that the source and drain terminals of a TFET can be doped of opposite type; that is, a source can be p-type, while the drain can be n-type (or vice- versa). For example, a TFET device structure can include a p-type, intrinsic, n-type (P-I-N or PIN) junction, in which the electrostatic potential of the intrinsic region can be controlled by a gate terminal.

[0024] In various embodiments, a fin-based TFET can refer to a transistor architecture that implements raised channels (that is, fins), referred to herein also as merely the channel, from source to drain. One characteristic of a fin-based TFET can be that the channel can be wrapped by a fin, which can form the body of the fin-based TFET device. In one embodiment, the thickness of the channel (for example, measured in the direction from source to drain) can determine the effective channel length of the device. In an embodiment, the wrap-around gate structure can provide electrical control over the channel and can reduce the leakage current and other short- channel effects, such as drain-induced barrier lowering (DIBL). Such effects can make it less likely for the voltage on a gate electrode to deplete the channel underneath the gate electrode and thereby stop the flow of carriers through the channel, which can cause the transistor be turned off. By raising the channel above the surface of the wafer instead of creating the channel just below the surface, it can be possible to wrap the gate around all but one of the gate’s sides, providing greater electrostatic control over the carriers within the channel. Further, in one embodiment, nonplanar devices such as fin-based TFETs can be more compact than planar transistors, thereby enabling higher transistor density, which can translate to smaller overall sizes for microelectronic devices.

[0025] In one embodiment, vertical fin-based TFETs (also referred to herein simply as vertical TFETs) can be fabricated in trenches, for example, silicon trenches. In another embodiment, vertical TFETs can be used on different material systems acting as a substrate and/or trenches. For example, the vertical TFETs can be used on silicon (Si), germanium (Ge), III-V semiconductors, gallium nitride (GaN), and the like.

[0026] In an embodiment, the vertical TFETs described herein may not need to use a buffer layer, for example, may not use a III-V material based buffer layer, which can otherwise be a feature of vertical TFETs. In an embodiment, for such vertical TFETs, p-type silicon substrates can be used to function as a p-type source in the vertical TFETs. In another embodiment, such vertical TFETs can have a channel layer that comprises a III-V material, for example, a channel that can include an InAs or InGaAs material, and/or the like. In an embodiment, such vertical TFETs can have a drain that is n-type (also referred to herein as N or N+ type herein). In an embodiment, such an n-type drain can include an N-InAs, an N-InGaAs, or an N-InP material, and/or the like.

[0027] In another embodiment, the vertical TFETs can be fabricated using an aspect ratio trapping (ART) approach. In one embodiment, ART can refer to can generally refer to the technique(s) of causing defects to terminate at non-crystalline sidewalls (for example, dielectric sidewalls), where the sidewalls are sufficiently high relative to the size of a growth area associated with depositing various layers, so as to trap most, if not all, of the defects.

[0028] In one embodiment, the tunneling direction for the carriers in the channel of the vertical TFET can be substantially perpendicular to the surface of the substrate (for example, p-type silicon substrate) on which the TFET is fabricated. In one embodiment, this tunneling direction for vertical TFETs can be different, that is perpendicular or near perpendicular, than the tunneling direction in the channel of lateral TFETs.

[0029] In one embodiment, the vertical TFET can comprise a substrate functioning as source (for example, a p-type silicon substrate functioning as a source), a lattice matched layer on the substrate also functioning as the source (for example, a p-type germanium or a p-type silicon germanium lattice matched layer), a channel (for example, a channel comprising a III-V material, such as an InAs or InGaAs material, and/or the like), and a drain (for example, a drain comprising an n-doped material, such as N-InAs, an N-InGaAs, or an N-InP material, and/or the like). In an embodiment, the junction described above can be gated at a (110) sidewall of the channel.

[0030] In one embodiment, the design and fabrication of a vertical TFET can reduce and/or simplify the fabrication steps needed, for example, as compared with a lateral TFET. For example, in one embodiment, there may not be a need to a dual p-source, n-drain regrowth process in the fabrication of the vertical TFET as compared with the structure and/or fabrication of a lateral TFET.

[0031] In one embodiment, the tunneling junction, that is the junction including the source of a lateral TFET may need to be regrown. In contrast, the channel of a vertical tunneling junction may not need to be regrown in the vertical TFETs, as compared with lateral TFETs. Accordingly, in vertical TFETs, the vertical tunneling junction may not be exposed to ambient atmosphere (for example, air) during fabrication, leading to fewer defects, fewer trap-assisted tunneling, and/or fewer Schottk -Reed-Hall (SRH) leakage. In one embodiment, due at least to features described herein, the fabrication of vertical TFETs can have higher scalability as compared with lateral TFETs.

[0032] FIG. 1 shows a diagram an example transistor, for example, a TFET having lateral structure in accordance with one or more example embodiments of the disclosure. In one embodiment, the transistor 100 can include a substrate 102. In one embodiment, the substrate 102 can refer to a solid (usually planar) substance onto which a layer of another substance is applied, and to which that second substance adheres. In another embodiment, the substrate 102 can include a silicon substrate. In one embodiment, the substrate 102 can include a p-doped silicon substrate. In one embodiment, the substrate 102 can be a thin slice of material such as silicon, silicon oxide, silicon dioxide, aluminum oxide, sapphire, an alloy of silicon and germanium, gallium antimonide (GaSb), and/or indium phosphide (InP), and the like. In one embodiment, the substrate 102 can include a semiconductor material (e.g., monocrystalline silicon, germanium, silicon germanium, SiGe, and/or a III-V materials based material (e.g., gallium arsenide, GaAs), or any combination thereof. In an embodiment, the substrate can include silicon on insulator (SOI), germanium on insulator (GeOI), or a III-V semiconductor on insulator (III-V-OI).

[0033] In one embodiment, the transistor 100 can include a buffer layer 104. In one embodiment, the buffer layer 104 can include any material suitable to insulate adjacent devices and prevent current leakage. The buffer layer 104 can provide field isolation regions that isolate one fin from other fins (not shown), for example, other fins on adjacent devices. In one embodiment, the buffer layer 104 can include an oxide layer (for example, silicon dioxide), or any other electrically insulating layer. In one embodiment, the buffer layer 104 can include an interlayer dielectric (ILD), such as silicon dioxide. In one embodiment, the buffer layer 104 may include polyimide, epoxy, photodefinable materials (for example, benzocyclobutene, BCB),

WPR-series materials, and/or spin-on-glass. In one embodiment, the buffer layer 104 can include a low permittivity (low-k) ILD layer. In one embodiment, low-k can refer to dielectrics having a dielectric constant (permittivity k) lower than the permittivity of silicon dioxide. In one embodiment, the thickness of the buffer layer 104 can be approximately 10 nm to approximately

300 nm, with an example thickness of approximately 30 nm to approximately 50 nm. In one embodiment, the buffer layer 104 can be deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), and/or atomic layer deposition (ALD), and the like.

[0034] In one embodiment, the transistor 100 can include a channel 106. In another embodiment, the channel 106 can include an indium arsenide (InAs) material. In one embodiment, the channel 106 can include an amorphous oxide semiconductor. In another embodiment, the channel 106 can include a zinc oxide (ZnO), an indium gallium zinc oxide (IGZO), an indium tin oxide (ITO) or an antimony oxide material and/or the like. In one embodiment, the channel 106 may include a material that has a wide-band gap with respect to silicon (approximately 1.1 eV).

In one embodiment, the channel 106 can include black phosphorous, amorphous silicon, germanium, carbon nanotube, and the like. In one embodiment, the channel 106 can include silicon, germanium, indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as amorphous silicon (a-Si), amorphous germanium (a-Ge), poly crystalline germanium, poly crystalline silicon, and/or poly crystalline InGaAs, and the like. In one embodiment, the channel thickness can depend on which technology is used to generate the transistor. In another embodiment, the channel 106 can be approximately 3 nm to approximately

50 nm thick, with example thicknesses of approximately 5 nm to approximately 20 nm. In one embodiment, the channel 106 can be deposited using PVD, CVD, and/or ALD, and the like.

[0035] In one embodiment, the transistor 100 can include a source 108. In another embodiment, the source 108 can include a p-doped gallium antimonide (p+ GaSb) layer. In another embodiment, the source 108 can include a nonreactive metal. In one embodiment, the source 108 can include tungsten, titanium nitride, aluminum, titanium, tantalum nitride, cobalt, and/or nickel. In another embodiment, the source 108 can include an p-doped indium gallium arsenide layer. In one embodiment, the source 108 can include silicon. In another embodiment, the silicon material may be p-doped. In another embodiment, the source 108 can be fabricated using MBE. In another embodiment, the source 108 can include doped or undoped black phosphorous, titanium, tantalum, cobalt, molybdenum, titanium nitride, tantalum nitride, hafnium, copper, gadolinium, and the like. In one embodiment, the source 108 can include silicon, germanium, silicon germanium (SiGe), indium phosphide (InP), indium arsenide (InAs), indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as zinc oxide

(ZnO), indium gallium zinc oxide (IGZO), amorphous silicon (a-Si), amorphous germanium (a-

Ge), gallium arsenide antimonide (GaAsSb), polycrystalline germanium, poly crystalline silicon, and/or polycrystalline InGaAs, and the like. In one embodiment, the2 doping can include generating electron vacancies in the source 108. In one embodiment, source can include gettering materials. In one embodiment, the gettering materials can getter sulfur. In one embodiment, the source 108 can be doped, for example, by creating vacancies of sulfur and selenium. In one embodiment, the source 108 can be doped with oxygen vacancies if the source comprises an oxide or a multi-material system. In another embodiment, the source can be doped with phosphorous, boron, aluminum, tin, hafnium, titanium, copper, indium, and/or arsenic if the source 108 comprises a non-oxide a single-material semiconductor. In another embodiment, the source 206 can be approximately 1 nanometer to approximately 100 nm thick, with example thicknesses of approximately 10 nm to approximately 50 nm thick. In one embodiment, the source 108 can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like.

[0036] In one embodiment, the transistor 100 can include a drain 110. In another embodiment, the drain 110 can include an n-doped indium arsenide (n+ InAs) layer. In another embodiment, the drain 110 can include a nonreactive metal. In one embodiment, the drain 110 can include tungsten and/or titanium nitride, aluminum, titanium, tantalum nitride, cobalt, and/or nickel material. In another embodiment, the drain 110 can include an n-doped indium gallium arsenide layer. In one embodiment, the drain 110 can include silicon. In another embodiment, the silicon material may be n-doped. In another embodiment, the drain 110 can include doped or undoped black phosphorous, titanium, tantalum, cobalt, molybdenum, titanium nitride, tantalum nitride, hafnium, copper, gadolinium, and the like. In one embodiment, the drain 110 can include silicon, germanium, silicon germanium (SiGe), indium phosphide (InP), indium arsenide (InAs), indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as zinc oxide (ZnO), indium gallium zinc oxide (IGZO), amorphous silicon (a-Si), amorphous germanium (a- Ge), poly crystalline germanium, poly crystalline silicon, and/or polycrystalline InGaAs, and the like. In one embodiment, the doping can include generating excess electron in the drain 110. In one embodiment, drain 110 can include gettering materials. In another embodiment, the source can be doped with phosphorous, boron, aluminum, tin, hafnium, titanium, copper, indium, and/or arsenic if the drain 110 comprises a non-oxide a single-material semiconductor. In another embodiment, the drain 110 can be approximately 1 nanometer to approximately 100 nm thick, with example thicknesses of approximately 10 nm to approximately 50 nm thick. In one embodiment, the drain 110 can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like.

[0037] In one embodiment, the transistor 100 can include a source contact 112 (also known as a contact electrode). In one embodiment, the source contact 112 can include a metal. In one embodiment, the metal can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. The source contact 112 can include any alloys of such materials. In one embodiment, the source contact 112 can have a thickness of approximately 2 nm to approximately 100 nm, with example thicknesses of approximately 5 nm to approximately 20 nm. In one embodiment, the source contact 112 can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like.

[0038] In one embodiment, the transistor 100 can include a drain contact 114. In one embodiment, the drain contact 114 can include a metal. In one embodiment, the metal can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. The drain contact 114 can include any alloys of such materials. In one embodiment, the drain contract 114 can have a thickness of approximately 2 nm to approximately 100 nm, with example thicknesses of approximately 5 nm to approximately 20 nm. In one embodiment, the drain contract 114 can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like.

[0039] In one embodiment, the transistor 100 can include a gate dielectric 116. In one embodiment, the gate dielectric 116 can include a dielectric material. In another embodiment, the gate dielectric 116 can include silicon oxide. In another embodiment, the gate dielectric 116 can include a high-K dielectric material. In another embodiment, the high-K material, for example, hafnium oxide, tantalum oxide, titanium oxide, aluminum oxide, silicon dioxide, silicon nitride and the like. In one embodiment, an electroglass (EG) can be used as the gate dielectric 116. In one embodiment, the gate dielectric 116 can include hexagonal boron nitride (HBN). In one embodiment, the gate material can be deposited using PVD, CVD, and/or ALD, and the like. In one embodiment, the gate dielectric 116 can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 2 nm to approximately 4 nm.

[0040] In one embodiment, the transistor 100 can include a gate 118. In one embodiment, a gate 118 can be deposited on the gate dielectric 116. In another embodiment, the gate 118 can include a metal. In another embodiment, the gate 118 can include a transition metal. In one embodiment, the gate 118 can be used to tune the threshold voltage of the device. In one embodiment, gate 118 can include titanium nitride, cobalt, tungsten, palladium, molybdenum, germanium, ruthenium, nickel, titanium silicide, and/or platinum. In one embodiment, the gate 118 can be deposited using PVD, CVD, MOCVD, MBE and/or ALD, and the like. In one embodiment, the gate 118 can have a thickness of approximately 30 nmto approximately 100 nm, with an example thickness of approximately 40 nm to approximately 60 nm.

[0041] In one embodiment, the transistor 100 can include spacers 120 and 122. In an embodiment, the spacers 120 and 122 can serve to provide electrical insulation between the gate 118 and the source 108 and/or the drain 110. In one embodiment, the spacers 120 and 122 can include silicon oxide or silicon nitride. The spacer can be serve to prevent the source 108 and/or drain 110 from making electrical contact to the gate 118.

[0042] FIG. 2A shows a vertical TFET transistor 200, in accordance with one or more example embodiments of the disclosure. In one embodiment, the transistor 200 can include a substrate 202.

In another embodiment, the substrate 202 can include a silicon layer. In an embodiment, the substrate 202 can include a p-type substrate, for example, a p-type silicon substrate. In an embodiment, the substrate 202, for example, the p-type silicon substrate, can function as a source, for example, a p-type source in the vertical TFET. In one embodiment, the substrate 202 can refer to a solid (usually planar) substance onto which a layer of another substance is applied, and to which that second substance adheres. In one embodiment, the substrate 202 can include a thin slice of material such as silicon, silicon oxide, silicon dioxide, aluminum oxide, sapphire, an alloy of silicon and germanium, and/or indium phosphide (InP), and the like. In one embodiment, the substrate 202 can include a semiconductor material (e.g., monocry stalline silicon, germanium, silicon germanium, SiGe, and/or a III-V materials based material (e.g., gallium arsenide, GaAs), or any combination thereof). In an embodiment, the substrate 202 can include gallium antimonide (GaSb), silicon on insulator (SOI), germanium on insulator (GOI), or a III-V semiconductor material on silicon (III-V-OI). In one embodiment, the transistors disclosed herein can use the substrate as a source; accordingly, buried oxide can serve as an insolation layer.

[0043] In one embodiment, the transistor 200 can include a channel 208. In one embodiment, the channel 208 includes a first portion and a second portion. In another embodiment, the channel 208 can include a III-V semiconductor material. In an embodiment, such a III-V semiconductor material based channel can include an InAs or an InGaAs based channel material. Further examples of such III-V materials can include those materials that are formed by combining group III elements (for example, including Al, Ga, In) with group V elements (for example, including N, P, As, Sb). For example, some III-V semiconductor materials that can be included in the channel 208 can further include, but not be limited to, GaAs, InP GaP and GaN. In one embodiment, the channel 208 can include an amorphous oxide semiconductor. In another embodiment, the channel 208 can include a zinc oxide (ZnO), an indium gallium zinc oxide (IGZO), an indium tin oxide (ITO) or an antimony oxide material and/or the like. In one embodiment, the channel 208 may include a material that has a wide-band gap with respect to silicon (approximately 1.1 eV). In one embodiment, the channel 208 may include a material that has a smaller band-gap with respect to p-type silicon. In one embodiment, the channel 208 can include black phosphorous, amorphous silicon, germanium, carbon nanotube, and the like. In one embodiment, the channel 208 can include silicon, germanium, indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as amorphous silicon (a-Si), amorphous germanium (a-Ge), polycrystalline germanium, polycrystalline silicon, and/or polycrystalline InGaAs, and the like. In one embodiment, the channel thickness can depend on which technology is used to generate the transistor. In another embodiment, the channel 208 can be approximately 3 nm to approximately 50 nm thick, with example thicknesses of approximately 5 nm to approximately 20 nm. In one embodiment, the channel 208 can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like. [0044] In an embodiment, the transistor can include a drain 212. In one embodiment, the drain 212 is formed on the first portion of the channel 208. In another embodiment, the drain 212 can include an n-doped material. In an embodiment, the drain 212 can include an n-doped indium phosphide (InP) layer. In another embodiment, the drain 212 can include a nonreactive metal. In one embodiment, the drain 212 can include tungsten and/or titanium nitride, aluminum, titanium, tantalum nitride, cobalt, and/or nickel material. In another embodiment, the drain 212 can include an n-doped indium gallium arsenide layer. In one embodiment, the drain 212 can include silicon. In another embodiment, the silicon material may be n-doped. In another embodiment, the drain 212 can include doped or undoped black phosphorous, titanium, tantalum, cobalt, molybdenum, titanium nitride, tantalum nitride, hafnium, copper, gadolinium, and the like. In one embodiment, the drain 212 can include silicon, germanium, silicon germanium (SiGe), indium phosphide (InP), indium arsenide (InAs), indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as zinc oxide (ZnO), indium gallium zinc oxide (IGZO), amorphous silicon (a-Si), amorphous germanium (a-Ge), poly crystalline germanium, poly crystalline silicon, and/or poly crystalline InGaAs, and the like. In one embodiment, the doping can include generating excess electron in the drain 212. In another embodiment, the drain 212 can be doped with phosphorous, boron, aluminum, tin, hafnium, titanium, copper, indium, and/or arsenic if the drain 212 comprises a non-oxide a single-material semiconductor. In another embodiment, the drain 212 can be approximately 1 nanometer to approximately 100 nm thick, with example thicknesses of approximately 10 nm to approximately 50 nm thick. In one embodiment, the drain 212 can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like.

[0045] In an embodiment, the source and drain of a vertical TFET as described herein can have opposite doping (that is, p-type and n-type doping). For example, in one embodiment, for a source including silicon or germanium and a drain including a III-V semiconductor, the doping can be different. In particular, n-dopants for silicon or germanium can include: phosphorous and arsenic; p-dopants for silicon or germanium can include: boron, aluminum, and gallium. Further, n-dopants for III-V semiconductors can include: silicon, carbon, tellurium, and germanium; p- dopants for III-V semiconductors can include: zinc, beryllium, and carbon.

[0046] In one embodiment, the transistor 200 can include a gate dielectric 216. In one embodiment, the gate dielectric 216 is formed on the second portion of the channel 208. In one embodiment, the gate dielectric 216 can include a dielectric material. In another embodiment, the gate dielectric 216 can include silicon oxide. In another embodiment, the gate dielectric 216 can include a high-K dielectric material. In another embodiment, the high-K material, for example, hafnium oxide, tantalum oxide, titanium oxide, aluminum oxide, silicon dioxide, silicon nitride and the like. In one embodiment, an electroglass (EG) can be used as the gate dielectric 216. In one embodiment, the gate dielectric 216 can include hexagonal boron nitride (HBN). In one embodiment, the gate material can be deposited using PVD, CVD, MOCVD, MBE and/or ALD, and the like. In one embodiment, the gate dielectric 216 can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 2 nm to approximately 4 nm.

[0047] In another embodiment, the transistor 200 can include a gate 218. In one embodiment, a gate 218 can be deposited on the gate dielectric 216. In another embodiment, the gate 218 can include a metal. In another embodiment, the gate 218 can include a transition metal. In one embodiment, the gate 218 can be used to tune the threshold voltage of the device. In one embodiment, gate 218 can include titanium nitride, cobalt, tungsten, palladium, molybdenum, germanium, ruthenium, nickel, titanium silicide, and/or platinum. In one embodiment, the gate 218 can be deposited using PVD, CVD, MOCVD, MBE and/or ALD, and the like. In one embodiment, the gate 218 can have a thickness of approximately 30 nmto approximately 100 nm, with an example thickness of approximately 40 nm to approximately 60 nm.

[0048] In one embodiment, the transistor 200 can include a drain contact 214. In one embodiment, the drain contact 214 is formed on the first portion of the channel 208. In one embodiment, the drain contact 214 can include a metal. In one embodiment, the metal can include gold, copper, silver, aluminum, zinc, tin, platinum, titanium, titanium nitride, tantalum nitride, silicide, tungsten, palladium, molybdenum, germanium, ruthenium, nickel any of the like. The drain contact 214 can include any alloys of such materials. In one embodiment, the drain contract 214 can have a thickness of approximately 2 nm to approximately 100 nm, with example thicknesses of approximately 5 nmto approximately 20 nm. In one embodiment, the drain contract 214 can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like.

[0049] In one embodiment, the transistor 200 can include a source contact 210. In one embodiment, the source contact 210 can include a metal. In one embodiment, the metal can include gold, copper, silver, aluminum, zinc, tin, platinum, titanium, titanium nitride, tantalum nitride, silicide, tungsten, palladium, molybdenum, germanium, ruthenium, nickel and any of the like. The source contact 210 can include any alloys of such materials. In one embodiment, the source contact 210 can have a horizontal thickness of approximately 2 nm to approximately 100 nm, with example thicknesses of approximately 5 nm to approximately 20 nm. In one embodiment, the source contact 1030 can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like. [0050] In another embodiment, the transistor 200 can include spacers 220 and 222. In an embodiment, the spacers 220 and 222 can serve to provide electrical insulation between the gate 218, and/or the drain 212. In one embodiment, the spacers 220 and 222 can include silicon oxide or silicon nitride. The spacer can be serve to prevent the drain 212 from making electrical contact to the gate 218.

[0051] In one embodiment, the spacers 220 and 222 can have a triangle shape (not shown). This can be due, for example, to an etching step involved in the fabrication of the spacers 220 and 222. That is, the spacers 220 and 222 may be first deposited as a blanket layer, and then an etch can be used to remove a portion of the insulating spacers 220 and 222 that might remain underneath the drain 212. In one embodiment, the etch can be a directional etch. In another embodiment, the etch may not etch straight downward (in the negative z direction); rather, the etch may have a slight slant and etch more of the top of the spacers 220 and 222 as well, giving rise to the triangular shape of the spacers 220 and 222.

[0052] FIG. 2B shows a diagram of another vertical TFET 201, in accordance with one or more example embodiments of the disclosure. In one embodiment, the transistor 201 can include a substrate 202. In one embodiment, the substrate 202 can refer to a solid (usually planar) substance onto which a layer of another substance is applied, and to which that second substance adheres. In another embodiment, the substrate 202 can include a silicon substrate. In one embodiment, the substrate 202 can include a p-doped silicon substrate. In one embodiment, the substrate 202 can be a thin slice of material such as silicon, silicon oxide, silicon dioxide, aluminum oxide, sapphire, an alloy of silicon and germanium, and/or indium phosphide (InP), and the like. In one embodiment, the substrate 202 can include a semiconductor material (e.g., monocry stalline silicon, germanium, silicon germanium, SiGe, and/or a III-V materials based material (e.g., gallium arsenide, GaAs), or any combination thereof).

[0053] In an embodiment, the transistor 201 can include a lattice matched layer 204, which is lattice matched to the substrate 202. In one embodiment, the lattice matched layer 204 can include a first portion and a second portion. In an embodiment, the lattice matched layer 204 can include a p-type semiconductor material. In an embodiment, the p-type semiconductor material can include a p-type germanium (p-type Ge) material, a p-type silicon-germanium (p-type SiGe) material, gallium arsenide antimonide (GaAsSb), and/or the like. In an embodiment, the lattice matched layer 204, in combination with the substrate 202, can function as a source in the vertical TFET. In one embodiment, the thickness of the lattice matched layer 204 can be approximately 10 nm to approximately 300 mm, with an example thickness of approximately 30 nm to approximately 100 nm. In one embodiment, the lattice matched layer 204 can be deposited using PVD, CVD, MOCVD, ALD, MBE, and the like.

[0054] In one embodiment, the transistor 201 can include a channel 208. In one embodiment, the channel 208 is formed on the first portion of the lattice matched layer 204. In one embodiment, the channel 208 includes a first portion and a second portion. In another embodiment, the channel 208 can include a III-V material. In an embodiment, such a III-V material based channel can include an InAs or an InGaAs material, and/or the like. Further examples of such III-V materials can include those materials that are formed by combining group III elements (for example, including Al, Ga, In) with group V elements (for example, including N, P, As, Sb). For example, some III-V semiconductor materials can further include, but not be limited to, GaAs, InP GaP and GaN. In one embodiment, the channel 208 may include a material that has a wide-band gap with respect to silicon (approximately 1.1 eV). In one embodiment, the channel 208 can include black phosphorous, amorphous silicon, germanium, carbon nanotube, and the like. In one embodiment, the channel 208 can include silicon, germanium, indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as amorphous silicon (a-Si), amorphous germanium (a-Ge), polycrystalline germanium, polycrystalline silicon, and/or polycrystalline InGaAs, and the like. In one embodiment, the channel thickness can depend on which technology is used to generate the transistor. In another embodiment, the channel 208 can be approximately 3 nm to approximately 50 nm thick, with example thicknesses of approximately 5 nm to approximately 20 nm. In one embodiment, the channel 208 can be deposited using PVD, CVD, MBE, MOCVD, ALD, and the like.

[0055] In one embodiment, the transistor 201 can include a source contact 210. In one embodiment, the source contact 210 can include a metal. In one embodiment, the metal can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. The source contact 210 can include any alloys of such materials. In one embodiment, the source contact 210 can have a thickness of approximately 2 nm to approximately 100 nm, with example thicknesses of approximately 5 nm to approximately 20 nm. In one embodiment, the source contact 210 can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like.

[0056] In an embodiment, the transistor 201 can include a drain 212. In one embodiment, the drain 212 is formed on the first portion of the channel 208. In another embodiment, the drain 212 can include an n-doped material. In an embodiment, the drain 212 can include an n-doped indium phosphide layer. In another embodiment, the drain 212 can include a nonreactive metal. In one embodiment, the drain 212 can include tungsten and/or titanium nitride, aluminum, titanium, tantalum nitride, cobalt, and/or nickel material. In another embodiment, the drain 212 can include an n-doped indium gallium arsenide layer. In one embodiment, the drain 212 can include silicon. In another embodiment, the silicon material may be n-doped. In another embodiment, the drain 212 can include doped or undoped black phosphorous, titanium, tantalum, cobalt, molybdenum, titanium nitride, tantalum nitride, hafnium, copper, gadolinium, and the like. In one embodiment, the drain 212 can include silicon, germanium, silicon germanium (SiGe), indium phosphide (InP), indium arsenide (InAs), indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as zinc oxide (ZnO), indium gallium zinc oxide (IGZO), amorphous silicon (a-Si), amorphous germanium (a-Ge), poly crystalline germanium, poly crystalline silicon, and/or poly crystalline InGaAs, and the like. In one embodiment, the doping can include generating excess electron in the drain 212. In another embodiment, the source can be doped with phosphorous, boron, aluminum, tin, hafnium, titanium, copper, indium, and/or arsenic if the drain 212 comprises a non-oxide a single-material semiconductor. In another embodiment, the drain 212 can be approximately 1 nanometer to approximately 100 nm thick, with example thicknesses of approximately 10 nm to approximately 50 nm thick. In one embodiment, the drain 212 can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like.

[0057] In one embodiment, the transistor 201 can include a drain contact 214. In one embodiment, the drain contact 214 can include a metal. In one embodiment, the metal can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. The drain contact 214 can include any alloys of such materials. In one embodiment, the drain contract 214 can have a thickness of approximately 2 nm to approximately 100 nm, with example thicknesses of approximately 5 nm to approximately 20 nm. In one embodiment, the drain contract 214 can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like.

[0058] In another embodiment, the transistor 201 can include a gate dielectric 216. In one embodiment, the gate dielectric 216 is formed on the second portion of the channel 208. In one embodiment, the gate dielectric 216 can include a dielectric material. In another embodiment, the gate dielectric 216 can include silicon oxide. In another embodiment, the gate dielectric 216 can include a high-K dielectric material. In one embodiment, the high-K material, for example, hafnium oxide, tantalum oxide, titanium oxide, aluminum oxide, silicon dioxide, silicon nitride and the like. In one embodiment, an electroglass (EG) can be used as the gate dielectric 216. In one embodiment, the gate dielectric 216 can include hexagonal boron nitride (HBN). In one embodiment, the gate dielectric 216 can be deposited using PVD, CVD, MBE, MOCVD, ALD, and the like. In one embodiment, the gate dielectric 216 can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 2 nm to approximately 4 nm. [0059] In one embodiment, the transistor 201 can include a gate 218. In one embodiment, a gate 218 can be deposited on the gate dielectric 216. In another embodiment, the gate 218 can include a metal. In another embodiment, the gate 218 can include a transition metal. In one embodiment, the gate 218 can be used to tune the threshold voltage of the device. In one embodiment, gate 218 can include titanium nitride, cobalt, tungsten and/or platinum. In one embodiment, the gate 218 can be deposited using PVD, CVD, MOCVD, MBE and/or ALD, and the like. In one embodiment, the gate 218 can have a thickness of approximately 30 nm to approximately 100 nm, with an example thickness of approximately 40 nm to approximately 60 nm.

[0060] In another embodiment, the transistor 200 can include spacers 220 and 222. In an embodiment, the spacers 220 and 222 can serve to provide electrical insulation between the gate 218 and the drain 212 and/or drain contact 214. In one embodiment, the spacers 220 and 222 can include silicon oxide or silicon nitride. In an embodiment, the spacers can be serve to prevent the drain 212 from making electrical contact to the gate 218.

[0061] In one embodiment, the spacers 220 and 222 can have a triangle shape (not shown). This can be due, for example, to an etching step involved in the fabrication of the spacers 220 and 222. That is, the spacers 220 and 222 may be first deposited as a blanket layer, and then an etch can be used to remove a portion of the insulating spacers 220 and 222 that might remain underneath the drain 212. In one embodiment, the etch can be a directional etch. In another embodiment, the etch may not etch straight downward (in the negative z direction); rather, the etch may have a slight slant and etch more of the top of the spacers 220 and 222 as well, giving rise to the triangular shape of the spacers 220 and 222.

[0062] FIG. 3 shows a partial structure of the transistor 300 in the fabrication of a vertical

TFET, in accordance with one or more example embodiments of the disclosure. In one embodiment, the transistor 300 can include a substrate 302. In another embodiment, the substrate

302 can include a silicon layer. In an embodiment, the substrate 302 can include a p-type substrate, for example, a p-type silicon substrate. In an embodiment, the substrate 302, for example, the p- type silicon substrate, can function as a source, for example, a p-type source in the vertical TFET.

In one embodiment, the substrate 302 can refer to a solid (usually planar) substance onto which a layer of another substance is applied, and to which that second substance adheres. In one embodiment, the substrate 302 can be a thin slice of material such as silicon, silicon oxide, silicon dioxide, aluminum oxide, sapphire, an alloy of silicon and germanium, and/or indium phosphide

(InP), and the like. In one embodiment, the substrate 302 can include a semiconductor material

(e.g., monocry stalline silicon, germanium, silicon germanium, SiGe, and/or a III-V materials based material (e.g., gallium arsenide, GaAs), or any combination thereof). In an embodiment, the substrate 302 can include gallium antimonide (GaSb), silicon on insulator (SOI), germanium on insulator (GOI), or a III-V semiconductor material on silicon (III-V-OI). In one embodiment, the transistors disclosed herein can use the substrate as a source; accordingly, buried oxide can serve as an insolation layer.

[0063] In one embodiment, the transistor 300 can include an STI layer (not shown). In one embodiment, the STI layer can include any material suitable to insulate adjacent devices and prevent current leakage. In one embodiment, the STI layer can provide field isolation regions that isolate one fin from other fins (not shown), for example, other fins on adjacent devices. In one embodiment, the STI layer can include an oxide layer (for example, silicon dioxide), or any other electrically insulating layer. In one embodiment, the STI layer can include an interlayer dielectric (ILD), such as silicon dioxide. In one embodiment, the STI layer may include polyimide, epoxy, photodefmable materials (for example, benzocyclobutene, BCB), WPR-series materials, and/or spin-on-glass. In one embodiment, the STI layer can include a low permittivity (low-k) ILD layer. In one embodiment, low-k can refer to dielectrics having a dielectric constant (permittivity k) lower than the permittivity of silicon dioxide. In one embodiment, the thickness of the STI layer can be approximately 10 nm to approximately 300 nm, with an example thickness of approximately 30 nmto approximately 50 nm. In one embodiment, the STI layer can be deposited using PVD, CVD, MOCVD, MBE, ALD, and the like.

[0064] In one embodiment, the transistor 300 can include a channel 308. In another embodiment, the channel 308 can include a III-V material. In an embodiment, such a III-V material based channel can include an InAs or an InGaAs material, and/or the like. Further examples of such III-V materials can include those materials that are formed by combining group

III elements (for example, including Al, Ga, In) with group V elements (for example, including

N, P, As, Sb). For example, some III-V semiconductor materials can further include, but not be limited to, GaAs, InP GaP and GaN. In another embodiment, the channel 308 can include an unintentionally doped (UID) indium arsenide (InAs) layer. In one embodiment, UID can refer to dopants that may be integrated into a layer, for example, during the fabrication of that layer, from the environment and/or processes that the layer is exposed to, often in an uncontrolled manner. In one embodiment, the channel 308 can include an amorphous oxide semiconductor. In another embodiment, the channel 308 can include a zinc oxide (ZnO), an indium gallium zinc oxide

(IGZO), an indium tin oxide (ITO) or an antimony oxide material and/or the like. In one embodiment, the channel 308 may include a material that has a wide-band gap with respect to silicon (approximately 1.1 eV). In one embodiment, the channel 308 can include black phosphorous, amorphous silicon, germanium, carbon nanotube, and the like. In one embodiment, the channel 308 can include silicon, germanium, indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as amorphous silicon (a-Si), amorphous germanium (a-Ge), polycrystalline germanium, polycrystalline silicon, and/or polycrystalline InGaAs, and the like. In one embodiment, the channel thickness can depend on which technology is used to generate the transistor. In another embodiment, the channel 308 can be approximately 3 nm to approximately 50 nm thick, with example thicknesses of approximately 5 nm to approximately 20 nm. In one embodiment, the channel 308 can be deposited using PVD, CVD, and/or ALD, and the like.

[0065] In an embodiment, the transistor can include a drain 312. In another embodiment, the drain 312 can include an n-doped material. In an embodiment, the drain 312 can include an n- doped indium phosphide layer. In another embodiment, the drain 312 can include a nonreactive metal. In one embodiment, the drain 312 can include tungsten and/or titanium nitride, aluminum, titanium, tantalum nitride, cobalt, and/or nickel material. In another embodiment, the drain 312 can include an n-doped indium gallium arsenide layer. In one embodiment, the drain 312 can include silicon. In another embodiment, the silicon material may be n-doped. In another embodiment, the drain 312 can include doped or undoped black phosphorous, titanium, tantalum, cobalt, molybdenum, titanium nitride, tantalum nitride, hafnium, copper, gadolinium, and the like. In one embodiment, the drain 312 can include silicon, germanium, silicon germanium (SiGe), indium phosphide (InP), indium arsenide (InAs), indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as zinc oxide (ZnO), indium gallium zinc oxide (IGZO), amorphous silicon (a-Si), amorphous germanium (a-Ge), polycrystalline germanium, polycrystalline silicon, and/or polycrystalline InGaAs, and the like. In one embodiment, the doping can include generating excess electron in the drain 312 In another embodiment, the source can be doped with phosphorous, boron, aluminum, tin, hafnium, titanium, copper, indium, and/or arsenic if the drain 312 comprises a non-oxide a single-material semiconductor. In another embodiment, the drain 312 can be approximately 1 nm to approximately 100 nm thick, with example thicknesses of approximately 10 nm to approximately 50 nm thick. In one embodiment, the drain 312 can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like.

[0066] FIG. 4 shows a partial structure of a transistor 400 using the fabrication of a vertical TFET, in accordance with one or more example embodiments of the disclosure. In one embodiment, the transistor 400 can include an oxide 420 In one embodiment, the oxide 420 can include an interlayer dielectric (ILD) material. In another embodiment, ILD can include silicon dioxide (SiCh), or a low-K material. In one embodiment, the oxide 420 can be deposited using PVD, CVD, MOCVD, and/or ALD, and the like.

[0067] In one embodiment, the transistor 400 can include a gate dielectric 416. In one embodiment, the gate dielectric 416 can include a dielectric material. In another embodiment, the gate dielectric 416 can include silicon oxide. In another embodiment, the gate dielectric 416 can include a high-K dielectric material. In another embodiment, the high-K material, for example, hafnium oxide, tantalum oxide, titanium oxide, aluminum oxide, silicon dioxide, silicon nitride and the like. In one embodiment, an electroglass (EG) can be used as the gate dielectric 416. In one embodiment, the gate dielectric 416 can include hexagonal boron nitride (HBN). In one embodiment, the gate material can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like. In one embodiment, the gate dielectric 416 can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 2 nm to approximately 4 nm.

[0068] In another embodiment, the transistor 400 can include a gate 418. In one embodiment, a gate 418 can be deposited on the gate dielectric 416. In another embodiment, the gate 418 can include a metal. In another embodiment, the gate 418 can include a transition metal. In one embodiment, the gate 418 can be used to tune the threshold voltage of the device. In one embodiment, gate 418 can include titanium nitride, cobalt, tungsten, palladium, molybdenum, germanium, ruthenium, nickel, titanium silicide, and/or platinum. In one embodiment, the gate 418 can be deposited using PVD, CVD, MOCVD, MBE and/or ALD, and the like. In one embodiment, the gate 418 can have a thickness of approximately 30 nmto approximately 100 nm, with an example thickness of approximately 40 nm to approximately 60 nm.

[0069] In another embodiment, the transistor 400 can include spacers 422. In an embodiment, the spacers 422 can serve to provide electrical insulation between the gate 418 and the drain 312. In one embodiment, the spacers 422 can include silicon oxide or silicon nitride. The spacer can be serve to prevent the drain 312 from making electrical contact to the gate 418.

[0070] In one embodiment, the spacers 422 can have a triangle shape (not shown). This can be due, for example, to an etching step involved in the fabrication of the spacers 422. That is, the spacers 422 may be first deposited as a blanket layer, and then an etch can be used to remove a portion of the insulating spacers 422 that might remain underneath the drain 312. In one embodiment, the etch can be a directional etch. In another embodiment, the etch may not etch straight downward (in the negative z direction); rather, the etch may have a slight slant and etch more of the top of the spacers 422 as well, giving rise to the triangular shape of the spacers 422. [0071] In various embodiments, the transistor 400 can further include the layers described previously in connection with FIG. 3. For example, the transistor 400 can include a substrate 302, a channel 308, and a drain 312. For further description of the various layers, including layer thicknesses, compositions, and/or fabrication techniques, please refer to the relevant description provided in connection with FIG. 3.

[0072] FIG. 5 shows a partial structure of the transistor 500 in the fabrication of a vertical TFET in accordance with one or more example embodiments of the disclosure. In one embodiment, the transistor 500 can include a recess 524 that can be formed by the removal of a portion of the drain 312 (not covered by the oxide 420 shown and described in connection with FIG. 4, above) and a portion of the channel 308. In one embodiment, the removal of the portion of the drain 312 and a portion of the channel 308 can be performed using an etching process. In one embodiment, the etching process can include, for example, a dry etch. In one embodiment, the dry etch can include, for example, a plasma-based and/or a mechanical-based etch. In one embodiment, the etching process can include, for example, a wet etch. The wet etching process can include, for example, any suitable chemicals for the removal of a portion of the drain 312 and a portion of the channel 308.

[0073] In one embodiment, spacer 522 can be thicker than spacer 422 as further shown and described in connection with FIG. 4. The thicker spacer 522 can be achieved by re-depositing a spacer (similar, but not necessarily identical to, spacer 422 as shown and described in connection with FIG. 4) and then performing an etching step on the spacer. In one embodiment, the thicker spacer 522 can serve, for example, to reduce the likelihood of a shorted ground to source connection and/or a shorted ground to drain connection.

[0074] In various embodiments, the transistor 500 can further include the layers similar, but not necessarily identical to, the layers described previously in connection with FIGs. 3 and/or FIG. 4. For example, the transistor 500 can include a substrate 302, a channel 308, and a drain 312, though portions of the channel 308 and/or the drain have been removed, as described above. The transistor 500 can also include a gate 418, gate dielectric 416, and spacers 522. For further description of the various layers, including layer thicknesses, compositions, and/or fabrication techniques, please refer to the relevant description provided in connection with FIG. 3 and/or FIG. 4.

[0075] FIG. 6 shows a partial structure of the transistor 600 in the fabrication of a vertical

TFET in accordance with one or more example embodiments of the disclosure. In one embodiment, the transistor 600 can include a source contact 610. In one embodiment, the source contact 610 can include a metal. In one embodiment, the metal can include gold, copper, silver, aluminum, zinc, tin, platinum, titanium, titanium nitride, tantalum nitride, silicide, tungsten, palladium, molybdenum, germanium, ruthenium, nickel and any of the like. The source contact 610 can include any alloys of such materials. In one embodiment, the source contact 610 can have a thickness of approximately 2 nm to approximately 100 nm, with example thicknesses of approximately 5 nm to approximately 20 nm. In one embodiment, the source contact 610 can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like.

[0076] In one embodiment, the transistor 600 can include a drain contact 614. In one embodiment, the drain contact 614 can include a metal. In one embodiment, the metal can include gold, copper, silver, aluminum, zinc, tin, platinum, titanium, titanium nitride, tantalum nitride, silicide, tungsten, palladium, molybdenum, germanium, ruthenium, nickel and any of the like. The drain contact 614 can include any alloys of such materials. In one embodiment, the drain contract 614 can have a thickness of approximately 2 nm to approximately 100 nm, with example thicknesses of approximately 5 nmto approximately 20 nm. In one embodiment, the drain contract 614 can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like.

[0077] In various embodiments, the transistor 600 can further include the layers similar, but not necessarily identical to, the layers described previously in connection with FIGs. 3-5. For example, the transistor 600 can include a substrate 302, a channel 308, and a drain 312, gate 418, gate dielectric 416, and spacers 522. For further description of the various layers, including layer thicknesses, compositions, and/or fabrication techniques, please refer to the relevant description provided in connection with FIGs. 3-5.

[0078] FIG. 7A shows a first view of a partial structure of a transistor 700 in the fabrication of a vertical TFET, in accordance with one or more example embodiments of the disclosure. In one embodiment, the transistor 700 can include a substrate 702. In another embodiment, the substrate 702 can include a silicon layer. In an embodiment, the substrate 702 can include a p-type substrate, for example, a p-type silicon substrate. In an embodiment, the substrate 702, for example, the p-type silicon substrate, can function as a source, for example, a p-type source in the vertical TFET. In one embodiment, the substrate 702 can refer to a solid (usually planar) substance onto which a layer of another substance is applied, and to which that second substance adheres. In one embodiment, the substrate 702 can be a thin slice of material such as silicon, silicon oxide, silicon dioxide, aluminum oxide, sapphire, an alloy of silicon and germanium, and/or indium phosphide (InP), and the like. In one embodiment, the substrate 702 can include a semiconductor material (e.g., monocrystalline silicon, germanium, silicon germanium, SiGe, and/or a III-V materials based material (e.g., gallium arsenide, GaAs), or any combination thereof). [0079] In an embodiment, the transistor 700 can include a lattice matched layer 704 (also referred to herein as a semiconductor material) to the substrate 702. In an embodiment, the lattice matched layer 704 can include a p-type semiconductor material. In an embodiment, the p-type semiconductor material can include a p-type germanium (p-type Ge) material, a p-type silicon- germanium (p-type SiGe) material, gallium arsenide antimonide (GaAsSb), and/or the like. In an embodiment, the lattice matched layer 704 in combination with the substrate 702, can function as a source in the vertical TFET. In one embodiment, the thickness of the lattice matched layer 704 can be approximately 10 nm to approximately 300 mm, with an example thickness of approximately 30 nm to approximately 150 nm. In one embodiment, the lattice matched layer 704 can be deposited using PVD, CVD, MOCVD, MBE, ALD, and the like.

[0080] In one embodiment, the transistor 700 can include a channel 708. In another embodiment, the channel 708 can include a III-V material. In an embodiment, such a III-V material based channel can include an InAs or an InGaAs material, and/or the like. Further examples of such III-V materials can include those materials that are formed by combining group III elements (for example, including Al, Ga, In) with group V elements (for example, including N, P, As, Sb). For example, some III-V semiconductor materials can further include, but not be limited to, GaAs, InP GaP and GaN. In one embodiment, the channel 708 may include a material that has a wide-band gap with respect to silicon (approximately 1.1 eV). In one embodiment, the channel 708 can include black phosphorous, amorphous silicon, germanium, carbon nanotube, and the like. In one embodiment, the channel thickness can depend on which technology is used to generate the transistor. In another embodiment, the channel 708 can be approximately 3 nm to approximately 50 nm thick, with example thicknesses of approximately 5 nmto approximately 20 nm. In one embodiment, the channel 708 can be deposited using PVD, CVD, MOCVD, MBE and/or ALD, and the like.

[0081] In an embodiment, the transistor 700 can include a drain 712. In another embodiment, the drain 712 can include an n-doped material. In an embodiment, the drain 712 can include an n- doped indium phosphide layer. In another embodiment, the drain 712 can include a nonreactive metal. In one embodiment, the drain 712 can include tungsten and/or titanium nitride, aluminum, titanium, tantalum nitride, cobalt, and/or nickel material. In another embodiment, the drain 712 can include an n-doped indium gallium arsenide layer. In one embodiment, the drain 712 can include silicon. In another embodiment, the silicon material may be n-doped. In another embodiment, the drain 712 can include doped or undoped black phosphorous, titanium, tantalum, cobalt, molybdenum, titanium nitride, tantalum nitride, hafnium, copper, gadolinium, and the like.

In one embodiment, the drain 312 can include silicon, germanium, silicon germanium (SiGe), indium phosphide (InP), indium arsenide (InAs), indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as zinc oxide (ZnO), indium gallium zinc oxide (IGZO), amorphous silicon (a-Si), amorphous germanium (a-Ge), polycrystalline germanium, poly crystalline silicon, and/or polycrystalline InGaAs, and the like. In one embodiment, the doping can include generating excess electron in the drain 712. In another embodiment, the source can be doped with phosphorous, boron, aluminum, tin, hafnium, titanium, copper, indium, and/or arsenic if the drain 712 comprises a non-oxide a single-material semiconductor. In another embodiment, the drain 712 can be approximately 1 nanometer to approximately 100 nm thick, with example thicknesses of approximately 10 nm to approximately 50 nm thick. In one embodiment, the drain 712 can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like.

[0082] FIG. 7B shows a second view of a partial structure of the transistor 701 in the fabrication of a vertical TFET in accordance with one or more example embodiments of the disclosure. In an embodiment, the lattice matched layer 704, the channel 708, and/or the drain 712 can be deposited in trenches formed via patterning of the STI layer, such as trench 705, using one of the patterning and etching techniques known to one of ordinary skill in the art. In one embodiment, the trench 705 can have a depth D of approximately 50 nm to about 300 nm and a width W of approximately 5 nm to about 20 nm. In one embodiment, an aspect ratio of the trench 705 (D/W) can determine the thickness of the various layers deposited through that trench. In another embodiment, the higher the D/W ratio of the trench, the thicker the various layers can be.

[0083] In one embodiment, the transistor 701 can include an STI layer 703 (also referred to herein as an isolation structure). In one embodiment, the STI layer 703 can include any material suitable to insulate adjacent devices and prevent current leakage. In one embodiment, the STI layer 703 can provide field isolation regions that isolate one fin from other fins (not shown), for example, other fins on adjacent devices. In one embodiment, the STI layer 703 can include an oxide layer (for example, silicon dioxide), or any other electrically insulating layer. In one embodiment, the STI layer 703 can include an interlayer dielectric (ILD), such as silicon dioxide. In one embodiment, the STI layer 703 may include polyimide, epoxy, photodefmable materials (for example, benzocyclobutene, BCB), WPR-series materials, and/or spin-on-glass. In one embodiment, the STI layer 703 can include a low permittivity (low-k) ILD layer. In one embodiment, low-k can refer to dielectrics having a dielectric constant (permittivity k) lower than the permittivity of silicon dioxide. In one embodiment, the thickness of the STI layer 703 can be approximately 10 nm to approximately 300 nm, with an example thickness of approximately 30 nm to approximately 50 nm. In one embodiment, the STI layer 703 can be deposited using can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like.

[0084] In various embodiments, the transistor 701 can further include the layers described previously in connection with FIG. 7A. For example, the transistor 701 can include a substrate 702, a buffer layer 704, a channel 308, and a drain 712. For further description of the various layers, including layer thicknesses, compositions, and/or fabrication techniques, please refer to the relevant description provided in connection with FIG. 7A.

[0085] FIG. 8 shows a partial structure of a transistor 800 using the fabrication of a vertical TFET in accordance with one or more example embodiments of the disclosure. In one embodiment, the transistor 800 can include an oxide 820. In one embodiment, the oxide 820 can include an interlayer dielectric (ILD) material. In another embodiment, ILD can include silicon dioxide (SiCh), or a low-K material. In one embodiment, the oxide 820 can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like.

[0086] In one embodiment, the transistor 800 can include a gate dielectric 816. In one embodiment, the gate dielectric 816 can include a dielectric material. In another embodiment, the gate dielectric 816 can include silicon oxide. In another embodiment, the gate dielectric 816 can include a high-K dielectric material. In another embodiment, the high-K material, for example, hafnium oxide, tantalum oxide, titanium oxide, aluminum oxide, silicon dioxide, silicon nitride and the like. In one embodiment, an electroglass (EG) can be used as the gate dielectric 816. In one embodiment, the gate dielectric 816 can include hexagonal boron nitride (HBN). In one embodiment, the gate material can be deposited using PVD, CVD, and/or ALD, and the like. In one embodiment, the gate dielectric 816 can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 2 nm to approximately 4 nm.

[0087] In another embodiment, the transistor 800 can include a gate 818. In one embodiment, a gate 818 can be deposited on the gate dielectric 816. In another embodiment, the gate 818 can include a metal. In another embodiment, the gate 818 can include a transition metal. In one embodiment, the gate 818 can be used to tune the threshold voltage of the device. In one embodiment, gate 818 can include titanium nitride, cobalt, tungsten and/or platinum. In one embodiment, the gate 818 can be deposited using PVD, CVD, MOCVD, MBE and/or ALD, and the like. In one embodiment, the gate 818 can have a thickness of approximately 30 nm to approximately 100 nm, with an example thickness of approximately 40 nm to approximately 60 nm.

[0088] In another embodiment, the transistor 800 can include spacers 822. In an embodiment, the spacers 822 can serve to provide electrical insulation between the gate 818, and/or the drain 712. In one embodiment, the spacers 822 can include silicon oxide or silicon nitride. The spacer can be serve to prevent the drain 712 from making electrical contact to the gate 718.

[0089] In one embodiment, the spacers 822 can have a triangle shape (not shown). This can be due, for example, to an etching step involved in the fabrication of the spacers 822. That is, the spacers 822 may be first deposited as a blanket layer, and then an etch can be used to remove a portion of the insulating spacers 822 that might remain underneath the drain 812. In one embodiment, the etch can be a directional etch. In another embodiment, the etch may not etch straight downward (in the negative z direction); rather, the etch may have a slight slant and etch more of the top of the spacers 822 as well, giving rise to the triangular shape of the spacers 822.

[0090] In various embodiments, the transistor 800 can further include the layers described previously in connection with FIG. 7. For example, the transistor 800 can include a substrate 702, a lattice matched layer 704, a channel 708, and a drain 712. For further description of the various layers, including layer thicknesses, compositions, and/or fabrication techniques, please refer to the relevant description provided in connection with FIG. 7.

[0091] FIG. 9 shows a partial structure of the transistor 900 in the fabrication of a vertical

TFET, in accordance with one or more example embodiments of the disclosure. In one embodiment, the transistor 900 can include a recess 924 can be formed by the removal of a portion of the drain 712 (not covered by the oxide 720 shown and described in connection with FIG. 8, above) and a portion of the channel 708. In one embodiment, the removal of the portion of the drain 712 and a portion of the channel 708 can be performed using an etching process. In one embodiment, the etching process can include, for example, a dry etch. In one embodiment, the dry etch can include, for example, a plasma-based and/or a mechanical-based etch. In one embodiment, the etching process can include, for example, a wet etch. The wet etching process can include, for example, any suitable chemicals for the removal of a portion of the drain 712 and a portion of the channel 708. In one embodiment, spacer 922 can be thicker than spacer 822 as further shown and described in connection with FIG. 8. The thicker spacer 922 can be achieved by re-depositing a spacer (similar, but not necessarily identical to, spacer 822 as shown and described in connection with FIG. 8) and then performing an etching step on the spacer. In one embodiment, the thicker spacer 922 can serve, for example, to reduce the likelihood of a shorted ground to source connection and/or a shorted ground to drain connection.

[0092] In various embodiments, the transistor 900 can further include the layers similar, but not necessarily identical to, the layers described previously in connection with FIGs. 7 and/or 8.

For example, the transistor 900 can include a substrate 702, a lattice-matched layer 704 (i.e., lattice-matched to channel 708), a channel 708, and a drain 712, though portions of the channel 708 and/or the drain have been removed, as described above. The transistor 900 can also include a gate 818, and gate dielectric 816. For further description of the various layers, including layer thicknesses, compositions, and/or fabrication techniques, please refer to the relevant description provided in connection with FIG. 7 and/or 8.

[0093] FIG. 10 shows a partial structure of the transistor 1000 in the fabrication of a vertical TFET in accordance with one or more example embodiments of the disclosure. In one embodiment, the transistor 1000 can include a source contact 1030. In one embodiment, the source contact 1030 can include a metal. In one embodiment, the metal can include gold, copper, silver, aluminum, zinc, tin, platinum, titanium, titanium nitride, tantalum nitride, silicide, and tungsten, palladium, molybdenum, germanium, ruthenium, nickel and any of the like. The source contact 1030 can include any alloys of such materials. In one embodiment, the source contact 1030 can have a thickness of approximately 2 nm to approximately 100 nm, with example thicknesses of approximately 5 nm to approximately 20 nm. In one embodiment, the source contact 1030 can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like.

[0094] In one embodiment, the transistor 1000 can include a drain contact 1032. In one embodiment, the drain contact 1032 can include a metal. In one embodiment, the metal can include gold, copper, silver, aluminum, zinc, tin, platinum, titanium, titanium nitride, tantalum nitride, silicide, and tungsten, palladium, molybdenum, germanium, ruthenium, nickel and any of the like. The drain contact 1032 can include any alloys of such materials. In one embodiment, the drain contract 1032 can have a thickness of approximately 2 nmto approximately 100 nm, with example thicknesses of approximately 5 nmto approximately 20 nm. In one embodiment, the drain contract 1032 can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like.

[0095] In various embodiments, the transistor 1000 can further include the layers similar, but not necessarily identical to, the layers described previously in connection with FIGs. 7-9. For example, the transistor 1032 can include a substrate 702, a channel 708, and a drain 712, gate 818, gate dielectric 816, and spacers 922. For further description of the various layers, including layer thicknesses, compositions, and/or fabrication techniques, please refer to the relevant description provided in connection with FIG. 7-9.

[0096] FIG. 11 shows a diagram of an example flow diagram for the fabrication of a vertical

TFET, in accordance with example embodiments of the disclosure. In block 1105, a substrate can be provided. In one embodiment, the substrate can refer to a solid (usually planar) substance onto which a layer of another substance is applied, and to which that second substance adheres. In another embodiment, the substrate can include a silicon substrate. In one embodiment, the substrate can include a p-doped silicon substrate. In an embodiment, the substrate, for example, the p-type silicon substrate, can function as a source, for example, a p-type source in the vertical TFET. In one embodiment, the substrate can be a thin slice of material such as silicon, silicon oxide, silicon dioxide, aluminum oxide, sapphire, an alloy of silicon and germanium, and/or indium phosphide (InP), and the like. In one embodiment, the substrate can include a semiconductor material (e.g., monocry stalline silicon, germanium, silicon germanium, SiGe, and/or a III-V materials based material (e.g., gallium arsenide, GaAs), or any combination thereof). In an embodiment, the substrate can include gallium antimonide (GaSb), silicon on insulator (SOI), germanium on insulator (GOI), or a III-V semiconductor material on silicon (III- V-OI). In one embodiment, the transistors disclosed herein can use the substrate as a source; accordingly, buried oxide can serve as an insolation layer.

[0097] In an embodiment, a shallow trench isolation layer can be deposited on the substrate. In one embodiment, the STI layer can include any material suitable to insulate adjacent devices and prevent current leakage. In one embodiment, the STI layer can provide field isolation regions that isolate one fin from other fins (not shown), for example, other fins on adjacent devices. In one embodiment, the STI layer can include an oxide layer (for example, silicon dioxide), or any other electrically insulating layer. In one embodiment, the STI layer can include an interlayer dielectric (ILD), such as silicon dioxide. In one embodiment, the STI layer may include polyimide, epoxy, photodefinable materials (for example, benzocyclobutene, BCB), WPR-series materials, and/or spin-on-glass. In one embodiment, the STI layer can include a low permittivity (low-k) ILD layer. In one embodiment, low-k can refer to dielectrics having a dielectric constant (permittivity k) lower than the permittivity of silicon dioxide. In one embodiment, the thickness of the STI layer can be approximately 10 nm to approximately 300 nm, with an example thickness of approximately 30 nm to approximately 50 nm. In one embodiment, the buffer layer can be deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), and/or atomic layer deposition (ALD), and the like.

[0098] In an embodiment, the STI layer can be patterned and etched to generate a trench. In an embodiment, the STI layer can be patterned and etched using one of the patterning and etching techniques known to one of ordinary skill in the art. In an embodiment, the etching can include, for example, a dry etch. In one embodiment, the dry etch can include, for example, a plasma-based and/or a mechanical-based etch. In one embodiment, the etching process can include, for example, a wet etch. The wet etching process can include, for example, any suitable chemicals for the removal of a portion of the STI layer. In another embodiment, the patterning of the STI layer can utilize one or more masks, such as one or more photomasks. In one embodiment, the trench can have a depth D of approximately 50 nm to about 300 nm and a width W of approximately 5 nm to about 20 nm. In one embodiment, an aspect ratio of the trench (D/W) can determine the thickness of the various layers deposited through that trench. In another embodiment, the higher the D/W ratio of the trench, the thicker the various layers can be.

[0099] In block 1110, a semiconductor can be optionally deposited on the substrate. In an embodiment, the semiconductor can include a lattice-matched layer. In another embodiment, the lattice-matched layer can serve as a source. In an embodiment, the lattice-matched layer not necessarily need to be lattice-matched to the substrate, but may need to be matched to the channel. In an embodiment, a defect free lattice-matched layer (e.g., serving as a source) and channel junction in TFETs can be used to reduce defect-assisted tunneling, an effect that may degrade the subthreshold slope of the transistor. In an embodiment, the lattice matched layer can be deposited in the trench generated in the STI layer. In an embodiment, the lattice matched layer can include a p-type semiconductor material. In an embodiment, the p-type semiconductor material can include a p-type germanium (p-type Ge) material, a p-type silicon-germanium (p-type SiGe) material, gallium arsenide antimonide (GaAsSb), and/or the like. In an embodiment, the lattice matched layer in combination with the substrate, can function as a source in the vertical TFET. In one embodiment, the thickness of the lattice matched layer can be approximately 10 nm to approximately 100 mm, with an example thickness of approximately 30 nm to approximately 150 nm. In one embodiment, the lattice matched layer can be deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), and/or atomic layer deposition (ALD), and the like.

[0100] In block 1115, a channel can be deposited on the substrate. In an embodiment, the channel can be deposited in the trench generated in the STI layer. In another embodiment, the channel can include a III-V material. In an embodiment, such a III-V material based channel can include an InAs or an InGaAs material, and/or the like. Further examples of such III-V materials can include those materials that are formed by combining group III elements (for example, including Al, Ga, In) with group V elements (for example, including N, P, As, Sb). For example, some III-V semiconductor materials can further include, but not be limited to, GaAs, InP GaP and GaN. In one embodiment, the channel may include a material that has a wide-band gap with respect to silicon (approximately 1.1 eV). In one embodiment, the channel can include black phosphorous, amorphous silicon, germanium, carbon nanotube, and the like. In one embodiment, the channel thickness can depend on which technology is used to generate the transistor. In another embodiment, the channel can be approximately 3 nmto approximately 50 nm thick, with example thicknesses of approximately 5 nm to approximately 20 nm. In one embodiment, the channel can be deposited using PVD, CVD, and/or ALD, and the like.

[0101] In block 1120, a drain can be deposited on the channel. In another embodiment, the drain can include an n-doped material. In an embodiment, the drain can include an n-doped indium phosphide layer. In another embodiment, the drain can include a nonreactive metal. In one embodiment, the drain can include tungsten and/or titanium nitride, aluminum, titanium, tantalum nitride, cobalt, and/or nickel material. In another embodiment, the drain can include an n-doped indium gallium arsenide layer. In one embodiment, the drain can include silicon. In another embodiment, the silicon material may be n-doped. In another embodiment, the drain can include doped or undoped black phosphorous, titanium, tantalum, cobalt, molybdenum, titanium nitride, tantalum nitride, hafnium, copper, gadolinium, and the like. In one embodiment, the drain can include silicon, germanium, silicon germanium (SiGe), indium phosphide (InP), indium arsenide (InAs), indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as zinc oxide (ZnO), indium gallium zinc oxide (IGZO), amorphous silicon (a-Si), amorphous germanium (a-Ge), polycrystalline germanium, polycrystalline silicon, and/or polycrystalline InGaAs, and the like. In one embodiment, the doping can include generating excess electron in the drain. In another embodiment, the source can be doped with phosphorous, boron, aluminum, tin, hafnium, titanium, copper, indium, and/or arsenic if the drain comprises anon-oxide a single material semiconductor. In another embodiment, the drain can be approximately 1 nanometer to approximately 100 nm thick, with example thicknesses of approximately 10 nm to approximately 50 nm thick. In one embodiment, the drain can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like.

[0102] In an embodiment, the lattice-matched layer (serving as the source) and drain of a vertical TFET as described herein can have opposite doping (that is, p-type and n-type doping). For example, in one embodiment, for a source including silicon or germanium and a drain including a III-V semiconductor, the doping can be different. In particular, n-dopants for silicon or germanium can include: phosphorous and arsenic; p-dopants for silicon or germanium can include: boron, aluminum, and gallium. Further, n-dopants for III-V semiconductors can include: silicon, carbon, tellurium, and germanium; p-dopants for III-V semiconductors can include: zinc, beryllium, and carbon.

[0103] In block 1125, a gate dielectric can be deposited on the drain. In one embodiment, the gate dielectric can include a dielectric material. In another embodiment, the gate dielectric can include silicon oxide. In another embodiment, the gate dielectric can include a high-K dielectric material. In another embodiment, the high-K material, for example, hafnium oxide, tantalum oxide, titanium oxide, aluminum oxide, silicon dioxide, silicon nitride and the like. In one embodiment, an electroglass (EG) can be used as the gate dielectric. In one embodiment, the gate dielectric can include hexagonal boron nitride (HBN). In one embodiment, the gate material can be deposited using PVD, CVD, and/or ALD, and the like. In one embodiment, the gate dielectric can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 2 nm to approximately 4 nm.

[0104] In block 1130, a gate can be deposited on the gate dielectric. In another embodiment, the gate can include a metal. In another embodiment, the gate can include a transition metal. In one embodiment, the gate can be used to tune the threshold voltage of the device. In one embodiment, gate can include titanium nitride, cobalt, tungsten and/or platinum. In one embodiment, the gate can have a thickness of approximately 30 nm to approximately 100 nm, with an example thickness of approximately 40 nm to approximately 60 nm. In one embodiment, the gate can be deposited using PVD, CVD, MOCVD, MBE and/or ALD, and the like.

[0105] In block 1135, spacers can be deposited on sidewalls of the gate dielectric. In an embodiment, the spacers can serve to provide electrical insulation between the gate and/or the drain. In one embodiment, the spacers and can include silicon oxide or silicon nitride. The spacer can be serve to prevent the drain from making electrical contact to the gate.

[0106] In one embodiment, the spacers can have a triangle shape. This can be due, for example, to an etching step involved in the fabrication of the spacers. That is, the spacers may be first deposited as a blanket layer, and then an etch can be used to remove a portion of the insulating spacers that might remain underneath the drain. In one embodiment, the etch can be a directional etch. In another embodiment, the etch may not etch straight downward; rather, the etch may have a slight slant and etch more of the top of the spacers as well, giving rise to the triangular shape of the spacers.

[0107] In an embodiment, an oxide can be deposited on a portion of the drain, a portion the gate, a portion of the gate dielectric. In one embodiment, the oxide can include an interlayer dielectric (ILD) material. In another embodiment, ILD can include silicon dioxide (SiCh), or a low-K material. In one embodiment, the oxide can be deposited using PVD, CVD, MOCVD, and/or ALD, and the like.

[0108] In block 1140, a portion of the drain and a portion of the channel can be removed. In an embodiment, the portion of the drain and the portion of the channel that are removed can include those portions that are not covered by the oxide. In one embodiment, the removal of the portion of the drain and a portion of the channel can be performed using an etching process. In one embodiment, the etching process can include, for example, a dry etch. In one embodiment, the dry etch can include, for example, a plasma-based and/or a mechanical-based etch. In one embodiment, the etching process can include, for example, a wet etch. The wet etching process can include, for example, any suitable chemicals for the removal of a portion of the drain and a portion of the channel.

[0109] In block 1145, second spacers can be deposited on the sidewalls existing spacer layers to thicken the spacers. In one embodiment, the thicker spacer can serve, for example, to reduce the likelihood of a shorted ground to source connection and/or a shorted ground to drain connection.

[0110] In block 1150, a source contact can be deposited. In an embodiment, the source contact can be deposited on the substrate. In an embodiment, the source contact can be deposited on the semiconductor serving as a lattice matching layer. In one embodiment, the source contact can include a metal. In one embodiment, the metal can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. The source contact can include any alloys of such materials. In one embodiment, the source contact can have a thickness of approximately 2 nm to approximately 100 nm, with example thicknesses of approximately 5 nm to approximately 20 nm. In one embodiment, the source contact can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like.

[0111] In block 1155, a drain contact can be deposited. In an embodiment, the drain contact can be deposited on the drain. In one embodiment, the drain contact can include a metal. In one embodiment, the metal can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. The drain contact can include any alloys of such materials. In one embodiment, the drain contract can have a thickness of approximately 2 nm to approximately 100 nm, with example thicknesses of approximately 5 nmto approximately 20 nm. In one embodiment, the drain contract can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like.

[0112] FIG. 12 depicts an example of a system 1200 according to one or more embodiments of the disclosure. In one embodiment, the transistors described herein can be used in connection with or formed as a part of any of the devices shown in system 1200. In one embodiment, system 1200 includes, but is not limited to, a desktop computer, a laptop computer, a netbook, a tablet, a notebook computer, a personal digital assistant (PDA), a server, a workstation, a cellular telephone, a mobile computing device, a smart phone, an Internet appliance or any other type of computing device. In some embodiments, system 1200 can include a system on a chip (SOC) system.

[0113] In one embodiment, system 1200 includes multiple processors including processor

1210 (in FIG. 12, processor 1210 is labeled as 1210) and processor N 1205, where processor N 1205 has logic similar or identical to the logic of processor 1210. In one embodiment, processor 1210 has one or more processing cores (represented here by processing core 1 1212 and processing core N 1212N, where 1212N represents the Nth processor core inside processor 1210, where N is a positive integer). More processing cores can be present (but not depicted in the diagram of FIG. 12). In some embodiments, processing core 1212 includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions, a combination thereof, or the like. In some embodiments, processor 1210 has a cache memory 1216 to cache instructions and/or data for system 1200. Cache memory 1216 may be organized into a hierarchical structure including one or more levels of cache memory.

[0114] In some embodiments, processor 1210 includes a memory controller (MC) 1214, which is configured to perform functions that enable the processor 1210 to access and communicate with memory 1230 that includes a volatile memory 1232 and/or a non-volatile memory 1234. In some embodiments, processor 1210 can be coupled with memory 1230 and chipset 1220. Processor 1210 may also be coupled to a wireless antenna 1278 to communicate with any device configured to transmit and/or receive wireless signals. In one embodiment, the wireless antenna 1278 operates in accordance with, but is not limited to, the IEEE 1102.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

[0115] In some embodiments, volatile memory 1232 includes, but is not limited to, Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM), and/or any other type of random access memory device. Non-volatile memory 1234 includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.

[0116] Memory device 1230 stores information and instructions to be executed by processor 1210. In one embodiment, memory 1230 may also store temporary variables or other intermediate information while processor 1210 is executing instructions. In the illustrated embodiment, chipset 1220 connects with processor 1210 via Point-to-Point (PtP or P-P) interface 1217 and P-P interface 1222. Chipset 1220 enables processor 1210 to connect to other elements in system 1200. In some embodiments of the disclosure, P-P interface 1217 and P-P interface 1222 can operate in accordance with a PtP communication protocol, such as the Intel® QuickPath Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used.

[0117] In some embodiments, chipset 1220 can be configured to communicate with processor

1210, the processor N 1205, display device 1240, and other devices 1272, 1276, 1274, 1260, 1262, 1264, 1266, 1277, etc. Chipset 1220 may also be coupled to the wireless antenna 1278 to communicate with any device configured to transmit and/or receive wireless signals.

[0118] Chipset 1220 connects to display device 1240 via interface 1226. Display 1240 may be, for example, a liquid crystal display (LCD), a plasma display, cathode ray tube (CRT) display, or any other form of visual display device. In some embodiments of the disclosure, processor 1210 and chipset 1220 are integrated into a single SOC. In addition, chipset 1220 connects to bus 1250 and/or bus 1255 that interconnect various elements 1274, 1260, 1262, 1264, and 1266. Bus 1250 and bus 1255 may be interconnected via a bus bridge 1272. In one embodiment, chipset 1220 couples with anon-volatile memory 1260, amass storage device(s) 1262, a keyboard/mouse 1264, and a network interface 1266 via interface 1224 and/or 1226, smart TV 1276, consumer electronics 1277, etc.

[0119] In one embodiment, mass storage device(s) 1262 can include, but not be limited to, a solid state drive, a hard disk drive, a universal serial bus flash memory drive, or any other form of computer data storage medium. In one embodiment, network interface 1266 is implemented by any type of well-known network interface standard including, but not limited to, an Ethernet interface, a universal serial bus (USB) interface, a Peripheral Component Interconnect (PCI) Express interface, a wireless interface and/or any other suitable type of interface. In one embodiment, the wireless interface operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

[0120] While the modules shown in FIG. 12 are depicted as separate blocks within the system

1200, the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits. For example, although cache memory 1216 is depicted as a separate block within processor 1210, cache memory 1216 or selected elements thereof can be incorporated into processor core 1212.

[0121] It is noted that the system 1200 described herein may include any suitable type of microelectronics packaging and configurations thereof, including, for example, system in a package (SiP), system on a package (SOP), package on package (PoP), interposer package, 3D stacked package, etc. Further, any suitable type of microelectronic components may be provided in the semiconductor packages, as described herein. For example, microcontrollers, microprocessors, baseband processors, digital signal processors, memory dies, field gate arrays, logic gate dies, passive component dies, MEMSs, surface mount devices, application specific integrated circuits, baseband processors, amplifiers, filters, combinations thereof, or the like may be packaged in the semiconductor packages, as disclosed herein. The semiconductor packages (for example, the semiconductor packages described in connection with any of FIGS. 1-11), as disclosed herein, may be provided in any variety of electronic devices including consumer, industrial, military, communications, infrastructural, and/or other electronic devices.

[0122] In various embodiments, the devices, as described herein, may be used in connection with one or more processors. The one or more processors may include, without limitation, a central processing unit (CPU), a digital signal processor(s) (DSP), a reduced instruction set computer (RISC), a complex instruction set computer (CISC), a microprocessor, a microcontroller, a field programmable gate array (FPGA), or any combination thereof. The processors may also include one or more application specific integrated circuits (ASICs) or application specific standard products (ASSPs) for handling specific data processing functions or tasks. In certain embodiments, the processors may be based on an Intel® Architecture system and the one or more processors and any chipset included in an electronic device may be from a family of Intel® processors and chipsets, such as the Intel® Atom® processor(s) family or Intel-64 processors (for example, Sandy Bridge®, Ivy Bridge®, Haswell®, Broadwell®, Skylake®, etc.).

[0123] Additionally or alternatively, the devices, as described herein, may be used in connection with one or more additional memory chips. The memory may include one or more volatile and/or non-volatile memory devices including, but not limited to, magnetic storage devices, read-only memory (ROM), random access memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), double data rate (DDR) SDRAM (DDR-SDRAM), RAM-BUS DRAM (RDRAM), flash memory devices, electrically erasable programmable read-only memory (EEPROM), non-volatile RAM (NVRAM), universal serial bus (USB) removable memory, or combinations thereof.

[0124] In example embodiments, the electronic device in which the disclosed devices are used and/or provided may be a computing device. Such a computing device may house one or more boards on which the devices may be disposed. The board may include a number of components including, but not limited to, a processor and/or at least one communication chip. The processor may be physically and electrically connected to the board through, for example, electrical connections of the devices. The computing device may further include a plurality of communication chips. For instance, a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA,

WiMAX, LTE, EV-DO, and others. In various example embodiments, the computing device may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant

(PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, combinations thereof, or the like. In further example embodiments, the computing device may be any other electronic device that processes data.

[0125] Example 1 may include an integrated circuit (IC) structure comprising: an isolation structure on a substrate, the isolation structure including a trench; a semiconductor material in the trench; a channel on a portion of the semiconductor material, the channel including a first portion and a second portion; a drain on the first portion of the channel; a gate dielectric on the second portion of the channel; and a gate on the gate dielectric.

[0126] Example 2 may include the structure of example 1 and/or some other example herein, wherein the semiconductor material comprises a material that is latticed matched to the channel.

[0127] Example 3 may include the structure of example 1 and/or some other example herein, wherein the semiconductor material comprises p-doped germanium or p-doped silicon germanium.

[0128] Example 4 may include the structure of example 1 and/or some other example herein, wherein the channel comprises a III-V semiconductor or germanium.

[0129] Example 5 may include the structure of example 1 and/or some other example herein, wherein the substrate comprises p-doped silicon.

[0130] Example 6 may include the structure of example 1 and/or some other example herein, wherein the portion of the semiconductor material is a first portion, and wherein the structure further comprises a first contact on a second portion of the semiconductor material and a second contact on the drain.

[0131] Example 7 may include the structure of example 1 and/or some other example herein, wherein the trench comprises an aspect ratio trapping (ART) trench.

[0132] Example 8 may include the structure of example 1 and/or some other example herein, further comprising a first spacer between a sidewall of the gate dielectric and a sidewall of the second contact.

[0133] Example 9 may include the structure of example 1 and/or some other example herein, further comprising a second spacer between a sidewall of the channel and a sidewall of the first contact.

[0134] Example 10 may include a semiconductor device, comprising: an isolation structure on a substrate, the isolation structure including a trench; a channel in the trench, the channel including a first portion and a second portion; a drain on the first portion of the channel; a gate dielectric on the second portion of the channel; and a gate on the gate dielectric. [0135] Example 11 may include the device of example 10 and/or some other example herein, wherein the channel comprises a III-V semiconductor or germanium.

[0136] Example 12 may include the device of example 10 and/or some other example herein, wherein the substrate comprises p-doped silicon, germanium, gallium and antimony, silicon on insulator, germanium on insulator, or a III-V semiconductor on insulator.

[0137] Example 13 may include the device of example 10 and/or some other example herein, further comprising a first contact on the drain and a second contact on the substrate.

[0138] Example 14 may include the device of example 10 and/or some other example herein, wherein the trench comprises an aspect ratio trapping (ART) trench.

[0139] Example 15 may include the device of example 10 and/or some other example herein, further comprising a first spacer between a sidewall of the gate dielectric and a sidewall of the first contact.

[0140] Example 16 may include the device of example 10 and/or some other example herein, further comprising a second spacer between a sidewall of the channel and a sidewall of the second contact.

[0141] Example 17 may include a device including a vertical tunneling field effect transistor (TFET) device, the device comprising: an isolation structure on a substrate, the isolation structure including a trench; a semiconductor material in the trench; a channel on a portion of the semiconductor material, the channel including a first portion and a second portion; a drain on the first portion of the channel; a gate dielectric on the second portion of the channel; and a gate on the gate dielectric.

[0142] Example 18 may include the device of example 17 and/or some other example herein, wherein the semiconductor material comprises a material that is latticed matched to the channel.

[0143] Example 19 may include the device of example 17 and/or some other example herein, wherein the semiconductor material comprises p-doped germanium or p-doped silicon germanium.

[0144] Example 20 may include the device of example 17 and/or some other example herein, wherein the channel comprises a III-V semiconductor or germanium.

[0145] Example 21 may include the device of example 17 and/or some other example herein, wherein the substrate comprises p-doped silicon, germanium, gallium and antimony, silicon on insulator, germanium on insulator, or a III-V semiconductor on insulator.

[0146] Example 22 may include a device including a vertical tunneling field effect transistor

(TFET), the device comprising: an isolation structure on a substrate, the isolation structure including a trench; a channel in the trench, the channel including a first portion and a second portion; a drain on the first portion of the channel; a gate dielectric on the second portion of the channel; and a gate on the gate dielectric.

[0147] Example 23 may include the device of example 22 and/or some other example herein, wherein the channel comprises an a III-V semiconductor or germanium.

[0148] Example 24 may include the device of example 22 and/or some other example herein, wherein the substrate comprises p-doped silicon, germanium, gallium and antimony, silicon on insulator, germanium on insulator, or a III-V semiconductor on insulator.

[0149] Example 25 may include a device comprising an integrated circuit (IC) structure comprising: an isolation structure on a substrate, the isolation structure including a trench; a semiconductor material in the trench; a channel on a portion of the semiconductor material, the channel including a first portion and a second portion; a drain on the first portion of the channel; a gate dielectric on the second portion of the channel; and a gate on the gate dielectric.

[0150] Example 26 may include the device of example 25 and/or some other example herein, wherein the semiconductor material comprises a material that is latticed matched to the channel.

[0151] Example 27 may include the device of example 25 and/or some other example herein, wherein the semiconductor material comprises p-doped germanium or p-doped silicon germanium.

[0152] Example 28 may include the device of example 25 and/or some other example herein, wherein the channel comprises a III-V semiconductor or germanium.

[0153] Example 29 may include the device of example 25 and/or some other example herein, wherein the substrate comprises p-doped silicon.

[0154] Example 30 may include the device of example 25 and/or some other example herein, wherein the portion of the semiconductor material is a first portion, and wherein the structure further comprises a first contact on a second portion of the semiconductor material and a second contact on the drain.

[0155] Example 31 may include the device of example 25 and/or some other example herein, wherein the trench comprises an aspect ratio trapping (ART) trench.

[0156] Example 32 may include the device of example 25 and/or some other example herein, further comprising a first spacer between a sidewall of the gate dielectric and a sidewall of the second contact.

[0157] Example 33 may include the device of example 25 and/or some other example herein, further comprising a second spacer between a sidewall of the channel and a sidewall of the first contact. [0158] Various features, aspects, and embodiments have been described herein. The features, aspects, and embodiments are susceptible to combination with one another as well as to variation and modification, as will be understood by those having skill in the art. The present disclosure should, therefore, be considered to encompass such combinations, variations, and modifications.

[0159] The terms and expressions which have been employed herein are used as terms of description and not of limitation, and there is no intention, in the use of such terms and expressions, of excluding any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications are possible within the scope of the claims. Other modifications, variations, and alternatives are also possible. Accordingly, the claims are intended to cover all such equivalents.

[0160] While the disclosure includes various embodiments, including at least a best mode, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the foregoing description. Accordingly, the disclosure is intended to embrace all such alternatives, modifications, and variations, which fall within the scope of the included claims. All matters disclosed herein or shown in the accompanying drawings are to be interpreted in an illustrative and non-limiting sense.

[0161] This written description uses examples to disclose certain embodiments of the disclosure, including the best mode, and also to enable any person skilled in the art to practice certain embodiments of the disclosure, including making and using any apparatus, devices or systems and performing any incorporated methods and processes. The patentable scope of certain embodiments of the invention is defined in the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal language of the claims.