Title:
VIA ETCHING METHOD AND CIRCUIT DETECTION METHOD FOR THIN FILM TRANSISTOR ARRAY SUBSTRATE
Document Type and Number:
WIPO Patent Application WO/2020/211517
Kind Code:
A1
Abstract:
A via etching method and a circuit detection method for a thin film transistor array substrate. The via etching method comprises: adjusting an included angle between a base supporting a sample to be etched and the center of an ion beam for etching said sample to a preset angle of greater than 0 degrees and less than 90 degrees (S101); and etching a second film layer and a first film layer of said sample until an etched surface of the first film layer is sloped relative to a surface of the base so as to form a via extending through the second film layer and partially extending through the first film layer in the thickness direction thereof (S102). The invention prevents over-etching or under-etching of a first film layer, such that the first film layer can be effectively exposed at a via, thereby ensuring favorable electrical contact between an electrode subsequently formed in the via and the first film layer.
Inventors:
BAO ZHENG (CN)
WEI WENHAO (CN)
LIAO WENLI (CN)
FAN LEI (CN)
XIN YANXIA (CN)
LI XUEPING (CN)
HU HONGWEI (CN)
WU YIHAO (CN)
CHEN GONG (CN)
WEI WENHAO (CN)
LIAO WENLI (CN)
FAN LEI (CN)
XIN YANXIA (CN)
LI XUEPING (CN)
HU HONGWEI (CN)
WU YIHAO (CN)
CHEN GONG (CN)
Application Number:
PCT/CN2020/075608
Publication Date:
October 22, 2020
Filing Date:
February 17, 2020
Export Citation:
Assignee:
BOE TECHNOLOGY GROUP CO LTD (CN)
CHENGDU BOE OPTOELECT TECH CO (CN)
CHENGDU BOE OPTOELECT TECH CO (CN)
International Classes:
H01L21/3065; G01R31/28
Foreign References:
| CN110176397A | 2019-08-27 | |||
| CN109546012A | 2019-03-29 | |||
| CN101246132A | 2008-08-20 | |||
| US20040109128A1 | 2004-06-10 | |||
| CN101290900A | 2008-10-22 |
Attorney, Agent or Firm:
TDIP & PARTNERS (CN)
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